drivers/dma/xilinx/zynqmp_dma.c

   1 /*
   2  * DMA driver for Xilinx ZynqMP DMA Engine
   3  *
   4  * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/dmapool.h>
  14 #include <linux/dma/xilinx_dma.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_dma.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/io-64-nonatomic-lo-hi.h>
  26 #include <linux/pm_runtime.h>
  27
  28 #include "../dmaengine.h"
  29
  30 /* Register Offsets */
  31 #define ZYNQMP_DMA_ISR                  0x100
  32 #define ZYNQMP_DMA_IMR                  0x104
  33 #define ZYNQMP_DMA_IER                  0x108
  34 #define ZYNQMP_DMA_IDS                  0x10C
  35 #define ZYNQMP_DMA_CTRL0                0x110
  36 #define ZYNQMP_DMA_CTRL1                0x114
  37 #define ZYNQMP_DMA_DATA_ATTR            0x120
  38 #define ZYNQMP_DMA_DSCR_ATTR            0x124
  39 #define ZYNQMP_DMA_SRC_DSCR_WRD0        0x128
  40 #define ZYNQMP_DMA_SRC_DSCR_WRD1        0x12C
  41 #define ZYNQMP_DMA_SRC_DSCR_WRD2        0x130
  42 #define ZYNQMP_DMA_SRC_DSCR_WRD3        0x134
  43 #define ZYNQMP_DMA_DST_DSCR_WRD0        0x138
  44 #define ZYNQMP_DMA_DST_DSCR_WRD1        0x13C
  45 #define ZYNQMP_DMA_DST_DSCR_WRD2        0x140
  46 #define ZYNQMP_DMA_DST_DSCR_WRD3        0x144
  47 #define ZYNQMP_DMA_SRC_START_LSB        0x158
  48 #define ZYNQMP_DMA_SRC_START_MSB        0x15C
  49 #define ZYNQMP_DMA_DST_START_LSB        0x160
  50 #define ZYNQMP_DMA_DST_START_MSB        0x164
  51 #define ZYNQMP_DMA_TOTAL_BYTE           0x188
  52 #define ZYNQMP_DMA_RATE_CTRL            0x18C
  53 #define ZYNQMP_DMA_IRQ_SRC_ACCT         0x190
  54 #define ZYNQMP_DMA_IRQ_DST_ACCT         0x194
  55 #define ZYNQMP_DMA_CTRL2                0x200
  56
  57 /* Interrupt registers bit field definitions */
  58 #define ZYNQMP_DMA_DONE                 BIT(10)
  59 #define ZYNQMP_DMA_AXI_WR_DATA          BIT(9)
  60 #define ZYNQMP_DMA_AXI_RD_DATA          BIT(8)
  61 #define ZYNQMP_DMA_AXI_RD_DST_DSCR      BIT(7)
  62 #define ZYNQMP_DMA_AXI_RD_SRC_DSCR      BIT(6)
  63 #define ZYNQMP_DMA_IRQ_DST_ACCT_ERR     BIT(5)
  64 #define ZYNQMP_DMA_IRQ_SRC_ACCT_ERR     BIT(4)
  65 #define ZYNQMP_DMA_BYTE_CNT_OVRFL       BIT(3)
  66 #define ZYNQMP_DMA_DST_DSCR_DONE        BIT(2)
  67 #define ZYNQMP_DMA_INV_APB              BIT(0)
  68
  69 /* Control 0 register bit field definitions */
  70 #define ZYNQMP_DMA_OVR_FETCH            BIT(7)
  71 #define ZYNQMP_DMA_POINT_TYPE_SG        BIT(6)
  72 #define ZYNQMP_DMA_RATE_CTRL_EN         BIT(3)
  73
  74 /* Control 1 register bit field definitions */
  75 #define ZYNQMP_DMA_SRC_ISSUE            GENMASK(4, 0)
  76
  77 /* Data Attribute register bit field definitions */
  78 #define ZYNQMP_DMA_ARBURST              GENMASK(27, 26)
  79 #define ZYNQMP_DMA_ARCACHE              GENMASK(25, 22)
  80 #define ZYNQMP_DMA_ARCACHE_OFST         22
  81 #define ZYNQMP_DMA_ARQOS                GENMASK(21, 18)
  82 #define ZYNQMP_DMA_ARQOS_OFST           18
  83 #define ZYNQMP_DMA_ARLEN                GENMASK(17, 14)
  84 #define ZYNQMP_DMA_ARLEN_OFST           14
  85 #define ZYNQMP_DMA_AWBURST              GENMASK(13, 12)
  86 #define ZYNQMP_DMA_AWCACHE              GENMASK(11, 8)
  87 #define ZYNQMP_DMA_AWCACHE_OFST         8
  88 #define ZYNQMP_DMA_AWQOS                GENMASK(7, 4)
  89 #define ZYNQMP_DMA_AWQOS_OFST           4
  90 #define ZYNQMP_DMA_AWLEN                GENMASK(3, 0)
  91 #define ZYNQMP_DMA_AWLEN_OFST           0
  92
  93 /* Descriptor Attribute register bit field definitions */
  94 #define ZYNQMP_DMA_AXCOHRNT             BIT(8)
  95 #define ZYNQMP_DMA_AXCACHE              GENMASK(7, 4)
  96 #define ZYNQMP_DMA_AXCACHE_OFST         4
  97 #define ZYNQMP_DMA_AXQOS                GENMASK(3, 0)
  98 #define ZYNQMP_DMA_AXQOS_OFST           0
  99
 100 /* Control register 2 bit field definitions */
 101 #define ZYNQMP_DMA_ENABLE               BIT(0)
 102
 103 /* Buffer Descriptor definitions */
 104 #define ZYNQMP_DMA_DESC_CTRL_STOP       0x10
 105 #define ZYNQMP_DMA_DESC_CTRL_COMP_INT   0x4
 106 #define ZYNQMP_DMA_DESC_CTRL_SIZE_256   0x2
 107 #define ZYNQMP_DMA_DESC_CTRL_COHRNT     0x1
 108
 109 /* Interrupt Mask specific definitions */
 110 #define ZYNQMP_DMA_INT_ERR      (ZYNQMP_DMA_AXI_RD_DATA | \
 111                                 ZYNQMP_DMA_AXI_WR_DATA | \
 112                                 ZYNQMP_DMA_AXI_RD_DST_DSCR | \
 113                                 ZYNQMP_DMA_AXI_RD_SRC_DSCR | \
 114                                 ZYNQMP_DMA_INV_APB)
 115 #define ZYNQMP_DMA_INT_OVRFL    (ZYNQMP_DMA_BYTE_CNT_OVRFL | \
 116                                 ZYNQMP_DMA_IRQ_SRC_ACCT_ERR | \
 117                                 ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
 118 #define ZYNQMP_DMA_INT_DONE     (ZYNQMP_DMA_DONE | ZYNQMP_DMA_DST_DSCR_DONE)
 119 #define ZYNQMP_DMA_INT_EN_DEFAULT_MASK  (ZYNQMP_DMA_INT_DONE | \
 120                                         ZYNQMP_DMA_INT_ERR | \
 121                                         ZYNQMP_DMA_INT_OVRFL | \
 122                                         ZYNQMP_DMA_DST_DSCR_DONE)
 123
 124 /* Max number of descriptors per channel */
 125 #define ZYNQMP_DMA_NUM_DESCS    32
 126
 127 /* Max transfer size per descriptor */
 128 #define ZYNQMP_DMA_MAX_TRANS_LEN        0x40000000
 129
 130 /* Reset values for data attributes */
 131 #define ZYNQMP_DMA_AXCACHE_VAL          0xF
 132 #define ZYNQMP_DMA_ARLEN_RST_VAL        0xF
 133 #define ZYNQMP_DMA_AWLEN_RST_VAL        0xF
 134
 135 #define ZYNQMP_DMA_SRC_ISSUE_RST_VAL    0x1F
 136
 137 #define ZYNQMP_DMA_IDS_DEFAULT_MASK     0xFFF
 138
 139 /* Bus width in bits */
 140 #define ZYNQMP_DMA_BUS_WIDTH_64         64
 141 #define ZYNQMP_DMA_BUS_WIDTH_128        128
 142
 143 #define ZDMA_PM_TIMEOUT                 100
 144
 145 #define ZYNQMP_DMA_DESC_SIZE(chan)      (chan->desc_size)
 146
 147 #define to_chan(chan)           container_of(chan, struct zynqmp_dma_chan, \
 148                                              common)
 149 #define tx_to_desc(tx)          container_of(tx, struct zynqmp_dma_desc_sw, \
 150                                              async_tx)
 151
 152 /**
 153  * struct zynqmp_dma_desc_ll - Hw linked list descriptor
 154  * @addr: Buffer address
 155  * @size: Size of the buffer
 156  * @ctrl: Control word
 157  * @nxtdscraddr: Next descriptor base address
 158  * @rsvd: Reserved field and for Hw internal use.
 159  */
 160 struct zynqmp_dma_desc_ll {
 161         u64 addr;
 162         u32 size;
 163         u32 ctrl;
 164         u64 nxtdscraddr;
 165         u64 rsvd;
 166 }; __aligned(64)
 167
 168 /**
 169  * struct zynqmp_dma_desc_sw - Per Transaction structure
 170  * @src: Source address for simple mode dma
 171  * @dst: Destination address for simple mode dma
 172  * @len: Transfer length for simple mode dma
 173  * @node: Node in the channel descriptor list
 174  * @tx_list: List head for the current transfer
 175  * @async_tx: Async transaction descriptor
 176  * @src_v: Virtual address of the src descriptor
 177  * @src_p: Physical address of the src descriptor
 178  * @dst_v: Virtual address of the dst descriptor
 179  * @dst_p: Physical address of the dst descriptor
 180  */
 181 struct zynqmp_dma_desc_sw {
 182         u64 src;
 183         u64 dst;
 184         u32 len;
 185         struct list_head node;
 186         struct list_head tx_list;
 187         struct dma_async_tx_descriptor async_tx;
 188         struct zynqmp_dma_desc_ll *src_v;
 189         dma_addr_t src_p;
 190         struct zynqmp_dma_desc_ll *dst_v;
 191         dma_addr_t dst_p;
 192 };
 193
 194 /**
 195  * struct zynqmp_dma_chan - Driver specific DMA channel structure
 196  * @zdev: Driver specific device structure
 197  * @regs: Control registers offset
 198  * @lock: Descriptor operation lock
 199  * @pending_list: Descriptors waiting
 200  * @free_list: Descriptors free
 201  * @active_list: Descriptors active
 202  * @sw_desc_pool: SW descriptor pool
 203  * @done_list: Complete descriptors
 204  * @common: DMA common channel
 205  * @desc_pool_v: Statically allocated descriptor base
 206  * @desc_pool_p: Physical allocated descriptor base
 207  * @desc_free_cnt: Descriptor available count
 208  * @dev: The dma device
 209  * @irq: Channel IRQ
 210  * @is_dmacoherent: Tells whether dma operations are coherent or not
 211  * @tasklet: Cleanup work after irq
 212  * @idle : Channel status;
 213  * @desc_size: Size of the low level descriptor
 214  * @err: Channel has errors
 215  * @bus_width: Bus width
 216  * @src_burst_len: Source burst length
 217  * @dst_burst_len: Dest burst length
 218  */
 219 struct zynqmp_dma_chan {
 220         struct zynqmp_dma_device *zdev;
 221         void __iomem *regs;
 222         spinlock_t lock;
 223         struct list_head pending_list;
 224         struct list_head free_list;
 225         struct list_head active_list;
 226         struct zynqmp_dma_desc_sw *sw_desc_pool;
 227         struct list_head done_list;
 228         struct dma_chan common;
 229         void *desc_pool_v;
 230         dma_addr_t desc_pool_p;
 231         u32 desc_free_cnt;
 232         struct device *dev;
 233         int irq;
 234         bool is_dmacoherent;
 235         struct tasklet_struct tasklet;
 236         bool idle;
 237         u32 desc_size;
 238         bool err;
 239         u32 bus_width;
 240         u32 src_burst_len;
 241         u32 dst_burst_len;
 242 };
 243
 244 /**
 245  * struct zynqmp_dma_device - DMA device structure
 246  * @dev: Device Structure
 247  * @common: DMA device structure
 248  * @chan: Driver specific DMA channel
 249  * @clk_main: Pointer to main clock
 250  * @clk_apb: Pointer to apb clock
 251  */
 252 struct zynqmp_dma_device {
 253         struct device *dev;
 254         struct dma_device common;
 255         struct zynqmp_dma_chan *chan;
 256         struct clk *clk_main;
 257         struct clk *clk_apb;
 258 };
 259
 260 static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg,
 261                                      u64 value)
 262 {
 263         lo_hi_writeq(value, chan->regs + reg);
 264 }
 265
 266 /**
 267  * zynqmp_dma_update_desc_to_ctrlr - Updates descriptor to the controller
 268  * @chan: ZynqMP DMA DMA channel pointer
 269  * @desc: Transaction descriptor pointer
 270  */
 271 static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan,
 272                                       struct zynqmp_dma_desc_sw *desc)
 273 {
 274         dma_addr_t addr;
 275
 276         addr = desc->src_p;
 277         zynqmp_dma_writeq(chan, ZYNQMP_DMA_SRC_START_LSB, addr);
 278         addr = desc->dst_p;
 279         zynqmp_dma_writeq(chan, ZYNQMP_DMA_DST_START_LSB, addr);
 280 }
 281
 282 /**
 283  * zynqmp_dma_desc_config_eod - Mark the descriptor as end descriptor
 284  * @chan: ZynqMP DMA channel pointer
 285  * @desc: Hw descriptor pointer
 286  */
 287 static void zynqmp_dma_desc_config_eod(struct zynqmp_dma_chan *chan,
 288                                        void *desc)
 289 {
 290         struct zynqmp_dma_desc_ll *hw = (struct zynqmp_dma_desc_ll *)desc;
 291
 292         hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_STOP;
 293         hw++;
 294         hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_COMP_INT | ZYNQMP_DMA_DESC_CTRL_STOP;
 295 }
 296
 297 /**
 298  * zynqmp_dma_config_sg_ll_desc - Configure the linked list descriptor
 299  * @chan: ZynqMP DMA channel pointer
 300  * @sdesc: Hw descriptor pointer
 301  * @src: Source buffer address
 302  * @dst: Destination buffer address
 303  * @len: Transfer length
 304  * @prev: Previous hw descriptor pointer
 305  */
 306 static void zynqmp_dma_config_sg_ll_desc(struct zynqmp_dma_chan *chan,
 307                                    struct zynqmp_dma_desc_ll *sdesc,
 308                                    dma_addr_t src, dma_addr_t dst, size_t len,
 309                                    struct zynqmp_dma_desc_ll *prev)
 310 {
 311         struct zynqmp_dma_desc_ll *ddesc = sdesc + 1;
 312
 313         sdesc->size = ddesc->size = len;
 314         sdesc->addr = src;
 315         ddesc->addr = dst;
 316
 317         sdesc->ctrl = ddesc->ctrl = ZYNQMP_DMA_DESC_CTRL_SIZE_256;
 318         if (chan->is_dmacoherent) {
 319                 sdesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
 320                 ddesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
 321         }
 322
 323         if (prev) {
 324                 dma_addr_t addr = chan->desc_pool_p +
 325                             ((uintptr_t)sdesc - (uintptr_t)chan->desc_pool_v);
 326                 ddesc = prev + 1;
 327                 prev->nxtdscraddr = addr;
 328                 ddesc->nxtdscraddr = addr + ZYNQMP_DMA_DESC_SIZE(chan);
 329         }
 330 }
 331
 332 /**
 333  * zynqmp_dma_init - Initialize the channel
 334  * @chan: ZynqMP DMA channel pointer
 335  */
 336 static void zynqmp_dma_init(struct zynqmp_dma_chan *chan)
 337 {
 338         u32 val;
 339
 340         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 341         val = readl(chan->regs + ZYNQMP_DMA_ISR);
 342         writel(val, chan->regs + ZYNQMP_DMA_ISR);
 343
 344         if (chan->is_dmacoherent) {
 345                 val = ZYNQMP_DMA_AXCOHRNT;
 346                 val = (val & ~ZYNQMP_DMA_AXCACHE) |
 347                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AXCACHE_OFST);
 348                 writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR);
 349         }
 350
 351         val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
 352         if (chan->is_dmacoherent) {
 353                 val = (val & ~ZYNQMP_DMA_ARCACHE) |
 354                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_ARCACHE_OFST);
 355                 val = (val & ~ZYNQMP_DMA_AWCACHE) |
 356                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AWCACHE_OFST);
 357         }
 358         writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
 359
 360         /* Clearing the interrupt account rgisters */
 361         val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
 362         val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 363
 364         chan->idle = true;
 365 }
 366
 367 /**
 368  * zynqmp_dma_tx_submit - Submit DMA transaction
 369  * @tx: Async transaction descriptor pointer
 370  *
 371  * Return: cookie value
 372  */
 373 static dma_cookie_t zynqmp_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 374 {
 375         struct zynqmp_dma_chan *chan = to_chan(tx->chan);
 376         struct zynqmp_dma_desc_sw *desc, *new;
 377         dma_cookie_t cookie;
 378
 379         new = tx_to_desc(tx);
 380         spin_lock_bh(&chan->lock);
 381         cookie = dma_cookie_assign(tx);
 382
 383         if (!list_empty(&chan->pending_list)) {
 384                 desc = list_last_entry(&chan->pending_list,
 385                                      struct zynqmp_dma_desc_sw, node);
 386                 if (!list_empty(&desc->tx_list))
 387                         desc = list_last_entry(&desc->tx_list,
 388                                                struct zynqmp_dma_desc_sw, node);
 389                 desc->src_v->nxtdscraddr = new->src_p;
 390                 desc->src_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
 391                 desc->dst_v->nxtdscraddr = new->dst_p;
 392                 desc->dst_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
 393         }
 394
 395         list_add_tail(&new->node, &chan->pending_list);
 396         spin_unlock_bh(&chan->lock);
 397
 398         return cookie;
 399 }
 400
 401 /**
 402  * zynqmp_dma_get_descriptor - Get the sw descriptor from the pool
 403  * @chan: ZynqMP DMA channel pointer
 404  *
 405  * Return: The sw descriptor
 406  */
 407 static struct zynqmp_dma_desc_sw *
 408 zynqmp_dma_get_descriptor(struct zynqmp_dma_chan *chan)
 409 {
 410         struct zynqmp_dma_desc_sw *desc;
 411
 412         spin_lock_bh(&chan->lock);
 413         desc = list_first_entry(&chan->free_list,
 414                                 struct zynqmp_dma_desc_sw, node);
 415         list_del(&desc->node);
 416         spin_unlock_bh(&chan->lock);
 417
 418         INIT_LIST_HEAD(&desc->tx_list);
 419         /* Clear the src and dst descriptor memory */
 420         memset((void *)desc->src_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
 421         memset((void *)desc->dst_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
 422
 423         return desc;
 424 }
 425
 426 /**
 427  * zynqmp_dma_free_descriptor - Issue pending transactions
 428  * @chan: ZynqMP DMA channel pointer
 429  * @sdesc: Transaction descriptor pointer
 430  */
 431 static void zynqmp_dma_free_descriptor(struct zynqmp_dma_chan *chan,
 432                                  struct zynqmp_dma_desc_sw *sdesc)
 433 {
 434         struct zynqmp_dma_desc_sw *child, *next;
 435
 436         chan->desc_free_cnt++;
 437         list_add_tail(&sdesc->node, &chan->free_list);
 438         list_for_each_entry_safe(child, next, &sdesc->tx_list, node) {
 439                 chan->desc_free_cnt++;
 440                 list_move_tail(&child->node, &chan->free_list);
 441         }
 442 }
 443
 444 /**
 445  * zynqmp_dma_free_desc_list - Free descriptors list
 446  * @chan: ZynqMP DMA channel pointer
 447  * @list: List to parse and delete the descriptor
 448  */
 449 static void zynqmp_dma_free_desc_list(struct zynqmp_dma_chan *chan,
 450                                       struct list_head *list)
 451 {
 452         struct zynqmp_dma_desc_sw *desc, *next;
 453
 454         list_for_each_entry_safe(desc, next, list, node)
 455                 zynqmp_dma_free_descriptor(chan, desc);
 456 }
 457
 458 /**
 459  * zynqmp_dma_alloc_chan_resources - Allocate channel resources
 460  * @dchan: DMA channel
 461  *
 462  * Return: Number of descriptors on success and failure value on error
 463  */
 464 static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan)
 465 {
 466         struct zynqmp_dma_chan *chan = to_chan(dchan);
 467         struct zynqmp_dma_desc_sw *desc;
 468         int i, ret;
 469
 470         ret = pm_runtime_get_sync(chan->dev);
 471         if (ret < 0)
 472                 return ret;
 473
 474         chan->sw_desc_pool = kcalloc(ZYNQMP_DMA_NUM_DESCS, sizeof(*desc),
 475                                      GFP_KERNEL);
 476         if (!chan->sw_desc_pool)
 477                 return -ENOMEM;
 478
 479         chan->idle = true;
 480         chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS;
 481
 482         INIT_LIST_HEAD(&chan->free_list);
 483
 484         for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
 485                 desc = chan->sw_desc_pool + i;
 486                 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
 487                 desc->async_tx.tx_submit = zynqmp_dma_tx_submit;
 488                 list_add_tail(&desc->node, &chan->free_list);
 489         }
 490
 491         chan->desc_pool_v = dma_zalloc_coherent(chan->dev,
 492                                 (2 * chan->desc_size * ZYNQMP_DMA_NUM_DESCS),
 493                                 &chan->desc_pool_p, GFP_KERNEL);
 494         if (!chan->desc_pool_v)
 495                 return -ENOMEM;
 496
 497         for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
 498                 desc = chan->sw_desc_pool + i;
 499                 desc->src_v = (struct zynqmp_dma_desc_ll *) (chan->desc_pool_v +
 500                                         (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2));
 501                 desc->dst_v = (struct zynqmp_dma_desc_ll *) (desc->src_v + 1);
 502                 desc->src_p = chan->desc_pool_p +
 503                                 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2);
 504                 desc->dst_p = desc->src_p + ZYNQMP_DMA_DESC_SIZE(chan);
 505         }
 506
 507         return ZYNQMP_DMA_NUM_DESCS;
 508 }
 509
 510 /**
 511  * zynqmp_dma_start - Start DMA channel
 512  * @chan: ZynqMP DMA channel pointer
 513  */
 514 static void zynqmp_dma_start(struct zynqmp_dma_chan *chan)
 515 {
 516         writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER);
 517         writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
 518         chan->idle = false;
 519         writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2);
 520 }
 521
 522 /**
 523  * zynqmp_dma_handle_ovfl_int - Process the overflow interrupt
 524  * @chan: ZynqMP DMA channel pointer
 525  * @status: Interrupt status value
 526  */
 527 static void zynqmp_dma_handle_ovfl_int(struct zynqmp_dma_chan *chan, u32 status)
 528 {
 529         if (status & ZYNQMP_DMA_BYTE_CNT_OVRFL)
 530                 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
 531         if (status & ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
 532                 readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 533         if (status & ZYNQMP_DMA_IRQ_SRC_ACCT_ERR)
 534                 readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
 535 }
 536
 537 static void zynqmp_dma_config(struct zynqmp_dma_chan *chan)
 538 {
 539         u32 val;
 540
 541         val = readl(chan->regs + ZYNQMP_DMA_CTRL0);
 542         val |= ZYNQMP_DMA_POINT_TYPE_SG;
 543         writel(val, chan->regs + ZYNQMP_DMA_CTRL0);
 544
 545         val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
 546         val = (val & ~ZYNQMP_DMA_ARLEN) |
 547                 (chan->src_burst_len << ZYNQMP_DMA_ARLEN_OFST);
 548         val = (val & ~ZYNQMP_DMA_AWLEN) |
 549                 (chan->dst_burst_len << ZYNQMP_DMA_AWLEN_OFST);
 550         writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
 551 }
 552
 553 /**
 554  * zynqmp_dma_device_config - Zynqmp dma device configuration
 555  * @dchan: DMA channel
 556  * @config: DMA device config
 557  *
 558  * Return: 0 always
 559  */
 560 static int zynqmp_dma_device_config(struct dma_chan *dchan,
 561                                     struct dma_slave_config *config)
 562 {
 563         struct zynqmp_dma_chan *chan = to_chan(dchan);
 564
 565         chan->src_burst_len = config->src_maxburst;
 566         chan->dst_burst_len = config->dst_maxburst;
 567
 568         return 0;
 569 }
 570
 571 /**
 572  * zynqmp_dma_start_transfer - Initiate the new transfer
 573  * @chan: ZynqMP DMA channel pointer
 574  */
 575 static void zynqmp_dma_start_transfer(struct zynqmp_dma_chan *chan)
 576 {
 577         struct zynqmp_dma_desc_sw *desc;
 578
 579         if (!chan->idle)
 580                 return;
 581
 582         zynqmp_dma_config(chan);
 583
 584         desc = list_first_entry_or_null(&chan->pending_list,
 585                                         struct zynqmp_dma_desc_sw, node);
 586         if (!desc)
 587                 return;
 588
 589         list_splice_tail_init(&chan->pending_list, &chan->active_list);
 590         zynqmp_dma_update_desc_to_ctrlr(chan, desc);
 591         zynqmp_dma_start(chan);
 592 }
 593
 594
 595 /**
 596  * zynqmp_dma_chan_desc_cleanup - Cleanup the completed descriptors
 597  * @chan: ZynqMP DMA channel
 598  */
 599 static void zynqmp_dma_chan_desc_cleanup(struct zynqmp_dma_chan *chan)
 600 {
 601         struct zynqmp_dma_desc_sw *desc, *next;
 602
 603         list_for_each_entry_safe(desc, next, &chan->done_list, node) {
 604                 dma_async_tx_callback callback;
 605                 void *callback_param;
 606
 607                 list_del(&desc->node);
 608
 609                 callback = desc->async_tx.callback;
 610                 callback_param = desc->async_tx.callback_param;
 611                 if (callback) {
 612                         spin_unlock(&chan->lock);
 613                         callback(callback_param);
 614                         spin_lock(&chan->lock);
 615                 }
 616
 617                 /* Run any dependencies, then free the descriptor */
 618                 zynqmp_dma_free_descriptor(chan, desc);
 619         }
 620 }
 621
 622 /**
 623  * zynqmp_dma_complete_descriptor - Mark the active descriptor as complete
 624  * @chan: ZynqMP DMA channel pointer
 625  */
 626 static void zynqmp_dma_complete_descriptor(struct zynqmp_dma_chan *chan)
 627 {
 628         struct zynqmp_dma_desc_sw *desc;
 629
 630         desc = list_first_entry_or_null(&chan->active_list,
 631                                         struct zynqmp_dma_desc_sw, node);
 632         if (!desc)
 633                 return;
 634         list_del(&desc->node);
 635         dma_cookie_complete(&desc->async_tx);
 636         list_add_tail(&desc->node, &chan->done_list);
 637 }
 638
 639 /**
 640  * zynqmp_dma_issue_pending - Issue pending transactions
 641  * @dchan: DMA channel pointer
 642  */
 643 static void zynqmp_dma_issue_pending(struct dma_chan *dchan)
 644 {
 645         struct zynqmp_dma_chan *chan = to_chan(dchan);
 646
 647         spin_lock_bh(&chan->lock);
 648         zynqmp_dma_start_transfer(chan);
 649         spin_unlock_bh(&chan->lock);
 650 }
 651
 652 /**
 653  * zynqmp_dma_free_descriptors - Free channel descriptors
 654  * @chan: ZynqMP DMA channel pointer
 655  */
 656 static void zynqmp_dma_free_descriptors(struct zynqmp_dma_chan *chan)
 657 {
 658         zynqmp_dma_free_desc_list(chan, &chan->active_list);
 659         zynqmp_dma_free_desc_list(chan, &chan->pending_list);
 660         zynqmp_dma_free_desc_list(chan, &chan->done_list);
 661 }
 662
 663 /**
 664  * zynqmp_dma_free_chan_resources - Free channel resources
 665  * @dchan: DMA channel pointer
 666  */
 667 static void zynqmp_dma_free_chan_resources(struct dma_chan *dchan)
 668 {
 669         struct zynqmp_dma_chan *chan = to_chan(dchan);
 670
 671         spin_lock_bh(&chan->lock);
 672         zynqmp_dma_free_descriptors(chan);
 673         spin_unlock_bh(&chan->lock);
 674         dma_free_coherent(chan->dev,
 675                 (2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS),
 676                 chan->desc_pool_v, chan->desc_pool_p);
 677         kfree(chan->sw_desc_pool);
 678         pm_runtime_mark_last_busy(chan->dev);
 679         pm_runtime_put_autosuspend(chan->dev);
 680 }
 681
 682 /**
 683  * zynqmp_dma_reset - Reset the channel
 684  * @chan: ZynqMP DMA channel pointer
 685  */
 686 static void zynqmp_dma_reset(struct zynqmp_dma_chan *chan)
 687 {
 688         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 689
 690         zynqmp_dma_complete_descriptor(chan);
 691         zynqmp_dma_chan_desc_cleanup(chan);
 692         zynqmp_dma_free_descriptors(chan);
 693         zynqmp_dma_init(chan);
 694 }
 695
 696 /**
 697  * zynqmp_dma_irq_handler - ZynqMP DMA Interrupt handler
 698  * @irq: IRQ number
 699  * @data: Pointer to the ZynqMP DMA channel structure
 700  *
 701  * Return: IRQ_HANDLED/IRQ_NONE
 702  */
 703 static irqreturn_t zynqmp_dma_irq_handler(int irq, void *data)
 704 {
 705         struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
 706         u32 isr, imr, status;
 707         irqreturn_t ret = IRQ_NONE;
 708
 709         isr = readl(chan->regs + ZYNQMP_DMA_ISR);
 710         imr = readl(chan->regs + ZYNQMP_DMA_IMR);
 711         status = isr & ~imr;
 712
 713         writel(isr, chan->regs + ZYNQMP_DMA_ISR);
 714         if (status & ZYNQMP_DMA_INT_DONE) {
 715                 tasklet_schedule(&chan->tasklet);
 716                 ret = IRQ_HANDLED;
 717         }
 718
 719         if (status & ZYNQMP_DMA_DONE)
 720                 chan->idle = true;
 721
 722         if (status & ZYNQMP_DMA_INT_ERR) {
 723                 chan->err = true;
 724                 tasklet_schedule(&chan->tasklet);
 725                 dev_err(chan->dev, "Channel %p has errors\n", chan);
 726                 ret = IRQ_HANDLED;
 727         }
 728
 729         if (status & ZYNQMP_DMA_INT_OVRFL) {
 730                 zynqmp_dma_handle_ovfl_int(chan, status);
 731                 dev_dbg(chan->dev, "Channel %p overflow interrupt\n", chan);
 732                 ret = IRQ_HANDLED;
 733         }
 734
 735         return ret;
 736 }
 737
 738 /**
 739  * zynqmp_dma_do_tasklet - Schedule completion tasklet
 740  * @data: Pointer to the ZynqMP DMA channel structure
 741  */
 742 static void zynqmp_dma_do_tasklet(unsigned long data)
 743 {
 744         struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
 745         u32 count;
 746
 747         spin_lock(&chan->lock);
 748
 749         if (chan->err) {
 750                 zynqmp_dma_reset(chan);
 751                 chan->err = false;
 752                 goto unlock;
 753         }
 754
 755         count = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 756
 757         while (count) {
 758                 zynqmp_dma_complete_descriptor(chan);
 759                 zynqmp_dma_chan_desc_cleanup(chan);
 760                 count--;
 761         }
 762
 763         if (chan->idle)
 764                 zynqmp_dma_start_transfer(chan);
 765
 766 unlock:
 767         spin_unlock(&chan->lock);
 768 }
 769
 770 /**
 771  * zynqmp_dma_device_terminate_all - Aborts all transfers on a channel
 772  * @dchan: DMA channel pointer
 773  *
 774  * Return: Always '0'
 775  */
 776 static int zynqmp_dma_device_terminate_all(struct dma_chan *dchan)
 777 {
 778         struct zynqmp_dma_chan *chan = to_chan(dchan);
 779
 780         spin_lock_bh(&chan->lock);
 781         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 782         zynqmp_dma_free_descriptors(chan);
 783         spin_unlock_bh(&chan->lock);
 784
 785         return 0;
 786 }
 787
 788 /**
 789  * zynqmp_dma_prep_memcpy - prepare descriptors for memcpy transaction
 790  * @dchan: DMA channel
 791  * @dma_dst: Destination buffer address
 792  * @dma_src: Source buffer address
 793  * @len: Transfer length
 794  * @flags: transfer ack flags
 795  *
 796  * Return: Async transaction descriptor on success and NULL on failure
 797  */
 798 static struct dma_async_tx_descriptor *zynqmp_dma_prep_memcpy(
 799                                 struct dma_chan *dchan, dma_addr_t dma_dst,
 800                                 dma_addr_t dma_src, size_t len, ulong flags)
 801 {
 802         struct zynqmp_dma_chan *chan;
 803         struct zynqmp_dma_desc_sw *new, *first = NULL;
 804         void *desc = NULL, *prev = NULL;
 805         size_t copy;
 806         u32 desc_cnt;
 807
 808         chan = to_chan(dchan);
 809
 810         desc_cnt = DIV_ROUND_UP(len, ZYNQMP_DMA_MAX_TRANS_LEN);
 811
 812         spin_lock_bh(&chan->lock);
 813         if (desc_cnt > chan->desc_free_cnt) {
 814                 spin_unlock_bh(&chan->lock);
 815                 dev_dbg(chan->dev, "chan %p descs are not available\n", chan);
 816                 return NULL;
 817         }
 818         chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt;
 819         spin_unlock_bh(&chan->lock);
 820
 821         do {
 822                 /* Allocate and populate the descriptor */
 823                 new = zynqmp_dma_get_descriptor(chan);
 824
 825                 copy = min_t(size_t, len, ZYNQMP_DMA_MAX_TRANS_LEN);
 826                 desc = (struct zynqmp_dma_desc_ll *)new->src_v;
 827                 zynqmp_dma_config_sg_ll_desc(chan, desc, dma_src,
 828                                              dma_dst, copy, prev);
 829                 prev = desc;
 830                 len -= copy;
 831                 dma_src += copy;
 832                 dma_dst += copy;
 833                 if (!first)
 834                         first = new;
 835                 else
 836                         list_add_tail(&new->node, &first->tx_list);
 837         } while (len);
 838
 839         zynqmp_dma_desc_config_eod(chan, desc);
 840         async_tx_ack(&first->async_tx);
 841         first->async_tx.flags = flags;
 842         return &first->async_tx;
 843 }
 844
 845 /**
 846  * zynqmp_dma_chan_remove - Channel remove function
 847  * @chan: ZynqMP DMA channel pointer
 848  */
 849 static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan)
 850 {
 851         if (!chan)
 852                 return;
 853
 854         if (chan->irq)
 855                 devm_free_irq(chan->zdev->dev, chan->irq, chan);
 856         tasklet_kill(&chan->tasklet);
 857         list_del(&chan->common.device_node);
 858 }
 859
 860 /**
 861  * zynqmp_dma_chan_probe - Per Channel Probing
 862  * @zdev: Driver specific device structure
 863  * @pdev: Pointer to the platform_device structure
 864  *
 865  * Return: '0' on success and failure value on error
 866  */
 867 static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev,
 868                            struct platform_device *pdev)
 869 {
 870         struct zynqmp_dma_chan *chan;
 871         struct resource *res;
 872         struct device_node *node = pdev->dev.of_node;
 873         int err;
 874
 875         chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
 876         if (!chan)
 877                 return -ENOMEM;
 878         chan->dev = zdev->dev;
 879         chan->zdev = zdev;
 880
 881         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 882         chan->regs = devm_ioremap_resource(&pdev->dev, res);
 883         if (IS_ERR(chan->regs))
 884                 return PTR_ERR(chan->regs);
 885
 886         chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
 887         chan->dst_burst_len = ZYNQMP_DMA_AWLEN_RST_VAL;
 888         chan->src_burst_len = ZYNQMP_DMA_ARLEN_RST_VAL;
 889         err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width);
 890         if (err < 0) {
 891                 dev_err(&pdev->dev, "missing xlnx,bus-width property\n");
 892                 return err;
 893         }
 894
 895         if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 &&
 896             chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) {
 897                 dev_err(zdev->dev, "invalid bus-width value");
 898                 return -EINVAL;
 899         }
 900
 901         chan->is_dmacoherent =  of_property_read_bool(node, "dma-coherent");
 902         zdev->chan = chan;
 903         tasklet_init(&chan->tasklet, zynqmp_dma_do_tasklet, (ulong)chan);
 904         spin_lock_init(&chan->lock);
 905         INIT_LIST_HEAD(&chan->active_list);
 906         INIT_LIST_HEAD(&chan->pending_list);
 907         INIT_LIST_HEAD(&chan->done_list);
 908         INIT_LIST_HEAD(&chan->free_list);
 909
 910         dma_cookie_init(&chan->common);
 911         chan->common.device = &zdev->common;
 912         list_add_tail(&chan->common.device_node, &zdev->common.channels);
 913
 914         zynqmp_dma_init(chan);
 915         chan->irq = platform_get_irq(pdev, 0);
 916         if (chan->irq < 0)
 917                 return -ENXIO;
 918         err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0,
 919                                "zynqmp-dma", chan);
 920         if (err)
 921                 return err;
 922
 923         chan->desc_size = sizeof(struct zynqmp_dma_desc_ll);
 924         chan->idle = true;
 925         return 0;
 926 }
 927
 928 /**
 929  * of_zynqmp_dma_xlate - Translation function
 930  * @dma_spec: Pointer to DMA specifier as found in the device tree
 931  * @ofdma: Pointer to DMA controller data
 932  *
 933  * Return: DMA channel pointer on success and NULL on error
 934  */
 935 static struct dma_chan *of_zynqmp_dma_xlate(struct of_phandle_args *dma_spec,
 936                                             struct of_dma *ofdma)
 937 {
 938         struct zynqmp_dma_device *zdev = ofdma->of_dma_data;
 939
 940         return dma_get_slave_channel(&zdev->chan->common);
 941 }
 942
 943 /**
 944  * zynqmp_dma_suspend - Suspend method for the driver
 945  * @dev:        Address of the device structure
 946  *
 947  * Put the driver into low power mode.
 948  * Return: 0 on success and failure value on error
 949  */
 950 static int __maybe_unused zynqmp_dma_suspend(struct device *dev)
 951 {
 952         if (!device_may_wakeup(dev))
 953                 return pm_runtime_force_suspend(dev);
 954
 955         return 0;
 956 }
 957
 958 /**
 959  * zynqmp_dma_resume - Resume from suspend
 960  * @dev:        Address of the device structure
 961  *
 962  * Resume operation after suspend.
 963  * Return: 0 on success and failure value on error
 964  */
 965 static int __maybe_unused zynqmp_dma_resume(struct device *dev)
 966 {
 967         if (!device_may_wakeup(dev))
 968                 return pm_runtime_force_resume(dev);
 969
 970         return 0;
 971 }
 972
 973 /**
 974  * zynqmp_dma_runtime_suspend - Runtime suspend method for the driver
 975  * @dev:        Address of the device structure
 976  *
 977  * Put the driver into low power mode.
 978  * Return: 0 always
 979  */
 980 static int __maybe_unused zynqmp_dma_runtime_suspend(struct device *dev)
 981 {
 982         struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
 983
 984         clk_disable_unprepare(zdev->clk_main);
 985         clk_disable_unprepare(zdev->clk_apb);
 986
 987         return 0;
 988 }
 989
 990 /**
 991  * zynqmp_dma_runtime_resume - Runtime suspend method for the driver
 992  * @dev:        Address of the device structure
 993  *
 994  * Put the driver into low power mode.
 995  * Return: 0 always
 996  */
 997 static int __maybe_unused zynqmp_dma_runtime_resume(struct device *dev)
 998 {
 999         struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
1000         int err;
1001
1002         err = clk_prepare_enable(zdev->clk_main);
1003         if (err) {
1004                 dev_err(dev, "Unable to enable main clock.\n");
1005                 return err;
1006         }
1007
1008         err = clk_prepare_enable(zdev->clk_apb);
1009         if (err) {
1010                 dev_err(dev, "Unable to enable apb clock.\n");
1011                 clk_disable_unprepare(zdev->clk_main);
1012                 return err;
1013         }
1014
1015         return 0;
1016 }
1017
1018 static const struct dev_pm_ops zynqmp_dma_dev_pm_ops = {
1019         SET_SYSTEM_SLEEP_PM_OPS(zynqmp_dma_suspend, zynqmp_dma_resume)
1020         SET_RUNTIME_PM_OPS(zynqmp_dma_runtime_suspend,
1021                            zynqmp_dma_runtime_resume, NULL)
1022 };
1023
1024 /**
1025  * zynqmp_dma_probe - Driver probe function
1026  * @pdev: Pointer to the platform_device structure
1027  *
1028  * Return: '0' on success and failure value on error
1029  */
1030 static int zynqmp_dma_probe(struct platform_device *pdev)
1031 {
1032         struct zynqmp_dma_device *zdev;
1033         struct dma_device *p;
1034         int ret;
1035
1036         zdev = devm_kzalloc(&pdev->dev, sizeof(*zdev), GFP_KERNEL);
1037         if (!zdev)
1038                 return -ENOMEM;
1039
1040         zdev->dev = &pdev->dev;
1041         INIT_LIST_HEAD(&zdev->common.channels);
1042
1043         dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1044         dma_cap_set(DMA_MEMCPY, zdev->common.cap_mask);
1045
1046         p = &zdev->common;
1047         p->device_prep_dma_memcpy = zynqmp_dma_prep_memcpy;
1048         p->device_terminate_all = zynqmp_dma_device_terminate_all;
1049         p->device_issue_pending = zynqmp_dma_issue_pending;
1050         p->device_alloc_chan_resources = zynqmp_dma_alloc_chan_resources;
1051         p->device_free_chan_resources = zynqmp_dma_free_chan_resources;
1052         p->device_tx_status = dma_cookie_status;
1053         p->device_config = zynqmp_dma_device_config;
1054         p->dev = &pdev->dev;
1055
1056         zdev->clk_main = devm_clk_get(&pdev->dev, "clk_main");
1057         if (IS_ERR(zdev->clk_main)) {
1058                 dev_err(&pdev->dev, "main clock not found.\n");
1059                 return PTR_ERR(zdev->clk_main);
1060         }
1061
1062         zdev->clk_apb = devm_clk_get(&pdev->dev, "clk_apb");
1063         if (IS_ERR(zdev->clk_apb)) {
1064                 dev_err(&pdev->dev, "apb clock not found.\n");
1065                 return PTR_ERR(zdev->clk_apb);
1066         }
1067
1068         platform_set_drvdata(pdev, zdev);
1069         pm_runtime_set_autosuspend_delay(zdev->dev, ZDMA_PM_TIMEOUT);
1070         pm_runtime_use_autosuspend(zdev->dev);
1071         pm_runtime_enable(zdev->dev);
1072         pm_runtime_get_sync(zdev->dev);
1073         if (!pm_runtime_enabled(zdev->dev)) {
1074                 ret = zynqmp_dma_runtime_resume(zdev->dev);
1075                 if (ret)
1076                         return ret;
1077         }
1078
1079         ret = zynqmp_dma_chan_probe(zdev, pdev);
1080         if (ret) {
1081                 dev_err(&pdev->dev, "Probing channel failed\n");
1082                 goto err_disable_pm;
1083         }
1084
1085         p->dst_addr_widths = BIT(zdev->chan->bus_width / 8);
1086         p->src_addr_widths = BIT(zdev->chan->bus_width / 8);
1087
1088         dma_async_device_register(&zdev->common);
1089
1090         ret = of_dma_controller_register(pdev->dev.of_node,
1091                                          of_zynqmp_dma_xlate, zdev);
1092         if (ret) {
1093                 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
1094                 dma_async_device_unregister(&zdev->common);
1095                 goto free_chan_resources;
1096         }
1097
1098         pm_runtime_mark_last_busy(zdev->dev);
1099         pm_runtime_put_sync_autosuspend(zdev->dev);
1100
1101         dev_info(&pdev->dev, "ZynqMP DMA driver Probe success\n");
1102
1103         return 0;
1104
1105 free_chan_resources:
1106         zynqmp_dma_chan_remove(zdev->chan);
1107 err_disable_pm:
1108         if (!pm_runtime_enabled(zdev->dev))
1109                 zynqmp_dma_runtime_suspend(zdev->dev);
1110         pm_runtime_disable(zdev->dev);
1111         return ret;
1112 }
1113
1114 /**
1115  * zynqmp_dma_remove - Driver remove function
1116  * @pdev: Pointer to the platform_device structure
1117  *
1118  * Return: Always '0'
1119  */
1120 static int zynqmp_dma_remove(struct platform_device *pdev)
1121 {
1122         struct zynqmp_dma_device *zdev = platform_get_drvdata(pdev);
1123
1124         of_dma_controller_free(pdev->dev.of_node);
1125         dma_async_device_unregister(&zdev->common);
1126
1127         zynqmp_dma_chan_remove(zdev->chan);
1128         pm_runtime_disable(zdev->dev);
1129         if (!pm_runtime_enabled(zdev->dev))
1130                 zynqmp_dma_runtime_suspend(zdev->dev);
1131
1132         return 0;
1133 }
1134
1135 static const struct of_device_id zynqmp_dma_of_match[] = {
1136         { .compatible = "xlnx,zynqmp-dma-1.0", },
1137         {}
1138 };
1139 MODULE_DEVICE_TABLE(of, zynqmp_dma_of_match);
1140
1141 static struct platform_driver zynqmp_dma_driver = {
1142         .driver = {
1143                 .name = "xilinx-zynqmp-dma",
1144                 .of_match_table = zynqmp_dma_of_match,
1145                 .pm = &zynqmp_dma_dev_pm_ops,
1146         },
1147         .probe = zynqmp_dma_probe,
1148         .remove = zynqmp_dma_remove,
1149 };
1150
1151 module_platform_driver(zynqmp_dma_driver);
1152
1153 MODULE_LICENSE("GPL");
1154 MODULE_AUTHOR("Xilinx, Inc.");
1155 MODULE_DESCRIPTION("Xilinx ZynqMP DMA driver");