| blob | 5d43ed9b05ad1521fa8a2990a22d35cf29d7403b |
1 /*
2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
19 /* core clocks */
20 #define PLL_APLL 1
21 #define PLL_DPLL 2
22 #define PLL_CPLL 3
23 #define PLL_GPLL 4
24 #define ARMCLK 5
26 /* sclk gates (special clocks) */
27 #define SCLK_SPI0 65
28 #define SCLK_NANDC 67
29 #define SCLK_SDMMC 68
30 #define SCLK_SDIO 69
31 #define SCLK_EMMC 71
32 #define SCLK_TSADC 72
33 #define SCLK_UART0 77
34 #define SCLK_UART1 78
35 #define SCLK_UART2 79
36 #define SCLK_I2S0 80
37 #define SCLK_I2S1 81
38 #define SCLK_I2S2 82
39 #define SCLK_SPDIF 83
40 #define SCLK_TIMER0 85
41 #define SCLK_TIMER1 86
42 #define SCLK_TIMER2 87
43 #define SCLK_TIMER3 88
44 #define SCLK_TIMER4 89
45 #define SCLK_TIMER5 90
46 #define SCLK_I2S_OUT 113
47 #define SCLK_SDMMC_DRV 114
48 #define SCLK_SDIO_DRV 115
49 #define SCLK_EMMC_DRV 117
50 #define SCLK_SDMMC_SAMPLE 118
51 #define SCLK_SDIO_SAMPLE 119
52 #define SCLK_EMMC_SAMPLE 121
53 #define SCLK_VOP 122
54 #define SCLK_HDMI_HDCP 123
56 /* dclk gates */
57 #define DCLK_VOP 190
58 #define DCLK_HDMI_PHY 191
60 /* aclk gates */
61 #define ACLK_DMAC 194
62 #define ACLK_PERI 210
63 #define ACLK_VOP 211
65 /* pclk gates */
66 #define PCLK_GPIO0 320
67 #define PCLK_GPIO1 321
68 #define PCLK_GPIO2 322
69 #define PCLK_GPIO3 323
70 #define PCLK_GRF 329
71 #define PCLK_I2C0 332
72 #define PCLK_I2C1 333
73 #define PCLK_I2C2 334
74 #define PCLK_I2C3 335
75 #define PCLK_SPI0 338
76 #define PCLK_UART0 341
77 #define PCLK_UART1 342
78 #define PCLK_UART2 343
79 #define PCLK_TSADC 344
80 #define PCLK_PWM 350
81 #define PCLK_TIMER 353
82 #define PCLK_PERI 363
83 #define PCLK_HDMI_CTRL 364
84 #define PCLK_HDMI_PHY 365
86 /* hclk gates */
87 #define HCLK_VOP 452
88 #define HCLK_NANDC 453
89 #define HCLK_SDMMC 456
90 #define HCLK_SDIO 457
91 #define HCLK_EMMC 459
92 #define HCLK_PERI 478
94 #define CLK_NR_CLKS (HCLK_PERI + 1)
96 /* soft-reset indices */
97 #define SRST_CORE0_PO 0
98 #define SRST_CORE1_PO 1
99 #define SRST_CORE2_PO 2
100 #define SRST_CORE3_PO 3
101 #define SRST_CORE0 4
102 #define SRST_CORE1 5
103 #define SRST_CORE2 6
104 #define SRST_CORE3 7
105 #define SRST_CORE0_DBG 8
106 #define SRST_CORE1_DBG 9
107 #define SRST_CORE2_DBG 10
108 #define SRST_CORE3_DBG 11
109 #define SRST_TOPDBG 12
110 #define SRST_ACLK_CORE 13
111 #define SRST_NOC 14
112 #define SRST_L2C 15
114 #define SRST_CPUSYS_H 18
115 #define SRST_BUSSYS_H 19
116 #define SRST_SPDIF 20
117 #define SRST_INTMEM 21
118 #define SRST_ROM 22
119 #define SRST_OTG_ADP 23
120 #define SRST_I2S0 24
121 #define SRST_I2S1 25
122 #define SRST_I2S2 26
123 #define SRST_ACODEC_P 27
124 #define SRST_DFIMON 28
125 #define SRST_MSCH 29
126 #define SRST_EFUSE1024 30
127 #define SRST_EFUSE256 31
129 #define SRST_GPIO0 32
130 #define SRST_GPIO1 33
131 #define SRST_GPIO2 34
132 #define SRST_GPIO3 35
133 #define SRST_PERIPH_NOC_A 36
134 #define SRST_PERIPH_NOC_BUS_H 37
135 #define SRST_PERIPH_NOC_P 38
136 #define SRST_UART0 39
137 #define SRST_UART1 40
138 #define SRST_UART2 41
139 #define SRST_PHYNOC 42
140 #define SRST_I2C0 43
141 #define SRST_I2C1 44
142 #define SRST_I2C2 45
143 #define SRST_I2C3 46
145 #define SRST_PWM 48
146 #define SRST_A53_GIC 49
147 #define SRST_DAP 51
148 #define SRST_DAP_NOC 52
149 #define SRST_CRYPTO 53
150 #define SRST_SGRF 54
151 #define SRST_GRF 55
152 #define SRST_GMAC 56
153 #define SRST_PERIPH_NOC_H 58
154 #define SRST_MACPHY 63
156 #define SRST_DMA 64
157 #define SRST_NANDC 68
158 #define SRST_USBOTG 69
159 #define SRST_OTGC 70
160 #define SRST_USBHOST0 71
161 #define SRST_HOST_CTRL0 72
162 #define SRST_USBHOST1 73
163 #define SRST_HOST_CTRL1 74
164 #define SRST_USBHOST2 75
165 #define SRST_HOST_CTRL2 76
166 #define SRST_USBPOR0 77
167 #define SRST_USBPOR1 78
168 #define SRST_DDRMSCH 79
170 #define SRST_SMART_CARD 80
171 #define SRST_SDMMC 81
172 #define SRST_SDIO 82
173 #define SRST_EMMC 83
174 #define SRST_SPI 84
175 #define SRST_TSP_H 85
176 #define SRST_TSP 86
177 #define SRST_TSADC 87
178 #define SRST_DDRPHY 88
179 #define SRST_DDRPHY_P 89
180 #define SRST_DDRCTRL 90
181 #define SRST_DDRCTRL_P 91
182 #define SRST_HOST0_ECHI 92
183 #define SRST_HOST1_ECHI 93
184 #define SRST_HOST2_ECHI 94
185 #define SRST_VOP_NOC_A 95
187 #define SRST_HDMI_P 96
188 #define SRST_VIO_ARBI_H 97
189 #define SRST_IEP_NOC_A 98
190 #define SRST_VIO_NOC_H 99
191 #define SRST_VOP_A 100
192 #define SRST_VOP_H 101
193 #define SRST_VOP_D 102
194 #define SRST_UTMI0 103
195 #define SRST_UTMI1 104
196 #define SRST_UTMI2 105
197 #define SRST_UTMI3 106
198 #define SRST_RGA 107
199 #define SRST_RGA_NOC_A 108
200 #define SRST_RGA_A 109
201 #define SRST_RGA_H 110
202 #define SRST_HDCP_A 111
204 #define SRST_VPU_A 112
205 #define SRST_VPU_H 113
206 #define SRST_VPU_NOC_A 116
207 #define SRST_VPU_NOC_H 117
208 #define SRST_RKVDEC_A 118
209 #define SRST_RKVDEC_NOC_A 119
210 #define SRST_RKVDEC_H 120
211 #define SRST_RKVDEC_NOC_H 121
212 #define SRST_RKVDEC_CORE 122
213 #define SRST_RKVDEC_CABAC 123
214 #define SRST_IEP_A 124
215 #define SRST_IEP_H 125
216 #define SRST_GPU_A 126
217 #define SRST_GPU_NOC_A 127
219 #define SRST_CORE_DBG 128
220 #define SRST_DBG_P 129
221 #define SRST_TIMER0 130
222 #define SRST_TIMER1 131
223 #define SRST_TIMER2 132
224 #define SRST_TIMER3 133
225 #define SRST_TIMER4 134
226 #define SRST_TIMER5 135
227 #define SRST_VIO_H2P 136
228 #define SRST_HDMIPHY 139
229 #define SRST_VDAC 140
230 #define SRST_TIMER_6CH_P 141
232 #endif