drivers/usb/host/fotg210.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __LINUX_FOTG210_H
   3 #define __LINUX_FOTG210_H
   4
   5 #include <linux/usb/ehci-dbgp.h>
   6
   7 /* definitions used for the EHCI driver */
   8
   9 /*
  10  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  11  * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
  12  * the host controller implementation.
  13  *
  14  * To facilitate the strongest possible byte-order checking from "sparse"
  15  * and so on, we use __leXX unless that's not practical.
  16  */
  17 #define __hc32  __le32
  18 #define __hc16  __le16
  19
  20 /* statistics can be kept for tuning/monitoring */
  21 struct fotg210_stats {
  22         /* irq usage */
  23         unsigned long           normal;
  24         unsigned long           error;
  25         unsigned long           iaa;
  26         unsigned long           lost_iaa;
  27
  28         /* termination of urbs from core */
  29         unsigned long           complete;
  30         unsigned long           unlink;
  31 };
  32
  33 /* fotg210_hcd->lock guards shared data against other CPUs:
  34  *   fotg210_hcd:       async, unlink, periodic (and shadow), ...
  35  *   usb_host_endpoint: hcpriv
  36  *   fotg210_qh:        qh_next, qtd_list
  37  *   fotg210_qtd:       qtd_list
  38  *
  39  * Also, hold this lock when talking to HC registers or
  40  * when updating hw_* fields in shared qh/qtd/... structures.
  41  */
  42
  43 #define FOTG210_MAX_ROOT_PORTS  1               /* see HCS_N_PORTS */
  44
  45 /*
  46  * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
  47  * controller may be doing DMA.  Lower values mean there's no DMA.
  48  */
  49 enum fotg210_rh_state {
  50         FOTG210_RH_HALTED,
  51         FOTG210_RH_SUSPENDED,
  52         FOTG210_RH_RUNNING,
  53         FOTG210_RH_STOPPING
  54 };
  55
  56 /*
  57  * Timer events, ordered by increasing delay length.
  58  * Always update event_delays_ns[] and event_handlers[] (defined in
  59  * ehci-timer.c) in parallel with this list.
  60  */
  61 enum fotg210_hrtimer_event {
  62         FOTG210_HRTIMER_POLL_ASS,       /* Poll for async schedule off */
  63         FOTG210_HRTIMER_POLL_PSS,       /* Poll for periodic schedule off */
  64         FOTG210_HRTIMER_POLL_DEAD,      /* Wait for dead controller to stop */
  65         FOTG210_HRTIMER_UNLINK_INTR,    /* Wait for interrupt QH unlink */
  66         FOTG210_HRTIMER_FREE_ITDS,      /* Wait for unused iTDs and siTDs */
  67         FOTG210_HRTIMER_ASYNC_UNLINKS,  /* Unlink empty async QHs */
  68         FOTG210_HRTIMER_IAA_WATCHDOG,   /* Handle lost IAA interrupts */
  69         FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
  70         FOTG210_HRTIMER_DISABLE_ASYNC,  /* Wait to disable async sched */
  71         FOTG210_HRTIMER_IO_WATCHDOG,    /* Check for missing IRQs */
  72         FOTG210_HRTIMER_NUM_EVENTS      /* Must come last */
  73 };
  74 #define FOTG210_HRTIMER_NO_EVENT        99
  75
  76 struct fotg210_hcd {                    /* one per controller */
  77         /* timing support */
  78         enum fotg210_hrtimer_event      next_hrtimer_event;
  79         unsigned                enabled_hrtimer_events;
  80         ktime_t                 hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
  81         struct hrtimer          hrtimer;
  82
  83         int                     PSS_poll_count;
  84         int                     ASS_poll_count;
  85         int                     died_poll_count;
  86
  87         /* glue to PCI and HCD framework */
  88         struct fotg210_caps __iomem *caps;
  89         struct fotg210_regs __iomem *regs;
  90         struct ehci_dbg_port __iomem *debug;
  91
  92         __u32                   hcs_params;     /* cached register copy */
  93         spinlock_t              lock;
  94         enum fotg210_rh_state   rh_state;
  95
  96         /* general schedule support */
  97         bool                    scanning:1;
  98         bool                    need_rescan:1;
  99         bool                    intr_unlinking:1;
 100         bool                    async_unlinking:1;
 101         bool                    shutdown:1;
 102         struct fotg210_qh               *qh_scan_next;
 103
 104         /* async schedule support */
 105         struct fotg210_qh               *async;
 106         struct fotg210_qh               *dummy;         /* For AMD quirk use */
 107         struct fotg210_qh               *async_unlink;
 108         struct fotg210_qh               *async_unlink_last;
 109         struct fotg210_qh               *async_iaa;
 110         unsigned                async_unlink_cycle;
 111         unsigned                async_count;    /* async activity count */
 112
 113         /* periodic schedule support */
 114 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 115         unsigned                periodic_size;
 116         __hc32                  *periodic;      /* hw periodic table */
 117         dma_addr_t              periodic_dma;
 118         struct list_head        intr_qh_list;
 119         unsigned                i_thresh;       /* uframes HC might cache */
 120
 121         union fotg210_shadow    *pshadow;       /* mirror hw periodic table */
 122         struct fotg210_qh               *intr_unlink;
 123         struct fotg210_qh               *intr_unlink_last;
 124         unsigned                intr_unlink_cycle;
 125         unsigned                now_frame;      /* frame from HC hardware */
 126         unsigned                next_frame;     /* scan periodic, start here */
 127         unsigned                intr_count;     /* intr activity count */
 128         unsigned                isoc_count;     /* isoc activity count */
 129         unsigned                periodic_count; /* periodic activity count */
 130         /* max periodic time per uframe */
 131         unsigned                uframe_periodic_max;
 132
 133
 134         /* list of itds completed while now_frame was still active */
 135         struct list_head        cached_itd_list;
 136         struct fotg210_itd      *last_itd_to_free;
 137
 138         /* per root hub port */
 139         unsigned long           reset_done[FOTG210_MAX_ROOT_PORTS];
 140
 141         /* bit vectors (one bit per port)
 142          * which ports were already suspended at the start of a bus suspend
 143          */
 144         unsigned long           bus_suspended;
 145
 146         /* which ports are edicated to the companion controller */
 147         unsigned long           companion_ports;
 148
 149         /* which ports are owned by the companion during a bus suspend */
 150         unsigned long           owned_ports;
 151
 152         /* which ports have the change-suspend feature turned on */
 153         unsigned long           port_c_suspend;
 154
 155         /* which ports are suspended */
 156         unsigned long           suspended_ports;
 157
 158         /* which ports have started to resume */
 159         unsigned long           resuming_ports;
 160
 161         /* per-HC memory pools (could be per-bus, but ...) */
 162         struct dma_pool         *qh_pool;       /* qh per active urb */
 163         struct dma_pool         *qtd_pool;      /* one or more per qh */
 164         struct dma_pool         *itd_pool;      /* itd per iso urb */
 165
 166         unsigned                random_frame;
 167         unsigned long           next_statechange;
 168         ktime_t                 last_periodic_enable;
 169         u32                     command;
 170
 171         /* SILICON QUIRKS */
 172         unsigned                need_io_watchdog:1;
 173         unsigned                fs_i_thresh:1;  /* Intel iso scheduling */
 174
 175         u8                      sbrn;           /* packed release number */
 176
 177         /* irq statistics */
 178 #ifdef FOTG210_STATS
 179         struct fotg210_stats    stats;
 180 #       define COUNT(x) ((x)++)
 181 #else
 182 #       define COUNT(x)
 183 #endif
 184
 185         /* debug files */
 186         struct dentry           *debug_dir;
 187 };
 188
 189 /* convert between an HCD pointer and the corresponding FOTG210_HCD */
 190 static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
 191 {
 192         return (struct fotg210_hcd *)(hcd->hcd_priv);
 193 }
 194 static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
 195 {
 196         return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
 197 }
 198
 199 /*-------------------------------------------------------------------------*/
 200
 201 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 202
 203 /* Section 2.2 Host Controller Capability Registers */
 204 struct fotg210_caps {
 205         /* these fields are specified as 8 and 16 bit registers,
 206          * but some hosts can't perform 8 or 16 bit PCI accesses.
 207          * some hosts treat caplength and hciversion as parts of a 32-bit
 208          * register, others treat them as two separate registers, this
 209          * affects the memory map for big endian controllers.
 210          */
 211         u32             hc_capbase;
 212 #define HC_LENGTH(fotg210, p)   (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
 213                                 (fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
 214 #define HC_VERSION(fotg210, p)  (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
 215                                 (fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
 216         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 217 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 218
 219         u32             hcc_params;     /* HCCPARAMS - offset 0x8 */
 220 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 221 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 222         u8              portroute[8];    /* nibbles for routing - offset 0xC */
 223 };
 224
 225
 226 /* Section 2.3 Host Controller Operational Registers */
 227 struct fotg210_regs {
 228
 229         /* USBCMD: offset 0x00 */
 230         u32             command;
 231
 232 /* EHCI 1.1 addendum */
 233 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 234 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 235 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 236 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 237 #define CMD_ASE         (1<<5)          /* async schedule enable */
 238 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 239 /* 3:2 is periodic frame list size */
 240 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 241 #define CMD_RUN         (1<<0)          /* start/stop HC */
 242
 243         /* USBSTS: offset 0x04 */
 244         u32             status;
 245 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 246 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 247 #define STS_RECL        (1<<13)         /* Reclamation */
 248 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 249 /* some bits reserved */
 250         /* these STS_* flags are also intr_enable bits (USBINTR) */
 251 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 252 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 253 #define STS_FLR         (1<<3)          /* frame list rolled over */
 254 #define STS_PCD         (1<<2)          /* port change detect */
 255 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 256 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 257
 258         /* USBINTR: offset 0x08 */
 259         u32             intr_enable;
 260
 261         /* FRINDEX: offset 0x0C */
 262         u32             frame_index;    /* current microframe number */
 263         /* CTRLDSSEGMENT: offset 0x10 */
 264         u32             segment;        /* address bits 63:32 if needed */
 265         /* PERIODICLISTBASE: offset 0x14 */
 266         u32             frame_list;     /* points to periodic list */
 267         /* ASYNCLISTADDR: offset 0x18 */
 268         u32             async_next;     /* address of next async queue head */
 269
 270         u32     reserved1;
 271         /* PORTSC: offset 0x20 */
 272         u32     port_status;
 273 /* 31:23 reserved */
 274 #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))        /* USB 1.1 device */
 275 #define PORT_RESET      (1<<8)          /* reset port */
 276 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 277 #define PORT_RESUME     (1<<6)          /* resume it */
 278 #define PORT_PEC        (1<<3)          /* port enable change */
 279 #define PORT_PE         (1<<2)          /* port enable */
 280 #define PORT_CSC        (1<<1)          /* connect status change */
 281 #define PORT_CONNECT    (1<<0)          /* device connected */
 282 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC)
 283         u32     reserved2[19];
 284
 285         /* OTGCSR: offet 0x70 */
 286         u32     otgcsr;
 287 #define OTGCSR_HOST_SPD_TYP     (3 << 22)
 288 #define OTGCSR_A_BUS_DROP       (1 << 5)
 289 #define OTGCSR_A_BUS_REQ        (1 << 4)
 290
 291         /* OTGISR: offset 0x74 */
 292         u32     otgisr;
 293 #define OTGISR_OVC      (1 << 10)
 294
 295         u32     reserved3[15];
 296
 297         /* GMIR: offset 0xB4 */
 298         u32     gmir;
 299 #define GMIR_INT_POLARITY       (1 << 3) /*Active High*/
 300 #define GMIR_MHC_INT            (1 << 2)
 301 #define GMIR_MOTG_INT           (1 << 1)
 302 #define GMIR_MDEV_INT   (1 << 0)
 303 };
 304
 305 /*-------------------------------------------------------------------------*/
 306
 307 #define QTD_NEXT(fotg210, dma)  cpu_to_hc32(fotg210, (u32)dma)
 308
 309 /*
 310  * EHCI Specification 0.95 Section 3.5
 311  * QTD: describe data transfer components (buffer, direction, ...)
 312  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 313  *
 314  * These are associated only with "QH" (Queue Head) structures,
 315  * used with control, bulk, and interrupt transfers.
 316  */
 317 struct fotg210_qtd {
 318         /* first part defined by EHCI spec */
 319         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 320         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 321         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 322 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 323 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 324 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 325 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 326 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 327 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 328 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 329 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 330 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 331 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 332 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 333 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 334 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 335
 336 #define ACTIVE_BIT(fotg210)     cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
 337 #define HALT_BIT(fotg210)               cpu_to_hc32(fotg210, QTD_STS_HALT)
 338 #define STATUS_BIT(fotg210)     cpu_to_hc32(fotg210, QTD_STS_STS)
 339
 340         __hc32                  hw_buf[5];      /* see EHCI 3.5.4 */
 341         __hc32                  hw_buf_hi[5];   /* Appendix B */
 342
 343         /* the rest is HCD-private */
 344         dma_addr_t              qtd_dma;                /* qtd address */
 345         struct list_head        qtd_list;               /* sw qtd list */
 346         struct urb              *urb;                   /* qtd's urb */
 347         size_t                  length;                 /* length of buffer */
 348 } __aligned(32);
 349
 350 /* mask NakCnt+T in qh->hw_alt_next */
 351 #define QTD_MASK(fotg210)       cpu_to_hc32(fotg210, ~0x1f)
 352
 353 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
 354
 355 /*-------------------------------------------------------------------------*/
 356
 357 /* type tag from {qh,itd,fstn}->hw_next */
 358 #define Q_NEXT_TYPE(fotg210, dma)       ((dma) & cpu_to_hc32(fotg210, 3 << 1))
 359
 360 /*
 361  * Now the following defines are not converted using the
 362  * cpu_to_le32() macro anymore, since we have to support
 363  * "dynamic" switching between be and le support, so that the driver
 364  * can be used on one system with SoC EHCI controller using big-endian
 365  * descriptors as well as a normal little-endian PCI EHCI controller.
 366  */
 367 /* values for that type tag */
 368 #define Q_TYPE_ITD      (0 << 1)
 369 #define Q_TYPE_QH       (1 << 1)
 370 #define Q_TYPE_SITD     (2 << 1)
 371 #define Q_TYPE_FSTN     (3 << 1)
 372
 373 /* next async queue entry, or pointer to interrupt/periodic QH */
 374 #define QH_NEXT(fotg210, dma) \
 375         (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 376
 377 /* for periodic/async schedules and qtd lists, mark end of list */
 378 #define FOTG210_LIST_END(fotg210) \
 379         cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
 380
 381 /*
 382  * Entries in periodic shadow table are pointers to one of four kinds
 383  * of data structure.  That's dictated by the hardware; a type tag is
 384  * encoded in the low bits of the hardware's periodic schedule.  Use
 385  * Q_NEXT_TYPE to get the tag.
 386  *
 387  * For entries in the async schedule, the type tag always says "qh".
 388  */
 389 union fotg210_shadow {
 390         struct fotg210_qh       *qh;            /* Q_TYPE_QH */
 391         struct fotg210_itd      *itd;           /* Q_TYPE_ITD */
 392         struct fotg210_fstn     *fstn;          /* Q_TYPE_FSTN */
 393         __hc32                  *hw_next;       /* (all types) */
 394         void                    *ptr;
 395 };
 396
 397 /*-------------------------------------------------------------------------*/
 398
 399 /*
 400  * EHCI Specification 0.95 Section 3.6
 401  * QH: describes control/bulk/interrupt endpoints
 402  * See Fig 3-7 "Queue Head Structure Layout".
 403  *
 404  * These appear in both the async and (for interrupt) periodic schedules.
 405  */
 406
 407 /* first part defined by EHCI spec */
 408 struct fotg210_qh_hw {
 409         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 410         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 411 #define QH_CONTROL_EP   (1 << 27)       /* FS/LS control endpoint */
 412 #define QH_HEAD         (1 << 15)       /* Head of async reclamation list */
 413 #define QH_TOGGLE_CTL   (1 << 14)       /* Data toggle control */
 414 #define QH_HIGH_SPEED   (2 << 12)       /* Endpoint speed */
 415 #define QH_LOW_SPEED    (1 << 12)
 416 #define QH_FULL_SPEED   (0 << 12)
 417 #define QH_INACTIVATE   (1 << 7)        /* Inactivate on next transaction */
 418         __hc32                  hw_info2;       /* see EHCI 3.6.2 */
 419 #define QH_SMASK        0x000000ff
 420 #define QH_CMASK        0x0000ff00
 421 #define QH_HUBADDR      0x007f0000
 422 #define QH_HUBPORT      0x3f800000
 423 #define QH_MULT         0xc0000000
 424         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 425
 426         /* qtd overlay (hardware parts of a struct fotg210_qtd) */
 427         __hc32                  hw_qtd_next;
 428         __hc32                  hw_alt_next;
 429         __hc32                  hw_token;
 430         __hc32                  hw_buf[5];
 431         __hc32                  hw_buf_hi[5];
 432 } __aligned(32);
 433
 434 struct fotg210_qh {
 435         struct fotg210_qh_hw    *hw;            /* Must come first */
 436         /* the rest is HCD-private */
 437         dma_addr_t              qh_dma;         /* address of qh */
 438         union fotg210_shadow    qh_next;        /* ptr to qh; or periodic */
 439         struct list_head        qtd_list;       /* sw qtd list */
 440         struct list_head        intr_node;      /* list of intr QHs */
 441         struct fotg210_qtd      *dummy;
 442         struct fotg210_qh       *unlink_next;   /* next on unlink list */
 443
 444         unsigned                unlink_cycle;
 445
 446         u8                      needs_rescan;   /* Dequeue during giveback */
 447         u8                      qh_state;
 448 #define QH_STATE_LINKED         1               /* HC sees this */
 449 #define QH_STATE_UNLINK         2               /* HC may still see this */
 450 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 451 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on unlink q */
 452 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 453
 454         u8                      xacterrs;       /* XactErr retry counter */
 455 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 456
 457         /* periodic schedule info */
 458         u8                      usecs;          /* intr bandwidth */
 459         u8                      gap_uf;         /* uframes split/csplit gap */
 460         u8                      c_usecs;        /* ... split completion bw */
 461         u16                     tt_usecs;       /* tt downstream bandwidth */
 462         unsigned short          period;         /* polling interval */
 463         unsigned short          start;          /* where polling starts */
 464 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 465
 466         struct usb_device       *dev;           /* access to TT */
 467         unsigned                is_out:1;       /* bulk or intr OUT */
 468         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 469 };
 470
 471 /*-------------------------------------------------------------------------*/
 472
 473 /* description of one iso transaction (up to 3 KB data if highspeed) */
 474 struct fotg210_iso_packet {
 475         /* These will be copied to iTD when scheduling */
 476         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 477         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 478         u8                      cross;          /* buf crosses pages */
 479         /* for full speed OUT splits */
 480         u32                     buf1;
 481 };
 482
 483 /* temporary schedule data for packets from iso urbs (both speeds)
 484  * each packet is one logical usb transaction to the device (not TT),
 485  * beginning at stream->next_uframe
 486  */
 487 struct fotg210_iso_sched {
 488         struct list_head        td_list;
 489         unsigned                span;
 490         struct fotg210_iso_packet       packet[0];
 491 };
 492
 493 /*
 494  * fotg210_iso_stream - groups all (s)itds for this endpoint.
 495  * acts like a qh would, if EHCI had them for ISO.
 496  */
 497 struct fotg210_iso_stream {
 498         /* first field matches fotg210_hq, but is NULL */
 499         struct fotg210_qh_hw    *hw;
 500
 501         u8                      bEndpointAddress;
 502         u8                      highspeed;
 503         struct list_head        td_list;        /* queued itds */
 504         struct list_head        free_list;      /* list of unused itds */
 505         struct usb_device       *udev;
 506         struct usb_host_endpoint *ep;
 507
 508         /* output of (re)scheduling */
 509         int                     next_uframe;
 510         __hc32                  splits;
 511
 512         /* the rest is derived from the endpoint descriptor,
 513          * trusting urb->interval == f(epdesc->bInterval) and
 514          * including the extra info for hw_bufp[0..2]
 515          */
 516         u8                      usecs, c_usecs;
 517         u16                     interval;
 518         u16                     tt_usecs;
 519         u16                     maxp;
 520         u16                     raw_mask;
 521         unsigned                bandwidth;
 522
 523         /* This is used to initialize iTD's hw_bufp fields */
 524         __hc32                  buf0;
 525         __hc32                  buf1;
 526         __hc32                  buf2;
 527
 528         /* this is used to initialize sITD's tt info */
 529         __hc32                  address;
 530 };
 531
 532 /*-------------------------------------------------------------------------*/
 533
 534 /*
 535  * EHCI Specification 0.95 Section 3.3
 536  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 537  *
 538  * Schedule records for high speed iso xfers
 539  */
 540 struct fotg210_itd {
 541         /* first part defined by EHCI spec */
 542         __hc32                  hw_next;        /* see EHCI 3.3.1 */
 543         __hc32                  hw_transaction[8]; /* see EHCI 3.3.2 */
 544 #define FOTG210_ISOC_ACTIVE     (1<<31) /* activate transfer this slot */
 545 #define FOTG210_ISOC_BUF_ERR    (1<<30) /* Data buffer error */
 546 #define FOTG210_ISOC_BABBLE     (1<<29) /* babble detected */
 547 #define FOTG210_ISOC_XACTERR    (1<<28) /* XactErr - transaction error */
 548 #define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
 549 #define FOTG210_ITD_IOC         (1 << 15)       /* interrupt on complete */
 550
 551 #define ITD_ACTIVE(fotg210)     cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
 552
 553         __hc32                  hw_bufp[7];     /* see EHCI 3.3.3 */
 554         __hc32                  hw_bufp_hi[7];  /* Appendix B */
 555
 556         /* the rest is HCD-private */
 557         dma_addr_t              itd_dma;        /* for this itd */
 558         union fotg210_shadow    itd_next;       /* ptr to periodic q entry */
 559
 560         struct urb              *urb;
 561         struct fotg210_iso_stream       *stream;        /* endpoint's queue */
 562         struct list_head        itd_list;       /* list of stream's itds */
 563
 564         /* any/all hw_transactions here may be used by that urb */
 565         unsigned                frame;          /* where scheduled */
 566         unsigned                pg;
 567         unsigned                index[8];       /* in urb->iso_frame_desc */
 568 } __aligned(32);
 569
 570 /*-------------------------------------------------------------------------*/
 571
 572 /*
 573  * EHCI Specification 0.96 Section 3.7
 574  * Periodic Frame Span Traversal Node (FSTN)
 575  *
 576  * Manages split interrupt transactions (using TT) that span frame boundaries
 577  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 578  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 579  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 580  */
 581 struct fotg210_fstn {
 582         __hc32                  hw_next;        /* any periodic q entry */
 583         __hc32                  hw_prev;        /* qh or FOTG210_LIST_END */
 584
 585         /* the rest is HCD-private */
 586         dma_addr_t              fstn_dma;
 587         union fotg210_shadow    fstn_next;      /* ptr to periodic q entry */
 588 } __aligned(32);
 589
 590 /*-------------------------------------------------------------------------*/
 591
 592 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 593
 594 #define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
 595                 fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup)
 596
 597 #define fotg210_prepare_ports_for_controller_resume(fotg210)            \
 598                 fotg210_adjust_port_wakeup_flags(fotg210, false, false)
 599
 600 /*-------------------------------------------------------------------------*/
 601
 602 /*
 603  * Some EHCI controllers have a Transaction Translator built into the
 604  * root hub. This is a non-standard feature.  Each controller will need
 605  * to add code to the following inline functions, and call them as
 606  * needed (mostly in root hub code).
 607  */
 608
 609 static inline unsigned int
 610 fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
 611 {
 612         return (readl(&fotg210->regs->otgcsr)
 613                 & OTGCSR_HOST_SPD_TYP) >> 22;
 614 }
 615
 616 /* Returns the speed of a device attached to a port on the root hub. */
 617 static inline unsigned int
 618 fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
 619 {
 620         switch (fotg210_get_speed(fotg210, portsc)) {
 621         case 0:
 622                 return 0;
 623         case 1:
 624                 return USB_PORT_STAT_LOW_SPEED;
 625         case 2:
 626         default:
 627                 return USB_PORT_STAT_HIGH_SPEED;
 628         }
 629 }
 630
 631 /*-------------------------------------------------------------------------*/
 632
 633 #define fotg210_has_fsl_portno_bug(e)           (0)
 634
 635 /*
 636  * While most USB host controllers implement their registers in
 637  * little-endian format, a minority (celleb companion chip) implement
 638  * them in big endian format.
 639  *
 640  * This attempts to support either format at compile time without a
 641  * runtime penalty, or both formats with the additional overhead
 642  * of checking a flag bit.
 643  *
 644  */
 645
 646 #define fotg210_big_endian_mmio(e)      0
 647 #define fotg210_big_endian_capbase(e)   0
 648
 649 static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
 650                 __u32 __iomem *regs)
 651 {
 652         return readl(regs);
 653 }
 654
 655 static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
 656                 const unsigned int val, __u32 __iomem *regs)
 657 {
 658         writel(val, regs);
 659 }
 660
 661 /* cpu to fotg210 */
 662 static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
 663 {
 664         return cpu_to_le32(x);
 665 }
 666
 667 /* fotg210 to cpu */
 668 static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
 669 {
 670         return le32_to_cpu(x);
 671 }
 672
 673 static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
 674                                const __hc32 *x)
 675 {
 676         return le32_to_cpup(x);
 677 }
 678
 679 /*-------------------------------------------------------------------------*/
 680
 681 static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
 682 {
 683         return fotg210_readl(fotg210, &fotg210->regs->frame_index);
 684 }
 685
 686 #define fotg210_itdlen(urb, desc, t) ({                 \
 687         usb_pipein((urb)->pipe) ?                               \
 688         (desc)->length - FOTG210_ITD_LENGTH(t) :                        \
 689         FOTG210_ITD_LENGTH(t);                                  \
 690 })
 691 /*-------------------------------------------------------------------------*/
 692
 693 #endif /* __LINUX_FOTG210_H */