drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18
  19 #define SSIC_PORT_NUM           2
  20 #define SSIC_PORT_CFG2          0x880c
  21 #define SSIC_PORT_CFG2_OFFSET   0x30
  22 #define PROG_DONE               (1 << 30)
  23 #define SSIC_PORT_UNUSED        (1 << 31)
  24
  25 /* Device for a quirk */
  26 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  30
  31 #define PCI_VENDOR_ID_ETRON             0x1b6f
  32 #define PCI_DEVICE_ID_EJ168             0x7023
  33
  34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  42 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  44 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  45
  46 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  47 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  48 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  49 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  50 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  51
  52 static const char hcd_name[] = "xhci_hcd";
  53
  54 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  55
  56 static int xhci_pci_setup(struct usb_hcd *hcd);
  57
  58 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  59         .reset = xhci_pci_setup,
  60 };
  61
  62 /* called after powerup, by probe or system-pm "wakeup" */
  63 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  64 {
  65         /*
  66          * TODO: Implement finding debug ports later.
  67          * TODO: see if there are any quirks that need to be added to handle
  68          * new extended capabilities.
  69          */
  70
  71         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  72         if (!pci_set_mwi(pdev))
  73                 xhci_dbg(xhci, "MWI active\n");
  74
  75         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  76         return 0;
  77 }
  78
  79 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  80 {
  81         struct pci_dev          *pdev = to_pci_dev(dev);
  82
  83         /* Look for vendor-specific quirks */
  84         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  85                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  86                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  87                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  88                                 pdev->revision == 0x0) {
  89                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  90                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  91                                 "QUIRK: Fresco Logic xHC needs configure"
  92                                 " endpoint cmd after reset endpoint");
  93                 }
  94                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  95                                 pdev->revision == 0x4) {
  96                         xhci->quirks |= XHCI_SLOW_SUSPEND;
  97                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  98                                 "QUIRK: Fresco Logic xHC revision %u"
  99                                 "must be suspended extra slowly",
 100                                 pdev->revision);
 101                 }
 102                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 103                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 104                 /* Fresco Logic confirms: all revisions of this chip do not
 105                  * support MSI, even though some of them claim to in their PCI
 106                  * capabilities.
 107                  */
 108                 xhci->quirks |= XHCI_BROKEN_MSI;
 109                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 110                                 "QUIRK: Fresco Logic revision %u "
 111                                 "has broken MSI implementation",
 112                                 pdev->revision);
 113                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 114         }
 115
 116         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 117                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 118                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 119
 120         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 121                 xhci->quirks |= XHCI_NEC_HOST;
 122
 123         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 124                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 125
 126         /* AMD PLL quirk */
 127         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 128                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 129
 130         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 131                 (pdev->device == 0x145c ||
 132                  pdev->device == 0x15e0 ||
 133                  pdev->device == 0x15e1 ||
 134                  pdev->device == 0x43bb))
 135                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 136
 137         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 138             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 139                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 140
 141         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 142                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 143
 144         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 145                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 146                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 147                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 148                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 149                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 150
 151         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 152                 xhci->quirks |= XHCI_LPM_SUPPORT;
 153                 xhci->quirks |= XHCI_INTEL_HOST;
 154                 xhci->quirks |= XHCI_AVOID_BEI;
 155         }
 156         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 157                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 158                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 159                 xhci->limit_active_eps = 64;
 160                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 161                 /*
 162                  * PPT desktop boards DH77EB and DH77DF will power back on after
 163                  * a few seconds of being shutdown.  The fix for this is to
 164                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 165                  * DMI information to find those particular boards (since each
 166                  * vendor will change the board name), so we have to key off all
 167                  * PPT chipsets.
 168                  */
 169                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 170         }
 171         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 172                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 173                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 174                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 175                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 176         }
 177         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 178                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 179                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 180                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 181                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 182                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 183                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 184                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 185                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 186                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 187         }
 188         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 189             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 190                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 191         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 192             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 193              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 194              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 195                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 196         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 197             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 198              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 199              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 200              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 201              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 202                 xhci->quirks |= XHCI_MISSING_CAS;
 203
 204         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 205                         pdev->device == PCI_DEVICE_ID_EJ168) {
 206                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 207                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 208                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 209         }
 210         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 211             pdev->device == 0x0014) {
 212                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 213                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 214         }
 215         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 216             pdev->device == 0x0015) {
 217                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 218                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 219         }
 220         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 221                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 222
 223         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 224         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 225                         pdev->device == 0x3432)
 226                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 227
 228         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 229                         pdev->device == 0x1042)
 230                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 231         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 232                         pdev->device == 0x1142)
 233                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 234
 235         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 236                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 237                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 238
 239         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 240                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 241
 242         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 243              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 244              pdev->device == 0x9026)
 245                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 246
 247         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 248                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 249                                 "QUIRK: Resetting on resume");
 250 }
 251
 252 #ifdef CONFIG_ACPI
 253 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 254 {
 255         static const guid_t intel_dsm_guid =
 256                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 257                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 258         union acpi_object *obj;
 259
 260         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 261                                 NULL);
 262         ACPI_FREE(obj);
 263 }
 264 #else
 265 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 266 #endif /* CONFIG_ACPI */
 267
 268 /* called during probe() after chip reset completes */
 269 static int xhci_pci_setup(struct usb_hcd *hcd)
 270 {
 271         struct xhci_hcd         *xhci;
 272         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 273         int                     retval;
 274
 275         xhci = hcd_to_xhci(hcd);
 276         if (!xhci->sbrn)
 277                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 278
 279         /* imod_interval is the interrupt moderation value in nanoseconds. */
 280         xhci->imod_interval = 40000;
 281
 282         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 283         if (retval)
 284                 return retval;
 285
 286         if (!usb_hcd_is_primary_hcd(hcd))
 287                 return 0;
 288
 289         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 290                 xhci_pme_acpi_rtd3_enable(pdev);
 291
 292         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 293
 294         /* Find any debug ports */
 295         return xhci_pci_reinit(xhci, pdev);
 296 }
 297
 298 /*
 299  * We need to register our own PCI probe function (instead of the USB core's
 300  * function) in order to create a second roothub under xHCI.
 301  */
 302 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 303 {
 304         int retval;
 305         struct xhci_hcd *xhci;
 306         struct hc_driver *driver;
 307         struct usb_hcd *hcd;
 308
 309         driver = (struct hc_driver *)id->driver_data;
 310
 311         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 312         pm_runtime_get_noresume(&dev->dev);
 313
 314         /* Register the USB 2.0 roothub.
 315          * FIXME: USB core must know to register the USB 2.0 roothub first.
 316          * This is sort of silly, because we could just set the HCD driver flags
 317          * to say USB 2.0, but I'm not sure what the implications would be in
 318          * the other parts of the HCD code.
 319          */
 320         retval = usb_hcd_pci_probe(dev, id);
 321
 322         if (retval)
 323                 goto put_runtime_pm;
 324
 325         /* USB 2.0 roothub is stored in the PCI device now. */
 326         hcd = dev_get_drvdata(&dev->dev);
 327         xhci = hcd_to_xhci(hcd);
 328         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 329                                 pci_name(dev), hcd);
 330         if (!xhci->shared_hcd) {
 331                 retval = -ENOMEM;
 332                 goto dealloc_usb2_hcd;
 333         }
 334
 335         retval = xhci_ext_cap_init(xhci);
 336         if (retval)
 337                 goto put_usb3_hcd;
 338
 339         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 340                         IRQF_SHARED);
 341         if (retval)
 342                 goto put_usb3_hcd;
 343         /* Roothub already marked as USB 3.0 speed */
 344
 345         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 346                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 347                 xhci->shared_hcd->can_do_streams = 1;
 348
 349         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 350         pm_runtime_put_noidle(&dev->dev);
 351
 352         return 0;
 353
 354 put_usb3_hcd:
 355         usb_put_hcd(xhci->shared_hcd);
 356 dealloc_usb2_hcd:
 357         usb_hcd_pci_remove(dev);
 358 put_runtime_pm:
 359         pm_runtime_put_noidle(&dev->dev);
 360         return retval;
 361 }
 362
 363 static void xhci_pci_remove(struct pci_dev *dev)
 364 {
 365         struct xhci_hcd *xhci;
 366
 367         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 368         xhci->xhc_state |= XHCI_STATE_REMOVING;
 369         if (xhci->shared_hcd) {
 370                 usb_remove_hcd(xhci->shared_hcd);
 371                 usb_put_hcd(xhci->shared_hcd);
 372                 xhci->shared_hcd = NULL;
 373         }
 374
 375         /* Workaround for spurious wakeups at shutdown with HSW */
 376         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 377                 pci_set_power_state(dev, PCI_D3hot);
 378
 379         usb_hcd_pci_remove(dev);
 380 }
 381
 382 #ifdef CONFIG_PM
 383 /*
 384  * In some Intel xHCI controllers, in order to get D3 working,
 385  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 386  * SSIC PORT need to be marked as "unused" before putting xHCI
 387  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 388  * Without this change, xHCI might not enter D3 state.
 389  */
 390 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 391 {
 392         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 393         u32 val;
 394         void __iomem *reg;
 395         int i;
 396
 397         for (i = 0; i < SSIC_PORT_NUM; i++) {
 398                 reg = (void __iomem *) xhci->cap_regs +
 399                                 SSIC_PORT_CFG2 +
 400                                 i * SSIC_PORT_CFG2_OFFSET;
 401
 402                 /* Notify SSIC that SSIC profile programming is not done. */
 403                 val = readl(reg) & ~PROG_DONE;
 404                 writel(val, reg);
 405
 406                 /* Mark SSIC port as unused(suspend) or used(resume) */
 407                 val = readl(reg);
 408                 if (suspend)
 409                         val |= SSIC_PORT_UNUSED;
 410                 else
 411                         val &= ~SSIC_PORT_UNUSED;
 412                 writel(val, reg);
 413
 414                 /* Notify SSIC that SSIC profile programming is done */
 415                 val = readl(reg) | PROG_DONE;
 416                 writel(val, reg);
 417                 readl(reg);
 418         }
 419 }
 420
 421 /*
 422  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 423  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 424  */
 425 static void xhci_pme_quirk(struct usb_hcd *hcd)
 426 {
 427         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 428         void __iomem *reg;
 429         u32 val;
 430
 431         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 432         val = readl(reg);
 433         writel(val | BIT(28), reg);
 434         readl(reg);
 435 }
 436
 437 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 438 {
 439         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 440         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 441         int                     ret;
 442
 443         /*
 444          * Systems with the TI redriver that loses port status change events
 445          * need to have the registers polled during D3, so avoid D3cold.
 446          */
 447         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 448                 pci_d3cold_disable(pdev);
 449
 450         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 451                 xhci_pme_quirk(hcd);
 452
 453         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 454                 xhci_ssic_port_unused_quirk(hcd, true);
 455
 456         ret = xhci_suspend(xhci, do_wakeup);
 457         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 458                 xhci_ssic_port_unused_quirk(hcd, false);
 459
 460         return ret;
 461 }
 462
 463 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 464 {
 465         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 466         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 467         int                     retval = 0;
 468
 469         /* The BIOS on systems with the Intel Panther Point chipset may or may
 470          * not support xHCI natively.  That means that during system resume, it
 471          * may switch the ports back to EHCI so that users can use their
 472          * keyboard to select a kernel from GRUB after resume from hibernate.
 473          *
 474          * The BIOS is supposed to remember whether the OS had xHCI ports
 475          * enabled before resume, and switch the ports back to xHCI when the
 476          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 477          * writers.
 478          *
 479          * Unconditionally switch the ports back to xHCI after a system resume.
 480          * It should not matter whether the EHCI or xHCI controller is
 481          * resumed first. It's enough to do the switchover in xHCI because
 482          * USB core won't notice anything as the hub driver doesn't start
 483          * running again until after all the devices (including both EHCI and
 484          * xHCI host controllers) have been resumed.
 485          */
 486
 487         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 488                 usb_enable_intel_xhci_ports(pdev);
 489
 490         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 491                 xhci_ssic_port_unused_quirk(hcd, false);
 492
 493         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 494                 xhci_pme_quirk(hcd);
 495
 496         retval = xhci_resume(xhci, hibernated);
 497         return retval;
 498 }
 499
 500 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 501 {
 502         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 503         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 504
 505         xhci_shutdown(hcd);
 506
 507         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 508         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 509                 pci_set_power_state(pdev, PCI_D3hot);
 510 }
 511 #endif /* CONFIG_PM */
 512
 513 /*-------------------------------------------------------------------------*/
 514
 515 /* PCI driver selection metadata; PCI hotplugging uses this */
 516 static const struct pci_device_id pci_ids[] = { {
 517         /* handle any USB 3.0 xHCI controller */
 518         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 519         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 520         },
 521         { /* end: all zeroes */ }
 522 };
 523 MODULE_DEVICE_TABLE(pci, pci_ids);
 524
 525 /* pci driver glue; this is a "new style" PCI driver module */
 526 static struct pci_driver xhci_pci_driver = {
 527         .name =         (char *) hcd_name,
 528         .id_table =     pci_ids,
 529
 530         .probe =        xhci_pci_probe,
 531         .remove =       xhci_pci_remove,
 532         /* suspend and resume implemented later */
 533
 534         .shutdown =     usb_hcd_pci_shutdown,
 535 #ifdef CONFIG_PM
 536         .driver = {
 537                 .pm = &usb_hcd_pci_pm_ops
 538         },
 539 #endif
 540 };
 541
 542 static int __init xhci_pci_init(void)
 543 {
 544         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 545 #ifdef CONFIG_PM
 546         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 547         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 548         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 549 #endif
 550         return pci_register_driver(&xhci_pci_driver);
 551 }
 552 module_init(xhci_pci_init);
 553
 554 static void __exit xhci_pci_exit(void)
 555 {
 556         pci_unregister_driver(&xhci_pci_driver);
 557 }
 558 module_exit(xhci_pci_exit);
 559
 560 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 561 MODULE_LICENSE("GPL");