drivers/usb/isp1760/isp1760-hcd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the NXP ISP1760 chip
   4  *
   5  * However, the code might contain some bugs. What doesn't work for sure is:
   6  * - ISO
   7  * - OTG
   8  e The interrupt line is configured as active low, level.
   9  *
  10  * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  11  *
  12  * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
  13  *
  14  */
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/slab.h>
  19 #include <linux/list.h>
  20 #include <linux/usb.h>
  21 #include <linux/usb/hcd.h>
  22 #include <linux/debugfs.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/io.h>
  25 #include <linux/mm.h>
  26 #include <linux/timer.h>
  27 #include <asm/unaligned.h>
  28 #include <asm/cacheflush.h>
  29
  30 #include "isp1760-core.h"
  31 #include "isp1760-hcd.h"
  32 #include "isp1760-regs.h"
  33
  34 static struct kmem_cache *qtd_cachep;
  35 static struct kmem_cache *qh_cachep;
  36 static struct kmem_cache *urb_listitem_cachep;
  37
  38 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
  39                 struct isp1760_qtd *qtd);
  40
  41 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  42 {
  43         return *(struct isp1760_hcd **)hcd->hcd_priv;
  44 }
  45
  46 /* urb state*/
  47 #define DELETE_URB              (0x0008)
  48 #define NO_TRANSFER_ACTIVE      (0xffffffff)
  49
  50 /* Philips Proprietary Transfer Descriptor (PTD) */
  51 typedef __u32 __bitwise __dw;
  52 struct ptd {
  53         __dw dw0;
  54         __dw dw1;
  55         __dw dw2;
  56         __dw dw3;
  57         __dw dw4;
  58         __dw dw5;
  59         __dw dw6;
  60         __dw dw7;
  61 };
  62 #define PTD_OFFSET              0x0400
  63 #define ISO_PTD_OFFSET          0x0400
  64 #define INT_PTD_OFFSET          0x0800
  65 #define ATL_PTD_OFFSET          0x0c00
  66 #define PAYLOAD_OFFSET          0x1000
  67
  68
  69 /* ATL */
  70 /* DW0 */
  71 #define DW0_VALID_BIT                   1
  72 #define FROM_DW0_VALID(x)               ((x) & 0x01)
  73 #define TO_DW0_LENGTH(x)                (((u32) x) << 3)
  74 #define TO_DW0_MAXPACKET(x)             (((u32) x) << 18)
  75 #define TO_DW0_MULTI(x)                 (((u32) x) << 29)
  76 #define TO_DW0_ENDPOINT(x)              (((u32) x) << 31)
  77 /* DW1 */
  78 #define TO_DW1_DEVICE_ADDR(x)           (((u32) x) << 3)
  79 #define TO_DW1_PID_TOKEN(x)             (((u32) x) << 10)
  80 #define DW1_TRANS_BULK                  ((u32) 2 << 12)
  81 #define DW1_TRANS_INT                   ((u32) 3 << 12)
  82 #define DW1_TRANS_SPLIT                 ((u32) 1 << 14)
  83 #define DW1_SE_USB_LOSPEED              ((u32) 2 << 16)
  84 #define TO_DW1_PORT_NUM(x)              (((u32) x) << 18)
  85 #define TO_DW1_HUB_NUM(x)               (((u32) x) << 25)
  86 /* DW2 */
  87 #define TO_DW2_DATA_START_ADDR(x)       (((u32) x) << 8)
  88 #define TO_DW2_RL(x)                    ((x) << 25)
  89 #define FROM_DW2_RL(x)                  (((x) >> 25) & 0xf)
  90 /* DW3 */
  91 #define FROM_DW3_NRBYTESTRANSFERRED(x)          ((x) & 0x7fff)
  92 #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x)      ((x) & 0x07ff)
  93 #define TO_DW3_NAKCOUNT(x)              ((x) << 19)
  94 #define FROM_DW3_NAKCOUNT(x)            (((x) >> 19) & 0xf)
  95 #define TO_DW3_CERR(x)                  ((x) << 23)
  96 #define FROM_DW3_CERR(x)                (((x) >> 23) & 0x3)
  97 #define TO_DW3_DATA_TOGGLE(x)           ((x) << 25)
  98 #define FROM_DW3_DATA_TOGGLE(x)         (((x) >> 25) & 0x1)
  99 #define TO_DW3_PING(x)                  ((x) << 26)
 100 #define FROM_DW3_PING(x)                (((x) >> 26) & 0x1)
 101 #define DW3_ERROR_BIT                   (1 << 28)
 102 #define DW3_BABBLE_BIT                  (1 << 29)
 103 #define DW3_HALT_BIT                    (1 << 30)
 104 #define DW3_ACTIVE_BIT                  (1 << 31)
 105 #define FROM_DW3_ACTIVE(x)              (((x) >> 31) & 0x01)
 106
 107 #define INT_UNDERRUN                    (1 << 2)
 108 #define INT_BABBLE                      (1 << 1)
 109 #define INT_EXACT                       (1 << 0)
 110
 111 #define SETUP_PID       (2)
 112 #define IN_PID          (1)
 113 #define OUT_PID         (0)
 114
 115 /* Errata 1 */
 116 #define RL_COUNTER      (0)
 117 #define NAK_COUNTER     (0)
 118 #define ERR_COUNTER     (2)
 119
 120 struct isp1760_qtd {
 121         u8 packet_type;
 122         void *data_buffer;
 123         u32 payload_addr;
 124
 125         /* the rest is HCD-private */
 126         struct list_head qtd_list;
 127         struct urb *urb;
 128         size_t length;
 129         size_t actual_length;
 130
 131         /* QTD_ENQUEUED:        waiting for transfer (inactive) */
 132         /* QTD_PAYLOAD_ALLOC:   chip mem has been allocated for payload */
 133         /* QTD_XFER_STARTED:    valid ptd has been written to isp176x - only
 134                                 interrupt handler may touch this qtd! */
 135         /* QTD_XFER_COMPLETE:   payload has been transferred successfully */
 136         /* QTD_RETIRE:          transfer error/abort qtd */
 137 #define QTD_ENQUEUED            0
 138 #define QTD_PAYLOAD_ALLOC       1
 139 #define QTD_XFER_STARTED        2
 140 #define QTD_XFER_COMPLETE       3
 141 #define QTD_RETIRE              4
 142         u32 status;
 143 };
 144
 145 /* Queue head, one for each active endpoint */
 146 struct isp1760_qh {
 147         struct list_head qh_list;
 148         struct list_head qtd_list;
 149         u32 toggle;
 150         u32 ping;
 151         int slot;
 152         int tt_buffer_dirty;    /* See USB2.0 spec section 11.17.5 */
 153 };
 154
 155 struct urb_listitem {
 156         struct list_head urb_list;
 157         struct urb *urb;
 158 };
 159
 160 /*
 161  * Access functions for isp176x registers (addresses 0..0x03FF).
 162  */
 163 static u32 reg_read32(void __iomem *base, u32 reg)
 164 {
 165         return isp1760_read32(base, reg);
 166 }
 167
 168 static void reg_write32(void __iomem *base, u32 reg, u32 val)
 169 {
 170         isp1760_write32(base, reg, val);
 171 }
 172
 173 /*
 174  * Access functions for isp176x memory (offset >= 0x0400).
 175  *
 176  * bank_reads8() reads memory locations prefetched by an earlier write to
 177  * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
 178  * bank optimizations, you should use the more generic mem_reads8() below.
 179  *
 180  * For access to ptd memory, use the specialized ptd_read() and ptd_write()
 181  * below.
 182  *
 183  * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
 184  * doesn't quite work because some people have to enforce 32-bit access
 185  */
 186 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
 187                                                         __u32 *dst, u32 bytes)
 188 {
 189         __u32 __iomem *src;
 190         u32 val;
 191         __u8 *src_byteptr;
 192         __u8 *dst_byteptr;
 193
 194         src = src_base + (bank_addr | src_offset);
 195
 196         if (src_offset < PAYLOAD_OFFSET) {
 197                 while (bytes >= 4) {
 198                         *dst = le32_to_cpu(__raw_readl(src));
 199                         bytes -= 4;
 200                         src++;
 201                         dst++;
 202                 }
 203         } else {
 204                 while (bytes >= 4) {
 205                         *dst = __raw_readl(src);
 206                         bytes -= 4;
 207                         src++;
 208                         dst++;
 209                 }
 210         }
 211
 212         if (!bytes)
 213                 return;
 214
 215         /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
 216          * allocated.
 217          */
 218         if (src_offset < PAYLOAD_OFFSET)
 219                 val = le32_to_cpu(__raw_readl(src));
 220         else
 221                 val = __raw_readl(src);
 222
 223         dst_byteptr = (void *) dst;
 224         src_byteptr = (void *) &val;
 225         while (bytes > 0) {
 226                 *dst_byteptr = *src_byteptr;
 227                 dst_byteptr++;
 228                 src_byteptr++;
 229                 bytes--;
 230         }
 231 }
 232
 233 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
 234                                                                 u32 bytes)
 235 {
 236         reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
 237         ndelay(90);
 238         bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
 239 }
 240
 241 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
 242                                                 __u32 const *src, u32 bytes)
 243 {
 244         __u32 __iomem *dst;
 245
 246         dst = dst_base + dst_offset;
 247
 248         if (dst_offset < PAYLOAD_OFFSET) {
 249                 while (bytes >= 4) {
 250                         __raw_writel(cpu_to_le32(*src), dst);
 251                         bytes -= 4;
 252                         src++;
 253                         dst++;
 254                 }
 255         } else {
 256                 while (bytes >= 4) {
 257                         __raw_writel(*src, dst);
 258                         bytes -= 4;
 259                         src++;
 260                         dst++;
 261                 }
 262         }
 263
 264         if (!bytes)
 265                 return;
 266         /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
 267          * extra bytes should not be read by the HW.
 268          */
 269
 270         if (dst_offset < PAYLOAD_OFFSET)
 271                 __raw_writel(cpu_to_le32(*src), dst);
 272         else
 273                 __raw_writel(*src, dst);
 274 }
 275
 276 /*
 277  * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
 278  * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
 279  */
 280 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
 281                                                                 struct ptd *ptd)
 282 {
 283         reg_write32(base, HC_MEMORY_REG,
 284                                 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
 285         ndelay(90);
 286         bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
 287                                                 (void *) ptd, sizeof(*ptd));
 288 }
 289
 290 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
 291                                                                 struct ptd *ptd)
 292 {
 293         mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
 294                                                 &ptd->dw1, 7*sizeof(ptd->dw1));
 295         /* Make sure dw0 gets written last (after other dw's and after payload)
 296            since it contains the enable bit */
 297         wmb();
 298         mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
 299                                                         sizeof(ptd->dw0));
 300 }
 301
 302
 303 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
 304 static void init_memory(struct isp1760_hcd *priv)
 305 {
 306         int i, curr;
 307         u32 payload_addr;
 308
 309         payload_addr = PAYLOAD_OFFSET;
 310         for (i = 0; i < BLOCK_1_NUM; i++) {
 311                 priv->memory_pool[i].start = payload_addr;
 312                 priv->memory_pool[i].size = BLOCK_1_SIZE;
 313                 priv->memory_pool[i].free = 1;
 314                 payload_addr += priv->memory_pool[i].size;
 315         }
 316
 317         curr = i;
 318         for (i = 0; i < BLOCK_2_NUM; i++) {
 319                 priv->memory_pool[curr + i].start = payload_addr;
 320                 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
 321                 priv->memory_pool[curr + i].free = 1;
 322                 payload_addr += priv->memory_pool[curr + i].size;
 323         }
 324
 325         curr = i;
 326         for (i = 0; i < BLOCK_3_NUM; i++) {
 327                 priv->memory_pool[curr + i].start = payload_addr;
 328                 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
 329                 priv->memory_pool[curr + i].free = 1;
 330                 payload_addr += priv->memory_pool[curr + i].size;
 331         }
 332
 333         WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
 334 }
 335
 336 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 337 {
 338         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 339         int i;
 340
 341         WARN_ON(qtd->payload_addr);
 342
 343         if (!qtd->length)
 344                 return;
 345
 346         for (i = 0; i < BLOCKS; i++) {
 347                 if (priv->memory_pool[i].size >= qtd->length &&
 348                                 priv->memory_pool[i].free) {
 349                         priv->memory_pool[i].free = 0;
 350                         qtd->payload_addr = priv->memory_pool[i].start;
 351                         return;
 352                 }
 353         }
 354 }
 355
 356 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 357 {
 358         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 359         int i;
 360
 361         if (!qtd->payload_addr)
 362                 return;
 363
 364         for (i = 0; i < BLOCKS; i++) {
 365                 if (priv->memory_pool[i].start == qtd->payload_addr) {
 366                         WARN_ON(priv->memory_pool[i].free);
 367                         priv->memory_pool[i].free = 1;
 368                         qtd->payload_addr = 0;
 369                         return;
 370                 }
 371         }
 372
 373         dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
 374                                                 __func__, qtd->payload_addr);
 375         WARN_ON(1);
 376         qtd->payload_addr = 0;
 377 }
 378
 379 static int handshake(struct usb_hcd *hcd, u32 reg,
 380                       u32 mask, u32 done, int usec)
 381 {
 382         u32 result;
 383
 384         do {
 385                 result = reg_read32(hcd->regs, reg);
 386                 if (result == ~0)
 387                         return -ENODEV;
 388                 result &= mask;
 389                 if (result == done)
 390                         return 0;
 391                 udelay(1);
 392                 usec--;
 393         } while (usec > 0);
 394         return -ETIMEDOUT;
 395 }
 396
 397 /* reset a non-running (STS_HALT == 1) controller */
 398 static int ehci_reset(struct usb_hcd *hcd)
 399 {
 400         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 401
 402         u32 command = reg_read32(hcd->regs, HC_USBCMD);
 403
 404         command |= CMD_RESET;
 405         reg_write32(hcd->regs, HC_USBCMD, command);
 406         hcd->state = HC_STATE_HALT;
 407         priv->next_statechange = jiffies;
 408
 409         return handshake(hcd, HC_USBCMD, CMD_RESET, 0, 250 * 1000);
 410 }
 411
 412 static struct isp1760_qh *qh_alloc(gfp_t flags)
 413 {
 414         struct isp1760_qh *qh;
 415
 416         qh = kmem_cache_zalloc(qh_cachep, flags);
 417         if (!qh)
 418                 return NULL;
 419
 420         INIT_LIST_HEAD(&qh->qh_list);
 421         INIT_LIST_HEAD(&qh->qtd_list);
 422         qh->slot = -1;
 423
 424         return qh;
 425 }
 426
 427 static void qh_free(struct isp1760_qh *qh)
 428 {
 429         WARN_ON(!list_empty(&qh->qtd_list));
 430         WARN_ON(qh->slot > -1);
 431         kmem_cache_free(qh_cachep, qh);
 432 }
 433
 434 /* one-time init, only for memory state */
 435 static int priv_init(struct usb_hcd *hcd)
 436 {
 437         struct isp1760_hcd              *priv = hcd_to_priv(hcd);
 438         u32                     hcc_params;
 439         int i;
 440
 441         spin_lock_init(&priv->lock);
 442
 443         for (i = 0; i < QH_END; i++)
 444                 INIT_LIST_HEAD(&priv->qh_list[i]);
 445
 446         /*
 447          * hw default: 1K periodic list heads, one per frame.
 448          * periodic_size can shrink by USBCMD update if hcc_params allows.
 449          */
 450         priv->periodic_size = DEFAULT_I_TDPS;
 451
 452         /* controllers may cache some of the periodic schedule ... */
 453         hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
 454         /* full frame cache */
 455         if (HCC_ISOC_CACHE(hcc_params))
 456                 priv->i_thresh = 8;
 457         else /* N microframes cached */
 458                 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 459
 460         return 0;
 461 }
 462
 463 static int isp1760_hc_setup(struct usb_hcd *hcd)
 464 {
 465         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 466         int result;
 467         u32 scratch, hwmode;
 468
 469         reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
 470         /* Change bus pattern */
 471         scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 472         scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
 473         if (scratch != 0xdeadbabe) {
 474                 dev_err(hcd->self.controller, "Scratch test failed.\n");
 475                 return -ENODEV;
 476         }
 477
 478         /*
 479          * The RESET_HC bit in the SW_RESET register is supposed to reset the
 480          * host controller without touching the CPU interface registers, but at
 481          * least on the ISP1761 it seems to behave as the RESET_ALL bit and
 482          * reset the whole device. We thus can't use it here, so let's reset
 483          * the host controller through the EHCI USB Command register. The device
 484          * has been reset in core code anyway, so this shouldn't matter.
 485          */
 486         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
 487         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 488         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 489         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 490
 491         result = ehci_reset(hcd);
 492         if (result)
 493                 return result;
 494
 495         /* Step 11 passed */
 496
 497         /* ATL reset */
 498         hwmode = reg_read32(hcd->regs, HC_HW_MODE_CTRL) & ~ALL_ATX_RESET;
 499         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
 500         mdelay(10);
 501         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 502
 503         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
 504
 505         priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
 506
 507         return priv_init(hcd);
 508 }
 509
 510 static u32 base_to_chip(u32 base)
 511 {
 512         return ((base - 0x400) >> 3);
 513 }
 514
 515 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
 516 {
 517         struct urb *urb;
 518
 519         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 520                 return 1;
 521
 522         urb = qtd->urb;
 523         qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
 524         return (qtd->urb != urb);
 525 }
 526
 527 /* magic numbers that can affect system performance */
 528 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
 529 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
 530 #define EHCI_TUNE_RL_TT         0
 531 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
 532 #define EHCI_TUNE_MULT_TT       1
 533 #define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
 534
 535 static void create_ptd_atl(struct isp1760_qh *qh,
 536                         struct isp1760_qtd *qtd, struct ptd *ptd)
 537 {
 538         u32 maxpacket;
 539         u32 multi;
 540         u32 rl = RL_COUNTER;
 541         u32 nak = NAK_COUNTER;
 542
 543         memset(ptd, 0, sizeof(*ptd));
 544
 545         /* according to 3.6.2, max packet len can not be > 0x400 */
 546         maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
 547                                                 usb_pipeout(qtd->urb->pipe));
 548         multi =  1 + ((maxpacket >> 11) & 0x3);
 549         maxpacket &= 0x7ff;
 550
 551         /* DW0 */
 552         ptd->dw0 = DW0_VALID_BIT;
 553         ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
 554         ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
 555         ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
 556
 557         /* DW1 */
 558         ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
 559         ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
 560         ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
 561
 562         if (usb_pipebulk(qtd->urb->pipe))
 563                 ptd->dw1 |= DW1_TRANS_BULK;
 564         else if  (usb_pipeint(qtd->urb->pipe))
 565                 ptd->dw1 |= DW1_TRANS_INT;
 566
 567         if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
 568                 /* split transaction */
 569
 570                 ptd->dw1 |= DW1_TRANS_SPLIT;
 571                 if (qtd->urb->dev->speed == USB_SPEED_LOW)
 572                         ptd->dw1 |= DW1_SE_USB_LOSPEED;
 573
 574                 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
 575                 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
 576
 577                 /* SE bit for Split INT transfers */
 578                 if (usb_pipeint(qtd->urb->pipe) &&
 579                                 (qtd->urb->dev->speed == USB_SPEED_LOW))
 580                         ptd->dw1 |= 2 << 16;
 581
 582                 rl = 0;
 583                 nak = 0;
 584         } else {
 585                 ptd->dw0 |= TO_DW0_MULTI(multi);
 586                 if (usb_pipecontrol(qtd->urb->pipe) ||
 587                                                 usb_pipebulk(qtd->urb->pipe))
 588                         ptd->dw3 |= TO_DW3_PING(qh->ping);
 589         }
 590         /* DW2 */
 591         ptd->dw2 = 0;
 592         ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
 593         ptd->dw2 |= TO_DW2_RL(rl);
 594
 595         /* DW3 */
 596         ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
 597         ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
 598         if (usb_pipecontrol(qtd->urb->pipe)) {
 599                 if (qtd->data_buffer == qtd->urb->setup_packet)
 600                         ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
 601                 else if (last_qtd_of_urb(qtd, qh))
 602                         ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
 603         }
 604
 605         ptd->dw3 |= DW3_ACTIVE_BIT;
 606         /* Cerr */
 607         ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
 608 }
 609
 610 static void transform_add_int(struct isp1760_qh *qh,
 611                         struct isp1760_qtd *qtd, struct ptd *ptd)
 612 {
 613         u32 usof;
 614         u32 period;
 615
 616         /*
 617          * Most of this is guessing. ISP1761 datasheet is quite unclear, and
 618          * the algorithm from the original Philips driver code, which was
 619          * pretty much used in this driver before as well, is quite horrendous
 620          * and, i believe, incorrect. The code below follows the datasheet and
 621          * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
 622          * more reliable this way (fingers crossed...).
 623          */
 624
 625         if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
 626                 /* urb->interval is in units of microframes (1/8 ms) */
 627                 period = qtd->urb->interval >> 3;
 628
 629                 if (qtd->urb->interval > 4)
 630                         usof = 0x01; /* One bit set =>
 631                                                 interval 1 ms * uFrame-match */
 632                 else if (qtd->urb->interval > 2)
 633                         usof = 0x22; /* Two bits set => interval 1/2 ms */
 634                 else if (qtd->urb->interval > 1)
 635                         usof = 0x55; /* Four bits set => interval 1/4 ms */
 636                 else
 637                         usof = 0xff; /* All bits set => interval 1/8 ms */
 638         } else {
 639                 /* urb->interval is in units of frames (1 ms) */
 640                 period = qtd->urb->interval;
 641                 usof = 0x0f;            /* Execute Start Split on any of the
 642                                            four first uFrames */
 643
 644                 /*
 645                  * First 8 bits in dw5 is uSCS and "specifies which uSOF the
 646                  * complete split needs to be sent. Valid only for IN." Also,
 647                  * "All bits can be set to one for every transfer." (p 82,
 648                  * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
 649                  * that number come from? 0xff seems to work fine...
 650                  */
 651                 /* ptd->dw5 = 0x1c; */
 652                 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
 653         }
 654
 655         period = period >> 1;/* Ensure equal or shorter period than requested */
 656         period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
 657
 658         ptd->dw2 |= period;
 659         ptd->dw4 = usof;
 660 }
 661
 662 static void create_ptd_int(struct isp1760_qh *qh,
 663                         struct isp1760_qtd *qtd, struct ptd *ptd)
 664 {
 665         create_ptd_atl(qh, qtd, ptd);
 666         transform_add_int(qh, qtd, ptd);
 667 }
 668
 669 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
 670 __releases(priv->lock)
 671 __acquires(priv->lock)
 672 {
 673         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 674
 675         if (!urb->unlinked) {
 676                 if (urb->status == -EINPROGRESS)
 677                         urb->status = 0;
 678         }
 679
 680         if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
 681                 void *ptr;
 682                 for (ptr = urb->transfer_buffer;
 683                      ptr < urb->transfer_buffer + urb->transfer_buffer_length;
 684                      ptr += PAGE_SIZE)
 685                         flush_dcache_page(virt_to_page(ptr));
 686         }
 687
 688         /* complete() can reenter this HCD */
 689         usb_hcd_unlink_urb_from_ep(hcd, urb);
 690         spin_unlock(&priv->lock);
 691         usb_hcd_giveback_urb(hcd, urb, urb->status);
 692         spin_lock(&priv->lock);
 693 }
 694
 695 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
 696                                                                 u8 packet_type)
 697 {
 698         struct isp1760_qtd *qtd;
 699
 700         qtd = kmem_cache_zalloc(qtd_cachep, flags);
 701         if (!qtd)
 702                 return NULL;
 703
 704         INIT_LIST_HEAD(&qtd->qtd_list);
 705         qtd->urb = urb;
 706         qtd->packet_type = packet_type;
 707         qtd->status = QTD_ENQUEUED;
 708         qtd->actual_length = 0;
 709
 710         return qtd;
 711 }
 712
 713 static void qtd_free(struct isp1760_qtd *qtd)
 714 {
 715         WARN_ON(qtd->payload_addr);
 716         kmem_cache_free(qtd_cachep, qtd);
 717 }
 718
 719 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
 720                                 struct isp1760_slotinfo *slots,
 721                                 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
 722                                 struct ptd *ptd)
 723 {
 724         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 725         int skip_map;
 726
 727         WARN_ON((slot < 0) || (slot > 31));
 728         WARN_ON(qtd->length && !qtd->payload_addr);
 729         WARN_ON(slots[slot].qtd);
 730         WARN_ON(slots[slot].qh);
 731         WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
 732
 733         /* Make sure done map has not triggered from some unlinked transfer */
 734         if (ptd_offset == ATL_PTD_OFFSET) {
 735                 priv->atl_done_map |= reg_read32(hcd->regs,
 736                                                 HC_ATL_PTD_DONEMAP_REG);
 737                 priv->atl_done_map &= ~(1 << slot);
 738         } else {
 739                 priv->int_done_map |= reg_read32(hcd->regs,
 740                                                 HC_INT_PTD_DONEMAP_REG);
 741                 priv->int_done_map &= ~(1 << slot);
 742         }
 743
 744         qh->slot = slot;
 745         qtd->status = QTD_XFER_STARTED;
 746         slots[slot].timestamp = jiffies;
 747         slots[slot].qtd = qtd;
 748         slots[slot].qh = qh;
 749         ptd_write(hcd->regs, ptd_offset, slot, ptd);
 750
 751         if (ptd_offset == ATL_PTD_OFFSET) {
 752                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
 753                 skip_map &= ~(1 << qh->slot);
 754                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
 755         } else {
 756                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
 757                 skip_map &= ~(1 << qh->slot);
 758                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
 759         }
 760 }
 761
 762 static int is_short_bulk(struct isp1760_qtd *qtd)
 763 {
 764         return (usb_pipebulk(qtd->urb->pipe) &&
 765                                         (qtd->actual_length < qtd->length));
 766 }
 767
 768 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
 769                                                 struct list_head *urb_list)
 770 {
 771         int last_qtd;
 772         struct isp1760_qtd *qtd, *qtd_next;
 773         struct urb_listitem *urb_listitem;
 774
 775         list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
 776                 if (qtd->status < QTD_XFER_COMPLETE)
 777                         break;
 778
 779                 last_qtd = last_qtd_of_urb(qtd, qh);
 780
 781                 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
 782                         qtd_next->status = QTD_RETIRE;
 783
 784                 if (qtd->status == QTD_XFER_COMPLETE) {
 785                         if (qtd->actual_length) {
 786                                 switch (qtd->packet_type) {
 787                                 case IN_PID:
 788                                         mem_reads8(hcd->regs, qtd->payload_addr,
 789                                                         qtd->data_buffer,
 790                                                         qtd->actual_length);
 791                                         /* Fall through (?) */
 792                                 case OUT_PID:
 793                                         qtd->urb->actual_length +=
 794                                                         qtd->actual_length;
 795                                         /* Fall through ... */
 796                                 case SETUP_PID:
 797                                         break;
 798                                 }
 799                         }
 800
 801                         if (is_short_bulk(qtd)) {
 802                                 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
 803                                         qtd->urb->status = -EREMOTEIO;
 804                                 if (!last_qtd)
 805                                         qtd_next->status = QTD_RETIRE;
 806                         }
 807                 }
 808
 809                 if (qtd->payload_addr)
 810                         free_mem(hcd, qtd);
 811
 812                 if (last_qtd) {
 813                         if ((qtd->status == QTD_RETIRE) &&
 814                                         (qtd->urb->status == -EINPROGRESS))
 815                                 qtd->urb->status = -EPIPE;
 816                         /* Defer calling of urb_done() since it releases lock */
 817                         urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
 818                                                                 GFP_ATOMIC);
 819                         if (unlikely(!urb_listitem))
 820                                 break; /* Try again on next call */
 821                         urb_listitem->urb = qtd->urb;
 822                         list_add_tail(&urb_listitem->urb_list, urb_list);
 823                 }
 824
 825                 list_del(&qtd->qtd_list);
 826                 qtd_free(qtd);
 827         }
 828 }
 829
 830 #define ENQUEUE_DEPTH   2
 831 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
 832 {
 833         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 834         int ptd_offset;
 835         struct isp1760_slotinfo *slots;
 836         int curr_slot, free_slot;
 837         int n;
 838         struct ptd ptd;
 839         struct isp1760_qtd *qtd;
 840
 841         if (unlikely(list_empty(&qh->qtd_list))) {
 842                 WARN_ON(1);
 843                 return;
 844         }
 845
 846         /* Make sure this endpoint's TT buffer is clean before queueing ptds */
 847         if (qh->tt_buffer_dirty)
 848                 return;
 849
 850         if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
 851                                                         qtd_list)->urb->pipe)) {
 852                 ptd_offset = INT_PTD_OFFSET;
 853                 slots = priv->int_slots;
 854         } else {
 855                 ptd_offset = ATL_PTD_OFFSET;
 856                 slots = priv->atl_slots;
 857         }
 858
 859         free_slot = -1;
 860         for (curr_slot = 0; curr_slot < 32; curr_slot++) {
 861                 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
 862                         free_slot = curr_slot;
 863                 if (slots[curr_slot].qh == qh)
 864                         break;
 865         }
 866
 867         n = 0;
 868         list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
 869                 if (qtd->status == QTD_ENQUEUED) {
 870                         WARN_ON(qtd->payload_addr);
 871                         alloc_mem(hcd, qtd);
 872                         if ((qtd->length) && (!qtd->payload_addr))
 873                                 break;
 874
 875                         if ((qtd->length) &&
 876                             ((qtd->packet_type == SETUP_PID) ||
 877                              (qtd->packet_type == OUT_PID))) {
 878                                 mem_writes8(hcd->regs, qtd->payload_addr,
 879                                                 qtd->data_buffer, qtd->length);
 880                         }
 881
 882                         qtd->status = QTD_PAYLOAD_ALLOC;
 883                 }
 884
 885                 if (qtd->status == QTD_PAYLOAD_ALLOC) {
 886 /*
 887                         if ((curr_slot > 31) && (free_slot == -1))
 888                                 dev_dbg(hcd->self.controller, "%s: No slot "
 889                                         "available for transfer\n", __func__);
 890 */
 891                         /* Start xfer for this endpoint if not already done */
 892                         if ((curr_slot > 31) && (free_slot > -1)) {
 893                                 if (usb_pipeint(qtd->urb->pipe))
 894                                         create_ptd_int(qh, qtd, &ptd);
 895                                 else
 896                                         create_ptd_atl(qh, qtd, &ptd);
 897
 898                                 start_bus_transfer(hcd, ptd_offset, free_slot,
 899                                                         slots, qtd, qh, &ptd);
 900                                 curr_slot = free_slot;
 901                         }
 902
 903                         n++;
 904                         if (n >= ENQUEUE_DEPTH)
 905                                 break;
 906                 }
 907         }
 908 }
 909
 910 static void schedule_ptds(struct usb_hcd *hcd)
 911 {
 912         struct isp1760_hcd *priv;
 913         struct isp1760_qh *qh, *qh_next;
 914         struct list_head *ep_queue;
 915         LIST_HEAD(urb_list);
 916         struct urb_listitem *urb_listitem, *urb_listitem_next;
 917         int i;
 918
 919         if (!hcd) {
 920                 WARN_ON(1);
 921                 return;
 922         }
 923
 924         priv = hcd_to_priv(hcd);
 925
 926         /*
 927          * check finished/retired xfers, transfer payloads, call urb_done()
 928          */
 929         for (i = 0; i < QH_END; i++) {
 930                 ep_queue = &priv->qh_list[i];
 931                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
 932                         collect_qtds(hcd, qh, &urb_list);
 933                         if (list_empty(&qh->qtd_list))
 934                                 list_del(&qh->qh_list);
 935                 }
 936         }
 937
 938         list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
 939                                                                 urb_list) {
 940                 isp1760_urb_done(hcd, urb_listitem->urb);
 941                 kmem_cache_free(urb_listitem_cachep, urb_listitem);
 942         }
 943
 944         /*
 945          * Schedule packets for transfer.
 946          *
 947          * According to USB2.0 specification:
 948          *
 949          * 1st prio: interrupt xfers, up to 80 % of bandwidth
 950          * 2nd prio: control xfers
 951          * 3rd prio: bulk xfers
 952          *
 953          * ... but let's use a simpler scheme here (mostly because ISP1761 doc
 954          * is very unclear on how to prioritize traffic):
 955          *
 956          * 1) Enqueue any queued control transfers, as long as payload chip mem
 957          *    and PTD ATL slots are available.
 958          * 2) Enqueue any queued INT transfers, as long as payload chip mem
 959          *    and PTD INT slots are available.
 960          * 3) Enqueue any queued bulk transfers, as long as payload chip mem
 961          *    and PTD ATL slots are available.
 962          *
 963          * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
 964          * conservation of chip mem and performance.
 965          *
 966          * I'm sure this scheme could be improved upon!
 967          */
 968         for (i = 0; i < QH_END; i++) {
 969                 ep_queue = &priv->qh_list[i];
 970                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
 971                         enqueue_qtds(hcd, qh);
 972         }
 973 }
 974
 975 #define PTD_STATE_QTD_DONE      1
 976 #define PTD_STATE_QTD_RELOAD    2
 977 #define PTD_STATE_URB_RETIRE    3
 978
 979 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
 980                                                                 struct urb *urb)
 981 {
 982         __dw dw4;
 983         int i;
 984
 985         dw4 = ptd->dw4;
 986         dw4 >>= 8;
 987
 988         /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
 989            need to handle these errors? Is it done in hardware? */
 990
 991         if (ptd->dw3 & DW3_HALT_BIT) {
 992
 993                 urb->status = -EPROTO; /* Default unknown error */
 994
 995                 for (i = 0; i < 8; i++) {
 996                         switch (dw4 & 0x7) {
 997                         case INT_UNDERRUN:
 998                                 dev_dbg(hcd->self.controller, "%s: underrun "
 999                                                 "during uFrame %d\n",
1000                                                 __func__, i);
1001                                 urb->status = -ECOMM; /* Could not write data */
1002                                 break;
1003                         case INT_EXACT:
1004                                 dev_dbg(hcd->self.controller, "%s: transaction "
1005                                                 "error during uFrame %d\n",
1006                                                 __func__, i);
1007                                 urb->status = -EPROTO; /* timeout, bad CRC, PID
1008                                                           error etc. */
1009                                 break;
1010                         case INT_BABBLE:
1011                                 dev_dbg(hcd->self.controller, "%s: babble "
1012                                                 "error during uFrame %d\n",
1013                                                 __func__, i);
1014                                 urb->status = -EOVERFLOW;
1015                                 break;
1016                         }
1017                         dw4 >>= 3;
1018                 }
1019
1020                 return PTD_STATE_URB_RETIRE;
1021         }
1022
1023         return PTD_STATE_QTD_DONE;
1024 }
1025
1026 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1027                                                                 struct urb *urb)
1028 {
1029         WARN_ON(!ptd);
1030         if (ptd->dw3 & DW3_HALT_BIT) {
1031                 if (ptd->dw3 & DW3_BABBLE_BIT)
1032                         urb->status = -EOVERFLOW;
1033                 else if (FROM_DW3_CERR(ptd->dw3))
1034                         urb->status = -EPIPE;  /* Stall */
1035                 else if (ptd->dw3 & DW3_ERROR_BIT)
1036                         urb->status = -EPROTO; /* XactErr */
1037                 else
1038                         urb->status = -EPROTO; /* Unknown */
1039 /*
1040                 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1041                         "        dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1042                         "        dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1043                         __func__,
1044                         ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1045                         ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1046 */
1047                 return PTD_STATE_URB_RETIRE;
1048         }
1049
1050         if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1051                 /* Transfer Error, *but* active and no HALT -> reload */
1052                 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1053                 return PTD_STATE_QTD_RELOAD;
1054         }
1055
1056         if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1057                 /*
1058                  * NAKs are handled in HW by the chip. Usually if the
1059                  * device is not able to send data fast enough.
1060                  * This happens mostly on slower hardware.
1061                  */
1062                 return PTD_STATE_QTD_RELOAD;
1063         }
1064
1065         return PTD_STATE_QTD_DONE;
1066 }
1067
1068 static void handle_done_ptds(struct usb_hcd *hcd)
1069 {
1070         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1071         struct ptd ptd;
1072         struct isp1760_qh *qh;
1073         int slot;
1074         int state;
1075         struct isp1760_slotinfo *slots;
1076         u32 ptd_offset;
1077         struct isp1760_qtd *qtd;
1078         int modified;
1079         int skip_map;
1080
1081         skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1082         priv->int_done_map &= ~skip_map;
1083         skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1084         priv->atl_done_map &= ~skip_map;
1085
1086         modified = priv->int_done_map || priv->atl_done_map;
1087
1088         while (priv->int_done_map || priv->atl_done_map) {
1089                 if (priv->int_done_map) {
1090                         /* INT ptd */
1091                         slot = __ffs(priv->int_done_map);
1092                         priv->int_done_map &= ~(1 << slot);
1093                         slots = priv->int_slots;
1094                         /* This should not trigger, and could be removed if
1095                            noone have any problems with it triggering: */
1096                         if (!slots[slot].qh) {
1097                                 WARN_ON(1);
1098                                 continue;
1099                         }
1100                         ptd_offset = INT_PTD_OFFSET;
1101                         ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1102                         state = check_int_transfer(hcd, &ptd,
1103                                                         slots[slot].qtd->urb);
1104                 } else {
1105                         /* ATL ptd */
1106                         slot = __ffs(priv->atl_done_map);
1107                         priv->atl_done_map &= ~(1 << slot);
1108                         slots = priv->atl_slots;
1109                         /* This should not trigger, and could be removed if
1110                            noone have any problems with it triggering: */
1111                         if (!slots[slot].qh) {
1112                                 WARN_ON(1);
1113                                 continue;
1114                         }
1115                         ptd_offset = ATL_PTD_OFFSET;
1116                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1117                         state = check_atl_transfer(hcd, &ptd,
1118                                                         slots[slot].qtd->urb);
1119                 }
1120
1121                 qtd = slots[slot].qtd;
1122                 slots[slot].qtd = NULL;
1123                 qh = slots[slot].qh;
1124                 slots[slot].qh = NULL;
1125                 qh->slot = -1;
1126
1127                 WARN_ON(qtd->status != QTD_XFER_STARTED);
1128
1129                 switch (state) {
1130                 case PTD_STATE_QTD_DONE:
1131                         if ((usb_pipeint(qtd->urb->pipe)) &&
1132                                        (qtd->urb->dev->speed != USB_SPEED_HIGH))
1133                                 qtd->actual_length =
1134                                        FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1135                         else
1136                                 qtd->actual_length =
1137                                         FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1138
1139                         qtd->status = QTD_XFER_COMPLETE;
1140                         if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1141                                                         is_short_bulk(qtd))
1142                                 qtd = NULL;
1143                         else
1144                                 qtd = list_entry(qtd->qtd_list.next,
1145                                                         typeof(*qtd), qtd_list);
1146
1147                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1148                         qh->ping = FROM_DW3_PING(ptd.dw3);
1149                         break;
1150
1151                 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1152                         qtd->status = QTD_PAYLOAD_ALLOC;
1153                         ptd.dw0 |= DW0_VALID_BIT;
1154                         /* RL counter = ERR counter */
1155                         ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1156                         ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1157                         ptd.dw3 &= ~TO_DW3_CERR(3);
1158                         ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1159                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1160                         qh->ping = FROM_DW3_PING(ptd.dw3);
1161                         break;
1162
1163                 case PTD_STATE_URB_RETIRE:
1164                         qtd->status = QTD_RETIRE;
1165                         if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1166                                         (qtd->urb->status != -EPIPE) &&
1167                                         (qtd->urb->status != -EREMOTEIO)) {
1168                                 qh->tt_buffer_dirty = 1;
1169                                 if (usb_hub_clear_tt_buffer(qtd->urb))
1170                                         /* Clear failed; let's hope things work
1171                                            anyway */
1172                                         qh->tt_buffer_dirty = 0;
1173                         }
1174                         qtd = NULL;
1175                         qh->toggle = 0;
1176                         qh->ping = 0;
1177                         break;
1178
1179                 default:
1180                         WARN_ON(1);
1181                         continue;
1182                 }
1183
1184                 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1185                         if (slots == priv->int_slots) {
1186                                 if (state == PTD_STATE_QTD_RELOAD)
1187                                         dev_err(hcd->self.controller,
1188                                                 "%s: PTD_STATE_QTD_RELOAD on "
1189                                                 "interrupt packet\n", __func__);
1190                                 if (state != PTD_STATE_QTD_RELOAD)
1191                                         create_ptd_int(qh, qtd, &ptd);
1192                         } else {
1193                                 if (state != PTD_STATE_QTD_RELOAD)
1194                                         create_ptd_atl(qh, qtd, &ptd);
1195                         }
1196
1197                         start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1198                                 qh, &ptd);
1199                 }
1200         }
1201
1202         if (modified)
1203                 schedule_ptds(hcd);
1204 }
1205
1206 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1207 {
1208         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1209         u32 imask;
1210         irqreturn_t irqret = IRQ_NONE;
1211
1212         spin_lock(&priv->lock);
1213
1214         if (!(hcd->state & HC_STATE_RUNNING))
1215                 goto leave;
1216
1217         imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1218         if (unlikely(!imask))
1219                 goto leave;
1220         reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1221
1222         priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1223         priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1224
1225         handle_done_ptds(hcd);
1226
1227         irqret = IRQ_HANDLED;
1228 leave:
1229         spin_unlock(&priv->lock);
1230
1231         return irqret;
1232 }
1233
1234 /*
1235  * Workaround for problem described in chip errata 2:
1236  *
1237  * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1238  * One solution suggested in the errata is to use SOF interrupts _instead_of_
1239  * ATL done interrupts (the "instead of" might be important since it seems
1240  * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1241  * to set the PTD's done bit in addition to not generating an interrupt!).
1242  *
1243  * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1244  * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1245  *
1246  * If we use SOF interrupts only, we get latency between ptd completion and the
1247  * actual handling. This is very noticeable in testusb runs which takes several
1248  * minutes longer without ATL interrupts.
1249  *
1250  * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1251  * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1252  * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1253  * completed and its done map bit is set.
1254  *
1255  * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1256  * not to cause too much lag when this HW bug occurs, while still hopefully
1257  * ensuring that the check does not falsely trigger.
1258  */
1259 #define SLOT_TIMEOUT 300
1260 #define SLOT_CHECK_PERIOD 200
1261 static struct timer_list errata2_timer;
1262 static struct usb_hcd *errata2_timer_hcd;
1263
1264 static void errata2_function(struct timer_list *unused)
1265 {
1266         struct usb_hcd *hcd = errata2_timer_hcd;
1267         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1268         int slot;
1269         struct ptd ptd;
1270         unsigned long spinflags;
1271
1272         spin_lock_irqsave(&priv->lock, spinflags);
1273
1274         for (slot = 0; slot < 32; slot++)
1275                 if (priv->atl_slots[slot].qh && time_after(jiffies,
1276                                         priv->atl_slots[slot].timestamp +
1277                                         msecs_to_jiffies(SLOT_TIMEOUT))) {
1278                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1279                         if (!FROM_DW0_VALID(ptd.dw0) &&
1280                                         !FROM_DW3_ACTIVE(ptd.dw3))
1281                                 priv->atl_done_map |= 1 << slot;
1282                 }
1283
1284         if (priv->atl_done_map)
1285                 handle_done_ptds(hcd);
1286
1287         spin_unlock_irqrestore(&priv->lock, spinflags);
1288
1289         errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1290         add_timer(&errata2_timer);
1291 }
1292
1293 static int isp1760_run(struct usb_hcd *hcd)
1294 {
1295         int retval;
1296         u32 temp;
1297         u32 command;
1298         u32 chipid;
1299
1300         hcd->uses_new_polling = 1;
1301
1302         hcd->state = HC_STATE_RUNNING;
1303
1304         /* Set PTD interrupt AND & OR maps */
1305         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1306         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1307         reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1308         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1309         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1310         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1311         /* step 23 passed */
1312
1313         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1314         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1315
1316         command = reg_read32(hcd->regs, HC_USBCMD);
1317         command &= ~(CMD_LRESET|CMD_RESET);
1318         command |= CMD_RUN;
1319         reg_write32(hcd->regs, HC_USBCMD, command);
1320
1321         retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1322         if (retval)
1323                 return retval;
1324
1325         /*
1326          * XXX
1327          * Spec says to write FLAG_CF as last config action, priv code grabs
1328          * the semaphore while doing so.
1329          */
1330         down_write(&ehci_cf_port_reset_rwsem);
1331         reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1332
1333         retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1334         up_write(&ehci_cf_port_reset_rwsem);
1335         if (retval)
1336                 return retval;
1337
1338         errata2_timer_hcd = hcd;
1339         timer_setup(&errata2_timer, errata2_function, 0);
1340         errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD);
1341         add_timer(&errata2_timer);
1342
1343         chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1344         dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1345                                         chipid & 0xffff, chipid >> 16);
1346
1347         /* PTD Register Init Part 2, Step 28 */
1348
1349         /* Setup registers controlling PTD checking */
1350         reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1351         reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1352         reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1353         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1354         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1355         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1356         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1357                                                 ATL_BUF_FILL | INT_BUF_FILL);
1358
1359         /* GRR this is run-once init(), being done every time the HC starts.
1360          * So long as they're part of class devices, we can't do it init()
1361          * since the class device isn't created that early.
1362          */
1363         return 0;
1364 }
1365
1366 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1367 {
1368         qtd->data_buffer = databuffer;
1369
1370         if (len > MAX_PAYLOAD_SIZE)
1371                 len = MAX_PAYLOAD_SIZE;
1372         qtd->length = len;
1373
1374         return qtd->length;
1375 }
1376
1377 static void qtd_list_free(struct list_head *qtd_list)
1378 {
1379         struct isp1760_qtd *qtd, *qtd_next;
1380
1381         list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1382                 list_del(&qtd->qtd_list);
1383                 qtd_free(qtd);
1384         }
1385 }
1386
1387 /*
1388  * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1389  * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1390  */
1391 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1392 static void packetize_urb(struct usb_hcd *hcd,
1393                 struct urb *urb, struct list_head *head, gfp_t flags)
1394 {
1395         struct isp1760_qtd *qtd;
1396         void *buf;
1397         int len, maxpacketsize;
1398         u8 packet_type;
1399
1400         /*
1401          * URBs map to sequences of QTDs:  one logical transaction
1402          */
1403
1404         if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1405                 /* XXX This looks like usb storage / SCSI bug */
1406                 dev_err(hcd->self.controller,
1407                                 "buf is null, dma is %08lx len is %d\n",
1408                                 (long unsigned)urb->transfer_dma,
1409                                 urb->transfer_buffer_length);
1410                 WARN_ON(1);
1411         }
1412
1413         if (usb_pipein(urb->pipe))
1414                 packet_type = IN_PID;
1415         else
1416                 packet_type = OUT_PID;
1417
1418         if (usb_pipecontrol(urb->pipe)) {
1419                 qtd = qtd_alloc(flags, urb, SETUP_PID);
1420                 if (!qtd)
1421                         goto cleanup;
1422                 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1423                 list_add_tail(&qtd->qtd_list, head);
1424
1425                 /* for zero length DATA stages, STATUS is always IN */
1426                 if (urb->transfer_buffer_length == 0)
1427                         packet_type = IN_PID;
1428         }
1429
1430         maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1431                                                 usb_pipeout(urb->pipe)));
1432
1433         /*
1434          * buffer gets wrapped in one or more qtds;
1435          * last one may be "short" (including zero len)
1436          * and may serve as a control status ack
1437          */
1438         buf = urb->transfer_buffer;
1439         len = urb->transfer_buffer_length;
1440
1441         for (;;) {
1442                 int this_qtd_len;
1443
1444                 qtd = qtd_alloc(flags, urb, packet_type);
1445                 if (!qtd)
1446                         goto cleanup;
1447                 this_qtd_len = qtd_fill(qtd, buf, len);
1448                 list_add_tail(&qtd->qtd_list, head);
1449
1450                 len -= this_qtd_len;
1451                 buf += this_qtd_len;
1452
1453                 if (len <= 0)
1454                         break;
1455         }
1456
1457         /*
1458          * control requests may need a terminating data "status" ack;
1459          * bulk ones may need a terminating short packet (zero length).
1460          */
1461         if (urb->transfer_buffer_length != 0) {
1462                 int one_more = 0;
1463
1464                 if (usb_pipecontrol(urb->pipe)) {
1465                         one_more = 1;
1466                         if (packet_type == IN_PID)
1467                                 packet_type = OUT_PID;
1468                         else
1469                                 packet_type = IN_PID;
1470                 } else if (usb_pipebulk(urb->pipe)
1471                                 && (urb->transfer_flags & URB_ZERO_PACKET)
1472                                 && !(urb->transfer_buffer_length %
1473                                                         maxpacketsize)) {
1474                         one_more = 1;
1475                 }
1476                 if (one_more) {
1477                         qtd = qtd_alloc(flags, urb, packet_type);
1478                         if (!qtd)
1479                                 goto cleanup;
1480
1481                         /* never any data in such packets */
1482                         qtd_fill(qtd, NULL, 0);
1483                         list_add_tail(&qtd->qtd_list, head);
1484                 }
1485         }
1486
1487         return;
1488
1489 cleanup:
1490         qtd_list_free(head);
1491 }
1492
1493 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1494                 gfp_t mem_flags)
1495 {
1496         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1497         struct list_head *ep_queue;
1498         struct isp1760_qh *qh, *qhit;
1499         unsigned long spinflags;
1500         LIST_HEAD(new_qtds);
1501         int retval;
1502         int qh_in_queue;
1503
1504         switch (usb_pipetype(urb->pipe)) {
1505         case PIPE_CONTROL:
1506                 ep_queue = &priv->qh_list[QH_CONTROL];
1507                 break;
1508         case PIPE_BULK:
1509                 ep_queue = &priv->qh_list[QH_BULK];
1510                 break;
1511         case PIPE_INTERRUPT:
1512                 if (urb->interval < 0)
1513                         return -EINVAL;
1514                 /* FIXME: Check bandwidth  */
1515                 ep_queue = &priv->qh_list[QH_INTERRUPT];
1516                 break;
1517         case PIPE_ISOCHRONOUS:
1518                 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1519                                                         "not yet supported\n",
1520                                                         __func__);
1521                 return -EPIPE;
1522         default:
1523                 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1524                                                         __func__);
1525                 return -EPIPE;
1526         }
1527
1528         if (usb_pipein(urb->pipe))
1529                 urb->actual_length = 0;
1530
1531         packetize_urb(hcd, urb, &new_qtds, mem_flags);
1532         if (list_empty(&new_qtds))
1533                 return -ENOMEM;
1534
1535         retval = 0;
1536         spin_lock_irqsave(&priv->lock, spinflags);
1537
1538         if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1539                 retval = -ESHUTDOWN;
1540                 qtd_list_free(&new_qtds);
1541                 goto out;
1542         }
1543         retval = usb_hcd_link_urb_to_ep(hcd, urb);
1544         if (retval) {
1545                 qtd_list_free(&new_qtds);
1546                 goto out;
1547         }
1548
1549         qh = urb->ep->hcpriv;
1550         if (qh) {
1551                 qh_in_queue = 0;
1552                 list_for_each_entry(qhit, ep_queue, qh_list) {
1553                         if (qhit == qh) {
1554                                 qh_in_queue = 1;
1555                                 break;
1556                         }
1557                 }
1558                 if (!qh_in_queue)
1559                         list_add_tail(&qh->qh_list, ep_queue);
1560         } else {
1561                 qh = qh_alloc(GFP_ATOMIC);
1562                 if (!qh) {
1563                         retval = -ENOMEM;
1564                         usb_hcd_unlink_urb_from_ep(hcd, urb);
1565                         qtd_list_free(&new_qtds);
1566                         goto out;
1567                 }
1568                 list_add_tail(&qh->qh_list, ep_queue);
1569                 urb->ep->hcpriv = qh;
1570         }
1571
1572         list_splice_tail(&new_qtds, &qh->qtd_list);
1573         schedule_ptds(hcd);
1574
1575 out:
1576         spin_unlock_irqrestore(&priv->lock, spinflags);
1577         return retval;
1578 }
1579
1580 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1581                 struct isp1760_qh *qh)
1582 {
1583         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1584         int skip_map;
1585
1586         WARN_ON(qh->slot == -1);
1587
1588         /* We need to forcefully reclaim the slot since some transfers never
1589            return, e.g. interrupt transfers and NAKed bulk transfers. */
1590         if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1591                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1592                 skip_map |= (1 << qh->slot);
1593                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1594                 priv->atl_slots[qh->slot].qh = NULL;
1595                 priv->atl_slots[qh->slot].qtd = NULL;
1596         } else {
1597                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1598                 skip_map |= (1 << qh->slot);
1599                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1600                 priv->int_slots[qh->slot].qh = NULL;
1601                 priv->int_slots[qh->slot].qtd = NULL;
1602         }
1603
1604         qh->slot = -1;
1605 }
1606
1607 /*
1608  * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1609  * any active transfer belonging to the urb in the process.
1610  */
1611 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1612                                                 struct isp1760_qtd *qtd)
1613 {
1614         struct urb *urb;
1615         int urb_was_running;
1616
1617         urb = qtd->urb;
1618         urb_was_running = 0;
1619         list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1620                 if (qtd->urb != urb)
1621                         break;
1622
1623                 if (qtd->status >= QTD_XFER_STARTED)
1624                         urb_was_running = 1;
1625                 if (last_qtd_of_urb(qtd, qh) &&
1626                                         (qtd->status >= QTD_XFER_COMPLETE))
1627                         urb_was_running = 0;
1628
1629                 if (qtd->status == QTD_XFER_STARTED)
1630                         kill_transfer(hcd, urb, qh);
1631                 qtd->status = QTD_RETIRE;
1632         }
1633
1634         if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1635                 qh->tt_buffer_dirty = 1;
1636                 if (usb_hub_clear_tt_buffer(urb))
1637                         /* Clear failed; let's hope things work anyway */
1638                         qh->tt_buffer_dirty = 0;
1639         }
1640 }
1641
1642 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1643                 int status)
1644 {
1645         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1646         unsigned long spinflags;
1647         struct isp1760_qh *qh;
1648         struct isp1760_qtd *qtd;
1649         int retval = 0;
1650
1651         spin_lock_irqsave(&priv->lock, spinflags);
1652         retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1653         if (retval)
1654                 goto out;
1655
1656         qh = urb->ep->hcpriv;
1657         if (!qh) {
1658                 retval = -EINVAL;
1659                 goto out;
1660         }
1661
1662         list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1663                 if (qtd->urb == urb) {
1664                         dequeue_urb_from_qtd(hcd, qh, qtd);
1665                         list_move(&qtd->qtd_list, &qh->qtd_list);
1666                         break;
1667                 }
1668
1669         urb->status = status;
1670         schedule_ptds(hcd);
1671
1672 out:
1673         spin_unlock_irqrestore(&priv->lock, spinflags);
1674         return retval;
1675 }
1676
1677 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1678                 struct usb_host_endpoint *ep)
1679 {
1680         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1681         unsigned long spinflags;
1682         struct isp1760_qh *qh, *qh_iter;
1683         int i;
1684
1685         spin_lock_irqsave(&priv->lock, spinflags);
1686
1687         qh = ep->hcpriv;
1688         if (!qh)
1689                 goto out;
1690
1691         WARN_ON(!list_empty(&qh->qtd_list));
1692
1693         for (i = 0; i < QH_END; i++)
1694                 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
1695                         if (qh_iter == qh) {
1696                                 list_del(&qh_iter->qh_list);
1697                                 i = QH_END;
1698                                 break;
1699                         }
1700         qh_free(qh);
1701         ep->hcpriv = NULL;
1702
1703         schedule_ptds(hcd);
1704
1705 out:
1706         spin_unlock_irqrestore(&priv->lock, spinflags);
1707 }
1708
1709 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1710 {
1711         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1712         u32 temp, status = 0;
1713         u32 mask;
1714         int retval = 1;
1715         unsigned long flags;
1716
1717         /* if !PM, root hub timers won't get shut down ... */
1718         if (!HC_IS_RUNNING(hcd->state))
1719                 return 0;
1720
1721         /* init status to no-changes */
1722         buf[0] = 0;
1723         mask = PORT_CSC;
1724
1725         spin_lock_irqsave(&priv->lock, flags);
1726         temp = reg_read32(hcd->regs, HC_PORTSC1);
1727
1728         if (temp & PORT_OWNER) {
1729                 if (temp & PORT_CSC) {
1730                         temp &= ~PORT_CSC;
1731                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1732                         goto done;
1733                 }
1734         }
1735
1736         /*
1737          * Return status information even for ports with OWNER set.
1738          * Otherwise hub_wq wouldn't see the disconnect event when a
1739          * high-speed device is switched over to the companion
1740          * controller by the user.
1741          */
1742
1743         if ((temp & mask) != 0
1744                         || ((temp & PORT_RESUME) != 0
1745                                 && time_after_eq(jiffies,
1746                                         priv->reset_done))) {
1747                 buf [0] |= 1 << (0 + 1);
1748                 status = STS_PCD;
1749         }
1750         /* FIXME autosuspend idle root hubs */
1751 done:
1752         spin_unlock_irqrestore(&priv->lock, flags);
1753         return status ? retval : 0;
1754 }
1755
1756 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1757                 struct usb_hub_descriptor *desc)
1758 {
1759         int ports = HCS_N_PORTS(priv->hcs_params);
1760         u16 temp;
1761
1762         desc->bDescriptorType = USB_DT_HUB;
1763         /* priv 1.0, 2.3.9 says 20ms max */
1764         desc->bPwrOn2PwrGood = 10;
1765         desc->bHubContrCurrent = 0;
1766
1767         desc->bNbrPorts = ports;
1768         temp = 1 + (ports / 8);
1769         desc->bDescLength = 7 + 2 * temp;
1770
1771         /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1772         memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1773         memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1774
1775         /* per-port overcurrent reporting */
1776         temp = HUB_CHAR_INDV_PORT_OCPM;
1777         if (HCS_PPC(priv->hcs_params))
1778                 /* per-port power control */
1779                 temp |= HUB_CHAR_INDV_PORT_LPSM;
1780         else
1781                 /* no power switching */
1782                 temp |= HUB_CHAR_NO_LPSM;
1783         desc->wHubCharacteristics = cpu_to_le16(temp);
1784 }
1785
1786 #define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1787
1788 static int check_reset_complete(struct usb_hcd *hcd, int index,
1789                 int port_status)
1790 {
1791         if (!(port_status & PORT_CONNECT))
1792                 return port_status;
1793
1794         /* if reset finished and it's still not enabled -- handoff */
1795         if (!(port_status & PORT_PE)) {
1796
1797                 dev_info(hcd->self.controller,
1798                                         "port %d full speed --> companion\n",
1799                                         index + 1);
1800
1801                 port_status |= PORT_OWNER;
1802                 port_status &= ~PORT_RWC_BITS;
1803                 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1804
1805         } else
1806                 dev_info(hcd->self.controller, "port %d high speed\n",
1807                                                                 index + 1);
1808
1809         return port_status;
1810 }
1811
1812 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1813                 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1814 {
1815         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1816         int ports = HCS_N_PORTS(priv->hcs_params);
1817         u32 temp, status;
1818         unsigned long flags;
1819         int retval = 0;
1820
1821         /*
1822          * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1823          * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1824          * (track current state ourselves) ... blink for diagnostics,
1825          * power, "this is the one", etc.  EHCI spec supports this.
1826          */
1827
1828         spin_lock_irqsave(&priv->lock, flags);
1829         switch (typeReq) {
1830         case ClearHubFeature:
1831                 switch (wValue) {
1832                 case C_HUB_LOCAL_POWER:
1833                 case C_HUB_OVER_CURRENT:
1834                         /* no hub-wide feature/status flags */
1835                         break;
1836                 default:
1837                         goto error;
1838                 }
1839                 break;
1840         case ClearPortFeature:
1841                 if (!wIndex || wIndex > ports)
1842                         goto error;
1843                 wIndex--;
1844                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1845
1846                 /*
1847                  * Even if OWNER is set, so the port is owned by the
1848                  * companion controller, hub_wq needs to be able to clear
1849                  * the port-change status bits (especially
1850                  * USB_PORT_STAT_C_CONNECTION).
1851                  */
1852
1853                 switch (wValue) {
1854                 case USB_PORT_FEAT_ENABLE:
1855                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1856                         break;
1857                 case USB_PORT_FEAT_C_ENABLE:
1858                         /* XXX error? */
1859                         break;
1860                 case USB_PORT_FEAT_SUSPEND:
1861                         if (temp & PORT_RESET)
1862                                 goto error;
1863
1864                         if (temp & PORT_SUSPEND) {
1865                                 if ((temp & PORT_PE) == 0)
1866                                         goto error;
1867                                 /* resume signaling for 20 msec */
1868                                 temp &= ~(PORT_RWC_BITS);
1869                                 reg_write32(hcd->regs, HC_PORTSC1,
1870                                                         temp | PORT_RESUME);
1871                                 priv->reset_done = jiffies +
1872                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
1873                         }
1874                         break;
1875                 case USB_PORT_FEAT_C_SUSPEND:
1876                         /* we auto-clear this feature */
1877                         break;
1878                 case USB_PORT_FEAT_POWER:
1879                         if (HCS_PPC(priv->hcs_params))
1880                                 reg_write32(hcd->regs, HC_PORTSC1,
1881                                                         temp & ~PORT_POWER);
1882                         break;
1883                 case USB_PORT_FEAT_C_CONNECTION:
1884                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1885                         break;
1886                 case USB_PORT_FEAT_C_OVER_CURRENT:
1887                         /* XXX error ?*/
1888                         break;
1889                 case USB_PORT_FEAT_C_RESET:
1890                         /* GetPortStatus clears reset */
1891                         break;
1892                 default:
1893                         goto error;
1894                 }
1895                 reg_read32(hcd->regs, HC_USBCMD);
1896                 break;
1897         case GetHubDescriptor:
1898                 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1899                         buf);
1900                 break;
1901         case GetHubStatus:
1902                 /* no hub-wide feature/status flags */
1903                 memset(buf, 0, 4);
1904                 break;
1905         case GetPortStatus:
1906                 if (!wIndex || wIndex > ports)
1907                         goto error;
1908                 wIndex--;
1909                 status = 0;
1910                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1911
1912                 /* wPortChange bits */
1913                 if (temp & PORT_CSC)
1914                         status |= USB_PORT_STAT_C_CONNECTION << 16;
1915
1916
1917                 /* whoever resumes must GetPortStatus to complete it!! */
1918                 if (temp & PORT_RESUME) {
1919                         dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1920
1921                         /* Remote Wakeup received? */
1922                         if (!priv->reset_done) {
1923                                 /* resume signaling for 20 msec */
1924                                 priv->reset_done = jiffies
1925                                                 + msecs_to_jiffies(20);
1926                                 /* check the port again */
1927                                 mod_timer(&hcd->rh_timer, priv->reset_done);
1928                         }
1929
1930                         /* resume completed? */
1931                         else if (time_after_eq(jiffies,
1932                                         priv->reset_done)) {
1933                                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1934                                 priv->reset_done = 0;
1935
1936                                 /* stop resume signaling */
1937                                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1938                                 reg_write32(hcd->regs, HC_PORTSC1,
1939                                         temp & ~(PORT_RWC_BITS | PORT_RESUME));
1940                                 retval = handshake(hcd, HC_PORTSC1,
1941                                            PORT_RESUME, 0, 2000 /* 2msec */);
1942                                 if (retval != 0) {
1943                                         dev_err(hcd->self.controller,
1944                                                 "port %d resume error %d\n",
1945                                                 wIndex + 1, retval);
1946                                         goto error;
1947                                 }
1948                                 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1949                         }
1950                 }
1951
1952                 /* whoever resets must GetPortStatus to complete it!! */
1953                 if ((temp & PORT_RESET)
1954                                 && time_after_eq(jiffies,
1955                                         priv->reset_done)) {
1956                         status |= USB_PORT_STAT_C_RESET << 16;
1957                         priv->reset_done = 0;
1958
1959                         /* force reset to complete */
1960                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1961                         /* REVISIT:  some hardware needs 550+ usec to clear
1962                          * this bit; seems too long to spin routinely...
1963                          */
1964                         retval = handshake(hcd, HC_PORTSC1,
1965                                         PORT_RESET, 0, 750);
1966                         if (retval != 0) {
1967                                 dev_err(hcd->self.controller, "port %d reset error %d\n",
1968                                                 wIndex + 1, retval);
1969                                 goto error;
1970                         }
1971
1972                         /* see what we found out */
1973                         temp = check_reset_complete(hcd, wIndex,
1974                                         reg_read32(hcd->regs, HC_PORTSC1));
1975                 }
1976                 /*
1977                  * Even if OWNER is set, there's no harm letting hub_wq
1978                  * see the wPortStatus values (they should all be 0 except
1979                  * for PORT_POWER anyway).
1980                  */
1981
1982                 if (temp & PORT_OWNER)
1983                         dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1984
1985                 if (temp & PORT_CONNECT) {
1986                         status |= USB_PORT_STAT_CONNECTION;
1987                         /* status may be from integrated TT */
1988                         status |= USB_PORT_STAT_HIGH_SPEED;
1989                 }
1990                 if (temp & PORT_PE)
1991                         status |= USB_PORT_STAT_ENABLE;
1992                 if (temp & (PORT_SUSPEND|PORT_RESUME))
1993                         status |= USB_PORT_STAT_SUSPEND;
1994                 if (temp & PORT_RESET)
1995                         status |= USB_PORT_STAT_RESET;
1996                 if (temp & PORT_POWER)
1997                         status |= USB_PORT_STAT_POWER;
1998
1999                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2000                 break;
2001         case SetHubFeature:
2002                 switch (wValue) {
2003                 case C_HUB_LOCAL_POWER:
2004                 case C_HUB_OVER_CURRENT:
2005                         /* no hub-wide feature/status flags */
2006                         break;
2007                 default:
2008                         goto error;
2009                 }
2010                 break;
2011         case SetPortFeature:
2012                 wIndex &= 0xff;
2013                 if (!wIndex || wIndex > ports)
2014                         goto error;
2015                 wIndex--;
2016                 temp = reg_read32(hcd->regs, HC_PORTSC1);
2017                 if (temp & PORT_OWNER)
2018                         break;
2019
2020 /*              temp &= ~PORT_RWC_BITS; */
2021                 switch (wValue) {
2022                 case USB_PORT_FEAT_ENABLE:
2023                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2024                         break;
2025
2026                 case USB_PORT_FEAT_SUSPEND:
2027                         if ((temp & PORT_PE) == 0
2028                                         || (temp & PORT_RESET) != 0)
2029                                 goto error;
2030
2031                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2032                         break;
2033                 case USB_PORT_FEAT_POWER:
2034                         if (HCS_PPC(priv->hcs_params))
2035                                 reg_write32(hcd->regs, HC_PORTSC1,
2036                                                         temp | PORT_POWER);
2037                         break;
2038                 case USB_PORT_FEAT_RESET:
2039                         if (temp & PORT_RESUME)
2040                                 goto error;
2041                         /* line status bits may report this as low speed,
2042                          * which can be fine if this root hub has a
2043                          * transaction translator built in.
2044                          */
2045                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2046                                         && PORT_USB11(temp)) {
2047                                 temp |= PORT_OWNER;
2048                         } else {
2049                                 temp |= PORT_RESET;
2050                                 temp &= ~PORT_PE;
2051
2052                                 /*
2053                                  * caller must wait, then call GetPortStatus
2054                                  * usb 2.0 spec says 50 ms resets on root
2055                                  */
2056                                 priv->reset_done = jiffies +
2057                                         msecs_to_jiffies(50);
2058                         }
2059                         reg_write32(hcd->regs, HC_PORTSC1, temp);
2060                         break;
2061                 default:
2062                         goto error;
2063                 }
2064                 reg_read32(hcd->regs, HC_USBCMD);
2065                 break;
2066
2067         default:
2068 error:
2069                 /* "stall" on error */
2070                 retval = -EPIPE;
2071         }
2072         spin_unlock_irqrestore(&priv->lock, flags);
2073         return retval;
2074 }
2075
2076 static int isp1760_get_frame(struct usb_hcd *hcd)
2077 {
2078         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2079         u32 fr;
2080
2081         fr = reg_read32(hcd->regs, HC_FRINDEX);
2082         return (fr >> 3) % priv->periodic_size;
2083 }
2084
2085 static void isp1760_stop(struct usb_hcd *hcd)
2086 {
2087         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2088         u32 temp;
2089
2090         del_timer(&errata2_timer);
2091
2092         isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2093                         NULL, 0);
2094         msleep(20);
2095
2096         spin_lock_irq(&priv->lock);
2097         ehci_reset(hcd);
2098         /* Disable IRQ */
2099         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2100         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2101         spin_unlock_irq(&priv->lock);
2102
2103         reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2104 }
2105
2106 static void isp1760_shutdown(struct usb_hcd *hcd)
2107 {
2108         u32 command, temp;
2109
2110         isp1760_stop(hcd);
2111         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2112         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2113
2114         command = reg_read32(hcd->regs, HC_USBCMD);
2115         command &= ~CMD_RUN;
2116         reg_write32(hcd->regs, HC_USBCMD, command);
2117 }
2118
2119 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2120                                                 struct usb_host_endpoint *ep)
2121 {
2122         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2123         struct isp1760_qh *qh = ep->hcpriv;
2124         unsigned long spinflags;
2125
2126         if (!qh)
2127                 return;
2128
2129         spin_lock_irqsave(&priv->lock, spinflags);
2130         qh->tt_buffer_dirty = 0;
2131         schedule_ptds(hcd);
2132         spin_unlock_irqrestore(&priv->lock, spinflags);
2133 }
2134
2135
2136 static const struct hc_driver isp1760_hc_driver = {
2137         .description            = "isp1760-hcd",
2138         .product_desc           = "NXP ISP1760 USB Host Controller",
2139         .hcd_priv_size          = sizeof(struct isp1760_hcd *),
2140         .irq                    = isp1760_irq,
2141         .flags                  = HCD_MEMORY | HCD_USB2,
2142         .reset                  = isp1760_hc_setup,
2143         .start                  = isp1760_run,
2144         .stop                   = isp1760_stop,
2145         .shutdown               = isp1760_shutdown,
2146         .urb_enqueue            = isp1760_urb_enqueue,
2147         .urb_dequeue            = isp1760_urb_dequeue,
2148         .endpoint_disable       = isp1760_endpoint_disable,
2149         .get_frame_number       = isp1760_get_frame,
2150         .hub_status_data        = isp1760_hub_status_data,
2151         .hub_control            = isp1760_hub_control,
2152         .clear_tt_buffer_complete       = isp1760_clear_tt_buffer_complete,
2153 };
2154
2155 int __init isp1760_init_kmem_once(void)
2156 {
2157         urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2158                         sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2159                         SLAB_MEM_SPREAD, NULL);
2160
2161         if (!urb_listitem_cachep)
2162                 return -ENOMEM;
2163
2164         qtd_cachep = kmem_cache_create("isp1760_qtd",
2165                         sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2166                         SLAB_MEM_SPREAD, NULL);
2167
2168         if (!qtd_cachep)
2169                 return -ENOMEM;
2170
2171         qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2172                         0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2173
2174         if (!qh_cachep) {
2175                 kmem_cache_destroy(qtd_cachep);
2176                 return -ENOMEM;
2177         }
2178
2179         return 0;
2180 }
2181
2182 void isp1760_deinit_kmem_cache(void)
2183 {
2184         kmem_cache_destroy(qtd_cachep);
2185         kmem_cache_destroy(qh_cachep);
2186         kmem_cache_destroy(urb_listitem_cachep);
2187 }
2188
2189 int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs,
2190                          struct resource *mem, int irq, unsigned long irqflags,
2191                          struct device *dev)
2192 {
2193         struct usb_hcd *hcd;
2194         int ret;
2195
2196         hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2197         if (!hcd)
2198                 return -ENOMEM;
2199
2200         *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2201
2202         priv->hcd = hcd;
2203
2204         init_memory(priv);
2205
2206         hcd->irq = irq;
2207         hcd->regs = regs;
2208         hcd->rsrc_start = mem->start;
2209         hcd->rsrc_len = resource_size(mem);
2210
2211         /* This driver doesn't support wakeup requests */
2212         hcd->cant_recv_wakeups = 1;
2213
2214         ret = usb_add_hcd(hcd, irq, irqflags);
2215         if (ret)
2216                 goto error;
2217
2218         device_wakeup_enable(hcd->self.controller);
2219
2220         return 0;
2221
2222 error:
2223         usb_put_hcd(hcd);
2224         return ret;
2225 }
2226
2227 void isp1760_hcd_unregister(struct isp1760_hcd *priv)
2228 {
2229         if (!priv->hcd)
2230                 return;
2231
2232         usb_remove_hcd(priv->hcd);
2233         usb_put_hcd(priv->hcd);
2234 }