arch/arm/mm/nommu.c

   1 /*
   2  *  linux/arch/arm/mm/nommu.c
   3  *
   4  * ARM uCLinux supporting functions.
   5  */
   6 #include <linux/module.h>
   7 #include <linux/mm.h>
   8 #include <linux/pagemap.h>
   9 #include <linux/io.h>
  10 #include <linux/memblock.h>
  11 #include <linux/kernel.h>
  12
  13 #include <asm/cacheflush.h>
  14 #include <asm/sections.h>
  15 #include <asm/page.h>
  16 #include <asm/setup.h>
  17 #include <asm/traps.h>
  18 #include <asm/mach/arch.h>
  19 #include <asm/cputype.h>
  20 #include <asm/mpu.h>
  21 #include <asm/procinfo.h>
  22
  23 #include "mm.h"
  24
  25 #ifdef CONFIG_ARM_MPU
  26 struct mpu_rgn_info mpu_rgn_info;
  27
  28 /* Region number */
  29 static void rgnr_write(u32 v)
  30 {
  31         asm("mcr        p15, 0, %0, c6, c2, 0" : : "r" (v));
  32 }
  33
  34 /* Data-side / unified region attributes */
  35
  36 /* Region access control register */
  37 static void dracr_write(u32 v)
  38 {
  39         asm("mcr        p15, 0, %0, c6, c1, 4" : : "r" (v));
  40 }
  41
  42 /* Region size register */
  43 static void drsr_write(u32 v)
  44 {
  45         asm("mcr        p15, 0, %0, c6, c1, 2" : : "r" (v));
  46 }
  47
  48 /* Region base address register */
  49 static void drbar_write(u32 v)
  50 {
  51         asm("mcr        p15, 0, %0, c6, c1, 0" : : "r" (v));
  52 }
  53
  54 static u32 drbar_read(void)
  55 {
  56         u32 v;
  57         asm("mrc        p15, 0, %0, c6, c1, 0" : "=r" (v));
  58         return v;
  59 }
  60 /* Optional instruction-side region attributes */
  61
  62 /* I-side Region access control register */
  63 static void iracr_write(u32 v)
  64 {
  65         asm("mcr        p15, 0, %0, c6, c1, 5" : : "r" (v));
  66 }
  67
  68 /* I-side Region size register */
  69 static void irsr_write(u32 v)
  70 {
  71         asm("mcr        p15, 0, %0, c6, c1, 3" : : "r" (v));
  72 }
  73
  74 /* I-side Region base address register */
  75 static void irbar_write(u32 v)
  76 {
  77         asm("mcr        p15, 0, %0, c6, c1, 1" : : "r" (v));
  78 }
  79
  80 static unsigned long irbar_read(void)
  81 {
  82         unsigned long v;
  83         asm("mrc        p15, 0, %0, c6, c1, 1" : "=r" (v));
  84         return v;
  85 }
  86
  87 /* MPU initialisation functions */
  88 void __init sanity_check_meminfo_mpu(void)
  89 {
  90         int i;
  91         phys_addr_t phys_offset = PHYS_OFFSET;
  92         phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
  93         struct memblock_region *reg;
  94         bool first = true;
  95         phys_addr_t mem_start;
  96         phys_addr_t mem_end;
  97
  98         for_each_memblock(memory, reg) {
  99                 if (first) {
 100                         /*
 101                          * Initially only use memory continuous from
 102                          * PHYS_OFFSET */
 103                         if (reg->base != phys_offset)
 104                                 panic("First memory bank must be contiguous from PHYS_OFFSET");
 105
 106                         mem_start = reg->base;
 107                         mem_end = reg->base + reg->size;
 108                         specified_mem_size = reg->size;
 109                         first = false;
 110                 } else {
 111                         /*
 112                          * memblock auto merges contiguous blocks, remove
 113                          * all blocks afterwards
 114                          */
 115                         pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
 116                                   &mem_start, &reg->base);
 117                         memblock_remove(reg->base, reg->size);
 118                 }
 119         }
 120
 121         /*
 122          * MPU has curious alignment requirements: Size must be power of 2, and
 123          * region start must be aligned to the region size
 124          */
 125         if (phys_offset != 0)
 126                 pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
 127
 128         /*
 129          * Maximum aligned region might overflow phys_addr_t if phys_offset is
 130          * 0. Hence we keep everything below 4G until we take the smaller of
 131          * the aligned_region_size and rounded_mem_size, one of which is
 132          * guaranteed to be smaller than the maximum physical address.
 133          */
 134         aligned_region_size = (phys_offset - 1) ^ (phys_offset);
 135         /* Find the max power-of-two sized region that fits inside our bank */
 136         rounded_mem_size = (1 <<  __fls(specified_mem_size)) - 1;
 137
 138         /* The actual region size is the smaller of the two */
 139         aligned_region_size = aligned_region_size < rounded_mem_size
 140                                 ? aligned_region_size + 1
 141                                 : rounded_mem_size + 1;
 142
 143         if (aligned_region_size != specified_mem_size) {
 144                 pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
 145                                 &specified_mem_size, &aligned_region_size);
 146                 memblock_remove(mem_start + aligned_region_size,
 147                                 specified_mem_size - aligned_round_size);
 148
 149                 mem_end = mem_start + aligned_region_size;
 150         }
 151
 152         pr_debug("MPU Region from %pa size %pa (end %pa))\n",
 153                 &phys_offset, &aligned_region_size, &mem_end);
 154
 155 }
 156
 157 static int mpu_present(void)
 158 {
 159         return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
 160 }
 161
 162 static int mpu_max_regions(void)
 163 {
 164         /*
 165          * We don't support a different number of I/D side regions so if we
 166          * have separate instruction and data memory maps then return
 167          * whichever side has a smaller number of supported regions.
 168          */
 169         u32 dregions, iregions, mpuir;
 170         mpuir = read_cpuid(CPUID_MPUIR);
 171
 172         dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
 173
 174         /* Check for separate d-side and i-side memory maps */
 175         if (mpuir & MPUIR_nU)
 176                 iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
 177
 178         /* Use the smallest of the two maxima */
 179         return min(dregions, iregions);
 180 }
 181
 182 static int mpu_iside_independent(void)
 183 {
 184         /* MPUIR.nU specifies whether there is *not* a unified memory map */
 185         return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
 186 }
 187
 188 static int mpu_min_region_order(void)
 189 {
 190         u32 drbar_result, irbar_result;
 191         /* We've kept a region free for this probing */
 192         rgnr_write(MPU_PROBE_REGION);
 193         isb();
 194         /*
 195          * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
 196          * region order
 197         */
 198         drbar_write(0xFFFFFFFC);
 199         drbar_result = irbar_result = drbar_read();
 200         drbar_write(0x0);
 201         /* If the MPU is non-unified, we use the larger of the two minima*/
 202         if (mpu_iside_independent()) {
 203                 irbar_write(0xFFFFFFFC);
 204                 irbar_result = irbar_read();
 205                 irbar_write(0x0);
 206         }
 207         isb(); /* Ensure that MPU region operations have completed */
 208         /* Return whichever result is larger */
 209         return __ffs(max(drbar_result, irbar_result));
 210 }
 211
 212 static int mpu_setup_region(unsigned int number, phys_addr_t start,
 213                         unsigned int size_order, unsigned int properties)
 214 {
 215         u32 size_data;
 216
 217         /* We kept a region free for probing resolution of MPU regions*/
 218         if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
 219                 return -ENOENT;
 220
 221         if (size_order > 32)
 222                 return -ENOMEM;
 223
 224         if (size_order < mpu_min_region_order())
 225                 return -ENOMEM;
 226
 227         /* Writing N to bits 5:1 (RSR_SZ)  specifies region size 2^N+1 */
 228         size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
 229
 230         dsb(); /* Ensure all previous data accesses occur with old mappings */
 231         rgnr_write(number);
 232         isb();
 233         drbar_write(start);
 234         dracr_write(properties);
 235         isb(); /* Propagate properties before enabling region */
 236         drsr_write(size_data);
 237
 238         /* Check for independent I-side registers */
 239         if (mpu_iside_independent()) {
 240                 irbar_write(start);
 241                 iracr_write(properties);
 242                 isb();
 243                 irsr_write(size_data);
 244         }
 245         isb();
 246
 247         /* Store region info (we treat i/d side the same, so only store d) */
 248         mpu_rgn_info.rgns[number].dracr = properties;
 249         mpu_rgn_info.rgns[number].drbar = start;
 250         mpu_rgn_info.rgns[number].drsr = size_data;
 251         return 0;
 252 }
 253
 254 /*
 255 * Set up default MPU regions, doing nothing if there is no MPU
 256 */
 257 void __init mpu_setup(void)
 258 {
 259         int region_err;
 260         if (!mpu_present())
 261                 return;
 262
 263         region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
 264                                         ilog2(meminfo.bank[0].size),
 265                                         MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
 266         if (region_err) {
 267                 panic("MPU region initialization failure! %d", region_err);
 268         } else {
 269                 pr_info("Using ARMv7 PMSA Compliant MPU. "
 270                          "Region independence: %s, Max regions: %d\n",
 271                         mpu_iside_independent() ? "Yes" : "No",
 272                         mpu_max_regions());
 273         }
 274 }
 275 #else
 276 static void sanity_check_meminfo_mpu(void) {}
 277 static void __init mpu_setup(void) {}
 278 #endif /* CONFIG_ARM_MPU */
 279
 280 void __init arm_mm_memblock_reserve(void)
 281 {
 282 #ifndef CONFIG_CPU_V7M
 283         /*
 284          * Register the exception vector page.
 285          * some architectures which the DRAM is the exception vector to trap,
 286          * alloc_page breaks with error, although it is not NULL, but "0."
 287          */
 288         memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
 289 #else /* ifndef CONFIG_CPU_V7M */
 290         /*
 291          * There is no dedicated vector page on V7-M. So nothing needs to be
 292          * reserved here.
 293          */
 294 #endif
 295 }
 296
 297 void __init sanity_check_meminfo(void)
 298 {
 299         phys_addr_t end;
 300         sanity_check_meminfo_mpu();
 301         end = memblock_end_of_DRAM();
 302         high_memory = __va(end - 1) + 1;
 303         memblock_set_current_limit(end);
 304 }
 305
 306 /*
 307  * paging_init() sets up the page tables, initialises the zone memory
 308  * maps, and sets up the zero page, bad page and bad page tables.
 309  */
 310 void __init paging_init(const struct machine_desc *mdesc)
 311 {
 312         early_trap_init((void *)CONFIG_VECTORS_BASE);
 313         mpu_setup();
 314         bootmem_init();
 315 }
 316
 317 /*
 318  * We don't need to do anything here for nommu machines.
 319  */
 320 void setup_mm_for_reboot(void)
 321 {
 322 }
 323
 324 void flush_dcache_page(struct page *page)
 325 {
 326         __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 327 }
 328 EXPORT_SYMBOL(flush_dcache_page);
 329
 330 void flush_kernel_dcache_page(struct page *page)
 331 {
 332         __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 333 }
 334 EXPORT_SYMBOL(flush_kernel_dcache_page);
 335
 336 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 337                        unsigned long uaddr, void *dst, const void *src,
 338                        unsigned long len)
 339 {
 340         memcpy(dst, src, len);
 341         if (vma->vm_flags & VM_EXEC)
 342                 __cpuc_coherent_user_range(uaddr, uaddr + len);
 343 }
 344
 345 void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
 346                                 size_t size, unsigned int mtype)
 347 {
 348         if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
 349                 return NULL;
 350         return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
 351 }
 352 EXPORT_SYMBOL(__arm_ioremap_pfn);
 353
 354 void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 355                                    unsigned int mtype, void *caller)
 356 {
 357         return (void __iomem *)phys_addr;
 358 }
 359
 360 void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
 361
 362 void __iomem *ioremap(resource_size_t res_cookie, size_t size)
 363 {
 364         return __arm_ioremap_caller(res_cookie, size, MT_DEVICE,
 365                                     __builtin_return_address(0));
 366 }
 367 EXPORT_SYMBOL(ioremap);
 368
 369 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
 370 {
 371         return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
 372                                     __builtin_return_address(0));
 373 }
 374 EXPORT_SYMBOL(ioremap_cache);
 375
 376 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
 377 {
 378         return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC,
 379                                     __builtin_return_address(0));
 380 }
 381 EXPORT_SYMBOL(ioremap_wc);
 382
 383 void __iounmap(volatile void __iomem *addr)
 384 {
 385 }
 386 EXPORT_SYMBOL(__iounmap);
 387
 388 void (*arch_iounmap)(volatile void __iomem *);
 389
 390 void iounmap(volatile void __iomem *addr)
 391 {
 392 }
 393 EXPORT_SYMBOL(iounmap);