arch/powerpc/include/asm/mpic.h

   1 #ifndef _ASM_POWERPC_MPIC_H
   2 #define _ASM_POWERPC_MPIC_H
   3 #ifdef __KERNEL__
   4
   5 #include <linux/irq.h>
   6 #include <linux/sysdev.h>
   7 #include <asm/dcr.h>
   8 #include <asm/msi_bitmap.h>
   9
  10 /*
  11  * Global registers
  12  */
  13
  14 #define MPIC_GREG_BASE                  0x01000
  15
  16 #define MPIC_GREG_FEATURE_0             0x00000
  17 #define         MPIC_GREG_FEATURE_LAST_SRC_MASK         0x07ff0000
  18 #define         MPIC_GREG_FEATURE_LAST_SRC_SHIFT        16
  19 #define         MPIC_GREG_FEATURE_LAST_CPU_MASK         0x00001f00
  20 #define         MPIC_GREG_FEATURE_LAST_CPU_SHIFT        8
  21 #define         MPIC_GREG_FEATURE_VERSION_MASK          0xff
  22 #define MPIC_GREG_FEATURE_1             0x00010
  23 #define MPIC_GREG_GLOBAL_CONF_0         0x00020
  24 #define         MPIC_GREG_GCONF_RESET                   0x80000000
  25 /* On the FSL mpic implementations the Mode field is expand to be
  26  * 2 bits wide:
  27  *      0b00 = pass through (interrupts routed to IRQ0)
  28  *      0b01 = Mixed mode
  29  *      0b10 = reserved
  30  *      0b11 = External proxy / coreint
  31  */
  32 #define         MPIC_GREG_GCONF_COREINT                 0x60000000
  33 #define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
  34 #define         MPIC_GREG_GCONF_NO_BIAS                 0x10000000
  35 #define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
  36 #define         MPIC_GREG_GCONF_MCK                     0x08000000
  37 #define MPIC_GREG_GLOBAL_CONF_1         0x00030
  38 #define         MPIC_GREG_GLOBAL_CONF_1_SIE             0x08000000
  39 #define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK  0x70000000
  40 #define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)    \
  41                         (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
  42 #define MPIC_GREG_VENDOR_0              0x00040
  43 #define MPIC_GREG_VENDOR_1              0x00050
  44 #define MPIC_GREG_VENDOR_2              0x00060
  45 #define MPIC_GREG_VENDOR_3              0x00070
  46 #define MPIC_GREG_VENDOR_ID             0x00080
  47 #define         MPIC_GREG_VENDOR_ID_STEPPING_MASK       0x00ff0000
  48 #define         MPIC_GREG_VENDOR_ID_STEPPING_SHIFT      16
  49 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK      0x0000ff00
  50 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT     8
  51 #define         MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK      0x000000ff
  52 #define MPIC_GREG_PROCESSOR_INIT        0x00090
  53 #define MPIC_GREG_IPI_VECTOR_PRI_0      0x000a0
  54 #define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
  55 #define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
  56 #define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
  57 #define MPIC_GREG_IPI_STRIDE            0x10
  58 #define MPIC_GREG_SPURIOUS              0x000e0
  59 #define MPIC_GREG_TIMER_FREQ            0x000f0
  60
  61 /*
  62  *
  63  * Timer registers
  64  */
  65 #define MPIC_TIMER_BASE                 0x01100
  66 #define MPIC_TIMER_STRIDE               0x40
  67
  68 #define MPIC_TIMER_CURRENT_CNT          0x00000
  69 #define MPIC_TIMER_BASE_CNT             0x00010
  70 #define MPIC_TIMER_VECTOR_PRI           0x00020
  71 #define MPIC_TIMER_DESTINATION          0x00030
  72
  73 /*
  74  * Per-Processor registers
  75  */
  76
  77 #define MPIC_CPU_THISBASE               0x00000
  78 #define MPIC_CPU_BASE                   0x20000
  79 #define MPIC_CPU_STRIDE                 0x01000
  80
  81 #define MPIC_CPU_IPI_DISPATCH_0         0x00040
  82 #define MPIC_CPU_IPI_DISPATCH_1         0x00050
  83 #define MPIC_CPU_IPI_DISPATCH_2         0x00060
  84 #define MPIC_CPU_IPI_DISPATCH_3         0x00070
  85 #define MPIC_CPU_IPI_DISPATCH_STRIDE    0x00010
  86 #define MPIC_CPU_CURRENT_TASK_PRI       0x00080
  87 #define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
  88 #define MPIC_CPU_WHOAMI                 0x00090
  89 #define         MPIC_CPU_WHOAMI_MASK                    0x0000001f
  90 #define MPIC_CPU_INTACK                 0x000a0
  91 #define MPIC_CPU_EOI                    0x000b0
  92 #define MPIC_CPU_MCACK                  0x000c0
  93
  94 /*
  95  * Per-source registers
  96  */
  97
  98 #define MPIC_IRQ_BASE                   0x10000
  99 #define MPIC_IRQ_STRIDE                 0x00020
 100 #define MPIC_IRQ_VECTOR_PRI             0x00000
 101 #define         MPIC_VECPRI_MASK                        0x80000000
 102 #define         MPIC_VECPRI_ACTIVITY                    0x40000000      /* Read Only */
 103 #define         MPIC_VECPRI_PRIORITY_MASK               0x000f0000
 104 #define         MPIC_VECPRI_PRIORITY_SHIFT              16
 105 #define         MPIC_VECPRI_VECTOR_MASK                 0x000007ff
 106 #define         MPIC_VECPRI_POLARITY_POSITIVE           0x00800000
 107 #define         MPIC_VECPRI_POLARITY_NEGATIVE           0x00000000
 108 #define         MPIC_VECPRI_POLARITY_MASK               0x00800000
 109 #define         MPIC_VECPRI_SENSE_LEVEL                 0x00400000
 110 #define         MPIC_VECPRI_SENSE_EDGE                  0x00000000
 111 #define         MPIC_VECPRI_SENSE_MASK                  0x00400000
 112 #define MPIC_IRQ_DESTINATION            0x00010
 113
 114 #define MPIC_MAX_IRQ_SOURCES    2048
 115 #define MPIC_MAX_CPUS           32
 116 #define MPIC_MAX_ISU            32
 117
 118 /*
 119  * Tsi108 implementation of MPIC has many differences from the original one
 120  */
 121
 122 /*
 123  * Global registers
 124  */
 125
 126 #define TSI108_GREG_BASE                0x00000
 127 #define TSI108_GREG_FEATURE_0           0x00000
 128 #define TSI108_GREG_GLOBAL_CONF_0       0x00004
 129 #define TSI108_GREG_VENDOR_ID           0x0000c
 130 #define TSI108_GREG_IPI_VECTOR_PRI_0    0x00204         /* Doorbell 0 */
 131 #define TSI108_GREG_IPI_STRIDE          0x0c
 132 #define TSI108_GREG_SPURIOUS            0x00010
 133 #define TSI108_GREG_TIMER_FREQ          0x00014
 134
 135 /*
 136  * Timer registers
 137  */
 138 #define TSI108_TIMER_BASE               0x0030
 139 #define TSI108_TIMER_STRIDE             0x10
 140 #define TSI108_TIMER_CURRENT_CNT        0x00000
 141 #define TSI108_TIMER_BASE_CNT           0x00004
 142 #define TSI108_TIMER_VECTOR_PRI         0x00008
 143 #define TSI108_TIMER_DESTINATION        0x0000c
 144
 145 /*
 146  * Per-Processor registers
 147  */
 148 #define TSI108_CPU_BASE                 0x00300
 149 #define TSI108_CPU_STRIDE               0x00040
 150 #define TSI108_CPU_IPI_DISPATCH_0       0x00200
 151 #define TSI108_CPU_IPI_DISPATCH_STRIDE  0x00000
 152 #define TSI108_CPU_CURRENT_TASK_PRI     0x00000
 153 #define TSI108_CPU_WHOAMI               0xffffffff
 154 #define TSI108_CPU_INTACK               0x00004
 155 #define TSI108_CPU_EOI                  0x00008
 156 #define TSI108_CPU_MCACK                0x00004 /* Doesn't really exist here */
 157
 158 /*
 159  * Per-source registers
 160  */
 161 #define TSI108_IRQ_BASE                 0x00100
 162 #define TSI108_IRQ_STRIDE               0x00008
 163 #define TSI108_IRQ_VECTOR_PRI           0x00000
 164 #define TSI108_VECPRI_VECTOR_MASK       0x000000ff
 165 #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
 166 #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
 167 #define TSI108_VECPRI_SENSE_LEVEL       0x02000000
 168 #define TSI108_VECPRI_SENSE_EDGE        0x00000000
 169 #define TSI108_VECPRI_POLARITY_MASK     0x01000000
 170 #define TSI108_VECPRI_SENSE_MASK        0x02000000
 171 #define TSI108_IRQ_DESTINATION          0x00004
 172
 173 /* weird mpic register indices and mask bits in the HW info array */
 174 enum {
 175         MPIC_IDX_GREG_BASE = 0,
 176         MPIC_IDX_GREG_FEATURE_0,
 177         MPIC_IDX_GREG_GLOBAL_CONF_0,
 178         MPIC_IDX_GREG_VENDOR_ID,
 179         MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
 180         MPIC_IDX_GREG_IPI_STRIDE,
 181         MPIC_IDX_GREG_SPURIOUS,
 182         MPIC_IDX_GREG_TIMER_FREQ,
 183
 184         MPIC_IDX_TIMER_BASE,
 185         MPIC_IDX_TIMER_STRIDE,
 186         MPIC_IDX_TIMER_CURRENT_CNT,
 187         MPIC_IDX_TIMER_BASE_CNT,
 188         MPIC_IDX_TIMER_VECTOR_PRI,
 189         MPIC_IDX_TIMER_DESTINATION,
 190
 191         MPIC_IDX_CPU_BASE,
 192         MPIC_IDX_CPU_STRIDE,
 193         MPIC_IDX_CPU_IPI_DISPATCH_0,
 194         MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
 195         MPIC_IDX_CPU_CURRENT_TASK_PRI,
 196         MPIC_IDX_CPU_WHOAMI,
 197         MPIC_IDX_CPU_INTACK,
 198         MPIC_IDX_CPU_EOI,
 199         MPIC_IDX_CPU_MCACK,
 200
 201         MPIC_IDX_IRQ_BASE,
 202         MPIC_IDX_IRQ_STRIDE,
 203         MPIC_IDX_IRQ_VECTOR_PRI,
 204
 205         MPIC_IDX_VECPRI_VECTOR_MASK,
 206         MPIC_IDX_VECPRI_POLARITY_POSITIVE,
 207         MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
 208         MPIC_IDX_VECPRI_SENSE_LEVEL,
 209         MPIC_IDX_VECPRI_SENSE_EDGE,
 210         MPIC_IDX_VECPRI_POLARITY_MASK,
 211         MPIC_IDX_VECPRI_SENSE_MASK,
 212         MPIC_IDX_IRQ_DESTINATION,
 213         MPIC_IDX_END
 214 };
 215
 216
 217 #ifdef CONFIG_MPIC_U3_HT_IRQS
 218 /* Fixup table entry */
 219 struct mpic_irq_fixup
 220 {
 221         u8 __iomem      *base;
 222         u8 __iomem      *applebase;
 223         u32             data;
 224         unsigned int    index;
 225 };
 226 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 227
 228
 229 enum mpic_reg_type {
 230         mpic_access_mmio_le,
 231         mpic_access_mmio_be,
 232 #ifdef CONFIG_PPC_DCR
 233         mpic_access_dcr
 234 #endif
 235 };
 236
 237 struct mpic_reg_bank {
 238         u32 __iomem     *base;
 239 #ifdef CONFIG_PPC_DCR
 240         dcr_host_t      dhost;
 241 #endif /* CONFIG_PPC_DCR */
 242 };
 243
 244 struct mpic_irq_save {
 245         u32             vecprio,
 246                         dest;
 247 #ifdef CONFIG_MPIC_U3_HT_IRQS
 248         u32             fixup_data;
 249 #endif
 250 };
 251
 252 /* The instance data of a given MPIC */
 253 struct mpic
 254 {
 255         /* The remapper for this MPIC */
 256         struct irq_host         *irqhost;
 257
 258         /* The "linux" controller struct */
 259         struct irq_chip         hc_irq;
 260 #ifdef CONFIG_MPIC_U3_HT_IRQS
 261         struct irq_chip         hc_ht_irq;
 262 #endif
 263 #ifdef CONFIG_SMP
 264         struct irq_chip         hc_ipi;
 265 #endif
 266         const char              *name;
 267         /* Flags */
 268         unsigned int            flags;
 269         /* How many irq sources in a given ISU */
 270         unsigned int            isu_size;
 271         unsigned int            isu_shift;
 272         unsigned int            isu_mask;
 273         unsigned int            irq_count;
 274         /* Number of sources */
 275         unsigned int            num_sources;
 276         /* Number of CPUs */
 277         unsigned int            num_cpus;
 278         /* default senses array */
 279         unsigned char           *senses;
 280         unsigned int            senses_count;
 281
 282         /* vector numbers used for internal sources (ipi/timers) */
 283         unsigned int            ipi_vecs[4];
 284         unsigned int            timer_vecs[4];
 285
 286         /* Spurious vector to program into unused sources */
 287         unsigned int            spurious_vec;
 288
 289 #ifdef CONFIG_MPIC_U3_HT_IRQS
 290         /* The fixup table */
 291         struct mpic_irq_fixup   *fixups;
 292         spinlock_t              fixup_lock;
 293 #endif
 294
 295         /* Register access method */
 296         enum mpic_reg_type      reg_type;
 297
 298         /* The various ioremap'ed bases */
 299         struct mpic_reg_bank    gregs;
 300         struct mpic_reg_bank    tmregs;
 301         struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
 302         struct mpic_reg_bank    isus[MPIC_MAX_ISU];
 303
 304         /* Protected sources */
 305         unsigned long           *protected;
 306
 307 #ifdef CONFIG_MPIC_WEIRD
 308         /* Pointer to HW info array */
 309         u32                     *hw_set;
 310 #endif
 311
 312 #ifdef CONFIG_PCI_MSI
 313         struct msi_bitmap       msi_bitmap;
 314 #endif
 315
 316 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 317         u32                     isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
 318 #endif
 319
 320         /* link */
 321         struct mpic             *next;
 322
 323         struct sys_device       sysdev;
 324
 325 #ifdef CONFIG_PM
 326         struct mpic_irq_save    *save_data;
 327 #endif
 328 };
 329
 330 /*
 331  * MPIC flags (passed to mpic_alloc)
 332  *
 333  * The top 4 bits contain an MPIC bhw id that is used to index the
 334  * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
 335  * Note setting any ID (leaving those bits to 0) means standard MPIC
 336  */
 337
 338 /* This is the primary controller, only that one has IPIs and
 339  * has afinity control. A non-primary MPIC always uses CPU0
 340  * registers only
 341  */
 342 #define MPIC_PRIMARY                    0x00000001
 343
 344 /* Set this for a big-endian MPIC */
 345 #define MPIC_BIG_ENDIAN                 0x00000002
 346 /* Broken U3 MPIC */
 347 #define MPIC_U3_HT_IRQS                 0x00000004
 348 /* Broken IPI registers (autodetected) */
 349 #define MPIC_BROKEN_IPI                 0x00000008
 350 /* MPIC wants a reset */
 351 #define MPIC_WANTS_RESET                0x00000010
 352 /* Spurious vector requires EOI */
 353 #define MPIC_SPV_EOI                    0x00000020
 354 /* No passthrough disable */
 355 #define MPIC_NO_PTHROU_DIS              0x00000040
 356 /* DCR based MPIC */
 357 #define MPIC_USES_DCR                   0x00000080
 358 /* MPIC has 11-bit vector fields (or larger) */
 359 #define MPIC_LARGE_VECTORS              0x00000100
 360 /* Enable delivery of prio 15 interrupts as MCK instead of EE */
 361 #define MPIC_ENABLE_MCK                 0x00000200
 362 /* Disable bias among target selection, spread interrupts evenly */
 363 #define MPIC_NO_BIAS                    0x00000400
 364 /* Ignore NIRQS as reported by FRR */
 365 #define MPIC_BROKEN_FRR_NIRQS           0x00000800
 366 /* Destination only supports a single CPU at a time */
 367 #define MPIC_SINGLE_DEST_CPU            0x00001000
 368 /* Enable CoreInt delivery of interrupts */
 369 #define MPIC_ENABLE_COREINT             0x00002000
 370
 371 /* MPIC HW modification ID */
 372 #define MPIC_REGSET_MASK                0xf0000000
 373 #define MPIC_REGSET(val)                (((val) & 0xf ) << 28)
 374 #define MPIC_GET_REGSET(flags)          (((flags) >> 28) & 0xf)
 375
 376 #define MPIC_REGSET_STANDARD            MPIC_REGSET(0)  /* Original MPIC */
 377 #define MPIC_REGSET_TSI108              MPIC_REGSET(1)  /* Tsi108/109 PIC */
 378
 379 /* Allocate the controller structure and setup the linux irq descs
 380  * for the range if interrupts passed in. No HW initialization is
 381  * actually performed.
 382  *
 383  * @phys_addr:  physial base address of the MPIC
 384  * @flags:      flags, see constants above
 385  * @isu_size:   number of interrupts in an ISU. Use 0 to use a
 386  *              standard ISU-less setup (aka powermac)
 387  * @irq_offset: first irq number to assign to this mpic
 388  * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 389  *              to match the number of sources
 390  * @ipi_offset: first irq number to assign to this mpic IPI sources,
 391  *              used only on primary mpic
 392  * @senses:     array of sense values
 393  * @senses_num: number of entries in the array
 394  *
 395  * Note about the sense array. If none is passed, all interrupts are
 396  * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
 397  * case they are edge positive (and the array is ignored anyway).
 398  * The values in the array start at the first source of the MPIC,
 399  * that is senses[0] correspond to linux irq "irq_offset".
 400  */
 401 extern struct mpic *mpic_alloc(struct device_node *node,
 402                                phys_addr_t phys_addr,
 403                                unsigned int flags,
 404                                unsigned int isu_size,
 405                                unsigned int irq_count,
 406                                const char *name);
 407
 408 /* Assign ISUs, to call before mpic_init()
 409  *
 410  * @mpic:       controller structure as returned by mpic_alloc()
 411  * @isu_num:    ISU number
 412  * @phys_addr:  physical address of the ISU
 413  */
 414 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 415                             phys_addr_t phys_addr);
 416
 417 /* Set default sense codes
 418  *
 419  * @mpic:       controller
 420  * @senses:     array of sense codes
 421  * @count:      size of above array
 422  *
 423  * Optionally provide an array (indexed on hardware interrupt numbers
 424  * for this MPIC) of default sense codes for the chip. Those are linux
 425  * sense codes IRQ_TYPE_*
 426  *
 427  * The driver gets ownership of the pointer, don't dispose of it or
 428  * anything like that. __init only.
 429  */
 430 extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
 431
 432
 433 /* Initialize the controller. After this has been called, none of the above
 434  * should be called again for this mpic
 435  */
 436 extern void mpic_init(struct mpic *mpic);
 437
 438 /*
 439  * All of the following functions must only be used after the
 440  * ISUs have been assigned and the controller fully initialized
 441  * with mpic_init()
 442  */
 443
 444
 445 /* Change the priority of an interrupt. Default is 8 for irqs and
 446  * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 447  * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 448  */
 449 extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
 450
 451 /* Setup a non-boot CPU */
 452 extern void mpic_setup_this_cpu(void);
 453
 454 /* Clean up for kexec (or cpu offline or ...) */
 455 extern void mpic_teardown_this_cpu(int secondary);
 456
 457 /* Get the current cpu priority for this cpu (0..15) */
 458 extern int mpic_cpu_get_priority(void);
 459
 460 /* Set the current cpu priority for this cpu */
 461 extern void mpic_cpu_set_priority(int prio);
 462
 463 /* Request IPIs on primary mpic */
 464 extern void mpic_request_ipis(void);
 465
 466 /* Send an IPI (non offseted number 0..3) */
 467 extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
 468
 469 /* Send a message (IPI) to a given target (cpu number or MSG_*) */
 470 void smp_mpic_message_pass(int target, int msg);
 471
 472 /* Unmask a specific virq */
 473 extern void mpic_unmask_irq(unsigned int irq);
 474 /* Mask a specific virq */
 475 extern void mpic_mask_irq(unsigned int irq);
 476 /* EOI a specific virq */
 477 extern void mpic_end_irq(unsigned int irq);
 478
 479 /* Fetch interrupt from a given mpic */
 480 extern unsigned int mpic_get_one_irq(struct mpic *mpic);
 481 /* This one gets from the primary mpic */
 482 extern unsigned int mpic_get_irq(void);
 483 /* This one gets from the primary mpic via CoreInt*/
 484 extern unsigned int mpic_get_coreint_irq(void);
 485 /* Fetch Machine Check interrupt from primary mpic */
 486 extern unsigned int mpic_get_mcirq(void);
 487
 488 /* Set the EPIC clock ratio */
 489 void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
 490
 491 /* Enable/Disable EPIC serial interrupt mode */
 492 void mpic_set_serial_int(struct mpic *mpic, int enable);
 493
 494 #endif /* __KERNEL__ */
 495 #endif  /* _ASM_POWERPC_MPIC_H */