| blob | ad95c7f50090c749c32c7fe6f7936f179f240606 |
1 /*
2 * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Device Tree binding constants for Samsung S3C64xx clock controller.
9 */
11 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
12 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
14 /*
15 * Let each exported clock get a unique index, which is used on DT-enabled
16 * platforms to lookup the clock from a clock specifier. These indices are
17 * therefore considered an ABI and so must not be changed. This implies
18 * that new clocks should be added either in free spaces between clock groups
19 * or at the end.
20 */
22 /* Core clocks. */
23 #define CLK27M 1
24 #define CLK48M 2
25 #define FOUT_APLL 3
26 #define FOUT_MPLL 4
27 #define FOUT_EPLL 5
28 #define ARMCLK 6
29 #define HCLKX2 7
30 #define HCLK 8
31 #define PCLK 9
33 /* HCLK bus clocks. */
34 #define HCLK_3DSE 16
35 #define HCLK_UHOST 17
36 #define HCLK_SECUR 18
37 #define HCLK_SDMA1 19
38 #define HCLK_SDMA0 20
39 #define HCLK_IROM 21
40 #define HCLK_DDR1 22
41 #define HCLK_MEM1 23
42 #define HCLK_MEM0 24
43 #define HCLK_USB 25
44 #define HCLK_HSMMC2 26
45 #define HCLK_HSMMC1 27
46 #define HCLK_HSMMC0 28
47 #define HCLK_MDP 29
48 #define HCLK_DHOST 30
49 #define HCLK_IHOST 31
50 #define HCLK_DMA1 32
51 #define HCLK_DMA0 33
52 #define HCLK_JPEG 34
53 #define HCLK_CAMIF 35
54 #define HCLK_SCALER 36
55 #define HCLK_2D 37
56 #define HCLK_TV 38
57 #define HCLK_POST0 39
58 #define HCLK_ROT 40
59 #define HCLK_LCD 41
60 #define HCLK_TZIC 42
61 #define HCLK_INTC 43
62 #define HCLK_MFC 44
63 #define HCLK_DDR0 45
65 /* PCLK bus clocks. */
66 #define PCLK_IIC1 48
67 #define PCLK_IIS2 49
68 #define PCLK_SKEY 50
69 #define PCLK_CHIPID 51
70 #define PCLK_SPI1 52
71 #define PCLK_SPI0 53
72 #define PCLK_HSIRX 54
73 #define PCLK_HSITX 55
74 #define PCLK_GPIO 56
75 #define PCLK_IIC0 57
76 #define PCLK_IIS1 58
77 #define PCLK_IIS0 59
78 #define PCLK_AC97 60
79 #define PCLK_TZPC 61
80 #define PCLK_TSADC 62
81 #define PCLK_KEYPAD 63
82 #define PCLK_IRDA 64
83 #define PCLK_PCM1 65
84 #define PCLK_PCM0 66
85 #define PCLK_PWM 67
86 #define PCLK_RTC 68
87 #define PCLK_WDT 69
88 #define PCLK_UART3 70
89 #define PCLK_UART2 71
90 #define PCLK_UART1 72
91 #define PCLK_UART0 73
92 #define PCLK_MFC 74
94 /* Special clocks. */
95 #define SCLK_UHOST 80
96 #define SCLK_MMC2_48 81
97 #define SCLK_MMC1_48 82
98 #define SCLK_MMC0_48 83
99 #define SCLK_MMC2 84
100 #define SCLK_MMC1 85
101 #define SCLK_MMC0 86
102 #define SCLK_SPI1_48 87
103 #define SCLK_SPI0_48 88
104 #define SCLK_SPI1 89
105 #define SCLK_SPI0 90
106 #define SCLK_DAC27 91
107 #define SCLK_TV27 92
108 #define SCLK_SCALER27 93
109 #define SCLK_SCALER 94
110 #define SCLK_LCD27 95
111 #define SCLK_LCD 96
112 #define SCLK_FIMC 97
113 #define SCLK_POST0_27 98
114 #define SCLK_AUDIO2 99
115 #define SCLK_POST0 100
116 #define SCLK_AUDIO1 101
117 #define SCLK_AUDIO0 102
118 #define SCLK_SECUR 103
119 #define SCLK_IRDA 104
120 #define SCLK_UART 105
121 #define SCLK_MFC 106
122 #define SCLK_CAM 107
123 #define SCLK_JPEG 108
124 #define SCLK_ONENAND 109
126 /* MEM0 bus clocks - S3C6410-specific. */
127 #define MEM0_CFCON 112
128 #define MEM0_ONENAND1 113
129 #define MEM0_ONENAND0 114
130 #define MEM0_NFCON 115
131 #define MEM0_SROM 116
133 /* Muxes. */
134 #define MOUT_APLL 128
135 #define MOUT_MPLL 129
136 #define MOUT_EPLL 130
137 #define MOUT_MFC 131
138 #define MOUT_AUDIO0 132
139 #define MOUT_AUDIO1 133
140 #define MOUT_UART 134
141 #define MOUT_SPI0 135
142 #define MOUT_SPI1 136
143 #define MOUT_MMC0 137
144 #define MOUT_MMC1 138
145 #define MOUT_MMC2 139
146 #define MOUT_UHOST 140
147 #define MOUT_IRDA 141
148 #define MOUT_LCD 142
149 #define MOUT_SCALER 143
150 #define MOUT_DAC27 144
151 #define MOUT_TV27 145
152 #define MOUT_AUDIO2 146
154 /* Dividers. */
155 #define DOUT_MPLL 160
156 #define DOUT_SECUR 161
157 #define DOUT_CAM 162
158 #define DOUT_JPEG 163
159 #define DOUT_MFC 164
160 #define DOUT_MMC0 165
161 #define DOUT_MMC1 166
162 #define DOUT_MMC2 167
163 #define DOUT_LCD 168
164 #define DOUT_SCALER 169
165 #define DOUT_UHOST 170
166 #define DOUT_SPI0 171
167 #define DOUT_SPI1 172
168 #define DOUT_AUDIO0 173
169 #define DOUT_AUDIO1 174
170 #define DOUT_UART 175
171 #define DOUT_IRDA 176
172 #define DOUT_FIMC 177
173 #define DOUT_AUDIO2 178
175 /* Total number of clocks. */
176 #define NR_CLKS (DOUT_AUDIO2 + 1)