arch/arm/mach-exynos/clock-exynos4212.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4212 - Clock support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/syscore_ops.h>
  17
  18 #include <plat/cpu-freq.h>
  19 #include <plat/clock.h>
  20 #include <plat/cpu.h>
  21 #include <plat/pll.h>
  22 #include <plat/s5p-clock.h>
  23 #include <plat/clock-clksrc.h>
  24 #include <plat/pm.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/map.h>
  28 #include <mach/regs-clock.h>
  29 #include <mach/sysmmu.h>
  30
  31 #include "common.h"
  32 #include "clock-exynos4.h"
  33
  34 #ifdef CONFIG_PM_SLEEP
  35 static struct sleep_save exynos4212_clock_save[] = {
  36         SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
  37         SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
  38         SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
  39         SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
  40 };
  41 #endif
  42
  43 static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
  44 {
  45         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
  46 }
  47
  48 static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
  49 {
  50         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
  51 }
  52
  53 static struct clk *clk_src_mpll_user_list[] = {
  54         [0] = &clk_fin_mpll,
  55         [1] = &exynos4_clk_mout_mpll.clk,
  56 };
  57
  58 static struct clksrc_sources clk_src_mpll_user = {
  59         .sources        = clk_src_mpll_user_list,
  60         .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
  61 };
  62
  63 static struct clksrc_clk clk_mout_mpll_user = {
  64         .clk = {
  65                 .name           = "mout_mpll_user",
  66         },
  67         .sources        = &clk_src_mpll_user,
  68         .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
  69 };
  70
  71 static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
  72         .clk    = {
  73                 .name           = "mout_g2d0",
  74         },
  75         .sources = &exynos4_clkset_mout_g2d0,
  76         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
  77 };
  78
  79 static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
  80         .clk    = {
  81                 .name           = "mout_g2d1",
  82         },
  83         .sources = &exynos4_clkset_mout_g2d1,
  84         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
  85 };
  86
  87 static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
  88         [0] = &exynos4x12_clk_mout_g2d0.clk,
  89         [1] = &exynos4x12_clk_mout_g2d1.clk,
  90 };
  91
  92 static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
  93         .sources        = exynos4x12_clkset_mout_g2d_list,
  94         .nr_sources     = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
  95 };
  96
  97 static struct clksrc_clk *sysclks[] = {
  98         &clk_mout_mpll_user,
  99 };
 100
 101 static struct clksrc_clk clksrcs[] = {
 102         {
 103                 .clk    = {
 104                         .name           = "sclk_fimg2d",
 105                 },
 106                 .sources = &exynos4x12_clkset_mout_g2d,
 107                 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
 108                 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
 109         },
 110 };
 111
 112 static struct clk init_clocks_off[] = {
 113         {
 114                 .name           = SYSMMU_CLOCK_NAME,
 115                 .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
 116                 .enable         = exynos4_clk_ip_dmc_ctrl,
 117                 .ctrlbit        = (1 << 24),
 118         }, {
 119                 .name           = SYSMMU_CLOCK_NAME,
 120                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 121                 .enable         = exynos4212_clk_ip_isp0_ctrl,
 122                 .ctrlbit        = (7 << 8),
 123         }, {
 124                 .name           = SYSMMU_CLOCK_NAME2,
 125                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 126                 .enable         = exynos4212_clk_ip_isp1_ctrl,
 127                 .ctrlbit        = (1 << 4),
 128         }, {
 129                 .name           = "flite",
 130                 .devname        = "exynos-fimc-lite.0",
 131                 .enable         = exynos4212_clk_ip_isp0_ctrl,
 132                 .ctrlbit        = (1 << 4),
 133         }, {
 134                 .name           = "flite",
 135                 .devname        = "exynos-fimc-lite.1",
 136                 .enable         = exynos4212_clk_ip_isp0_ctrl,
 137                 .ctrlbit        = (1 << 3),
 138         }, {
 139                 .name           = "fimg2d",
 140                 .enable         = exynos4_clk_ip_dmc_ctrl,
 141                 .ctrlbit        = (1 << 23),
 142         },
 143 };
 144
 145 #ifdef CONFIG_PM_SLEEP
 146 static int exynos4212_clock_suspend(void)
 147 {
 148         s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
 149
 150         return 0;
 151 }
 152
 153 static void exynos4212_clock_resume(void)
 154 {
 155         s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
 156 }
 157
 158 #else
 159 #define exynos4212_clock_suspend NULL
 160 #define exynos4212_clock_resume NULL
 161 #endif
 162
 163 static struct syscore_ops exynos4212_clock_syscore_ops = {
 164         .suspend        = exynos4212_clock_suspend,
 165         .resume         = exynos4212_clock_resume,
 166 };
 167
 168 void __init exynos4212_register_clocks(void)
 169 {
 170         int ptr;
 171
 172         /* usbphy1 is removed */
 173         exynos4_clkset_group_list[4] = NULL;
 174
 175         /* mout_mpll_user is used */
 176         exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
 177         exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
 178
 179         exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
 180         exynos4_clk_mout_mpll.reg_src.shift = 12;
 181         exynos4_clk_mout_mpll.reg_src.size = 1;
 182
 183         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 184                 s3c_register_clksrc(sysclks[ptr], 1);
 185
 186         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 187
 188         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 189         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 190
 191         register_syscore_ops(&exynos4212_clock_syscore_ops);
 192 }