arch/arm/mach-exynos/dma.c

   1 /* linux/arch/arm/mach-exynos4/dma.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   7  *      Jaswinder Singh <jassi.brar@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include <linux/dma-mapping.h>
  25 #include <linux/amba/bus.h>
  26 #include <linux/amba/pl330.h>
  27 #include <linux/of.h>
  28
  29 #include <asm/irq.h>
  30 #include <plat/devs.h>
  31 #include <plat/irqs.h>
  32 #include <plat/cpu.h>
  33
  34 #include <mach/map.h>
  35 #include <mach/irqs.h>
  36 #include <mach/dma.h>
  37
  38 static u8 exynos4210_pdma0_peri[] = {
  39         DMACH_PCM0_RX,
  40         DMACH_PCM0_TX,
  41         DMACH_PCM2_RX,
  42         DMACH_PCM2_TX,
  43         DMACH_MSM_REQ0,
  44         DMACH_MSM_REQ2,
  45         DMACH_SPI0_RX,
  46         DMACH_SPI0_TX,
  47         DMACH_SPI2_RX,
  48         DMACH_SPI2_TX,
  49         DMACH_I2S0S_TX,
  50         DMACH_I2S0_RX,
  51         DMACH_I2S0_TX,
  52         DMACH_I2S2_RX,
  53         DMACH_I2S2_TX,
  54         DMACH_UART0_RX,
  55         DMACH_UART0_TX,
  56         DMACH_UART2_RX,
  57         DMACH_UART2_TX,
  58         DMACH_UART4_RX,
  59         DMACH_UART4_TX,
  60         DMACH_SLIMBUS0_RX,
  61         DMACH_SLIMBUS0_TX,
  62         DMACH_SLIMBUS2_RX,
  63         DMACH_SLIMBUS2_TX,
  64         DMACH_SLIMBUS4_RX,
  65         DMACH_SLIMBUS4_TX,
  66         DMACH_AC97_MICIN,
  67         DMACH_AC97_PCMIN,
  68         DMACH_AC97_PCMOUT,
  69 };
  70
  71 static u8 exynos4212_pdma0_peri[] = {
  72         DMACH_PCM0_RX,
  73         DMACH_PCM0_TX,
  74         DMACH_PCM2_RX,
  75         DMACH_PCM2_TX,
  76         DMACH_MIPI_HSI0,
  77         DMACH_MIPI_HSI1,
  78         DMACH_SPI0_RX,
  79         DMACH_SPI0_TX,
  80         DMACH_SPI2_RX,
  81         DMACH_SPI2_TX,
  82         DMACH_I2S0S_TX,
  83         DMACH_I2S0_RX,
  84         DMACH_I2S0_TX,
  85         DMACH_I2S2_RX,
  86         DMACH_I2S2_TX,
  87         DMACH_UART0_RX,
  88         DMACH_UART0_TX,
  89         DMACH_UART2_RX,
  90         DMACH_UART2_TX,
  91         DMACH_UART4_RX,
  92         DMACH_UART4_TX,
  93         DMACH_SLIMBUS0_RX,
  94         DMACH_SLIMBUS0_TX,
  95         DMACH_SLIMBUS2_RX,
  96         DMACH_SLIMBUS2_TX,
  97         DMACH_SLIMBUS4_RX,
  98         DMACH_SLIMBUS4_TX,
  99         DMACH_AC97_MICIN,
 100         DMACH_AC97_PCMIN,
 101         DMACH_AC97_PCMOUT,
 102         DMACH_MIPI_HSI4,
 103         DMACH_MIPI_HSI5,
 104 };
 105
 106 static u8 exynos5250_pdma0_peri[] = {
 107         DMACH_PCM0_RX,
 108         DMACH_PCM0_TX,
 109         DMACH_PCM2_RX,
 110         DMACH_PCM2_TX,
 111         DMACH_SPI0_RX,
 112         DMACH_SPI0_TX,
 113         DMACH_SPI2_RX,
 114         DMACH_SPI2_TX,
 115         DMACH_I2S0S_TX,
 116         DMACH_I2S0_RX,
 117         DMACH_I2S0_TX,
 118         DMACH_I2S2_RX,
 119         DMACH_I2S2_TX,
 120         DMACH_UART0_RX,
 121         DMACH_UART0_TX,
 122         DMACH_UART2_RX,
 123         DMACH_UART2_TX,
 124         DMACH_UART4_RX,
 125         DMACH_UART4_TX,
 126         DMACH_SLIMBUS0_RX,
 127         DMACH_SLIMBUS0_TX,
 128         DMACH_SLIMBUS2_RX,
 129         DMACH_SLIMBUS2_TX,
 130         DMACH_SLIMBUS4_RX,
 131         DMACH_SLIMBUS4_TX,
 132         DMACH_AC97_MICIN,
 133         DMACH_AC97_PCMIN,
 134         DMACH_AC97_PCMOUT,
 135         DMACH_MIPI_HSI0,
 136         DMACH_MIPI_HSI2,
 137         DMACH_MIPI_HSI4,
 138         DMACH_MIPI_HSI6,
 139 };
 140
 141 static struct dma_pl330_platdata exynos_pdma0_pdata;
 142
 143 static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
 144         EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
 145
 146 static u8 exynos4210_pdma1_peri[] = {
 147         DMACH_PCM0_RX,
 148         DMACH_PCM0_TX,
 149         DMACH_PCM1_RX,
 150         DMACH_PCM1_TX,
 151         DMACH_MSM_REQ1,
 152         DMACH_MSM_REQ3,
 153         DMACH_SPI1_RX,
 154         DMACH_SPI1_TX,
 155         DMACH_I2S0S_TX,
 156         DMACH_I2S0_RX,
 157         DMACH_I2S0_TX,
 158         DMACH_I2S1_RX,
 159         DMACH_I2S1_TX,
 160         DMACH_UART0_RX,
 161         DMACH_UART0_TX,
 162         DMACH_UART1_RX,
 163         DMACH_UART1_TX,
 164         DMACH_UART3_RX,
 165         DMACH_UART3_TX,
 166         DMACH_SLIMBUS1_RX,
 167         DMACH_SLIMBUS1_TX,
 168         DMACH_SLIMBUS3_RX,
 169         DMACH_SLIMBUS3_TX,
 170         DMACH_SLIMBUS5_RX,
 171         DMACH_SLIMBUS5_TX,
 172 };
 173
 174 static u8 exynos4212_pdma1_peri[] = {
 175         DMACH_PCM0_RX,
 176         DMACH_PCM0_TX,
 177         DMACH_PCM1_RX,
 178         DMACH_PCM1_TX,
 179         DMACH_MIPI_HSI2,
 180         DMACH_MIPI_HSI3,
 181         DMACH_SPI1_RX,
 182         DMACH_SPI1_TX,
 183         DMACH_I2S0S_TX,
 184         DMACH_I2S0_RX,
 185         DMACH_I2S0_TX,
 186         DMACH_I2S1_RX,
 187         DMACH_I2S1_TX,
 188         DMACH_UART0_RX,
 189         DMACH_UART0_TX,
 190         DMACH_UART1_RX,
 191         DMACH_UART1_TX,
 192         DMACH_UART3_RX,
 193         DMACH_UART3_TX,
 194         DMACH_SLIMBUS1_RX,
 195         DMACH_SLIMBUS1_TX,
 196         DMACH_SLIMBUS3_RX,
 197         DMACH_SLIMBUS3_TX,
 198         DMACH_SLIMBUS5_RX,
 199         DMACH_SLIMBUS5_TX,
 200         DMACH_SLIMBUS0AUX_RX,
 201         DMACH_SLIMBUS0AUX_TX,
 202         DMACH_SPDIF,
 203         DMACH_MIPI_HSI6,
 204         DMACH_MIPI_HSI7,
 205 };
 206
 207 static u8 exynos5250_pdma1_peri[] = {
 208         DMACH_PCM0_RX,
 209         DMACH_PCM0_TX,
 210         DMACH_PCM1_RX,
 211         DMACH_PCM1_TX,
 212         DMACH_SPI1_RX,
 213         DMACH_SPI1_TX,
 214         DMACH_PWM,
 215         DMACH_SPDIF,
 216         DMACH_I2S0S_TX,
 217         DMACH_I2S0_RX,
 218         DMACH_I2S0_TX,
 219         DMACH_I2S1_RX,
 220         DMACH_I2S1_TX,
 221         DMACH_UART0_RX,
 222         DMACH_UART0_TX,
 223         DMACH_UART1_RX,
 224         DMACH_UART1_TX,
 225         DMACH_UART3_RX,
 226         DMACH_UART3_TX,
 227         DMACH_SLIMBUS1_RX,
 228         DMACH_SLIMBUS1_TX,
 229         DMACH_SLIMBUS3_RX,
 230         DMACH_SLIMBUS3_TX,
 231         DMACH_SLIMBUS5_RX,
 232         DMACH_SLIMBUS5_TX,
 233         DMACH_SLIMBUS0AUX_RX,
 234         DMACH_SLIMBUS0AUX_TX,
 235         DMACH_DISP1,
 236         DMACH_MIPI_HSI1,
 237         DMACH_MIPI_HSI3,
 238         DMACH_MIPI_HSI5,
 239         DMACH_MIPI_HSI7,
 240 };
 241
 242 static struct dma_pl330_platdata exynos_pdma1_pdata;
 243
 244 static AMBA_AHB_DEVICE(exynos_pdma1,  "dma-pl330.1", 0x00041330,
 245         EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
 246
 247 static u8 mdma_peri[] = {
 248         DMACH_MTOM_0,
 249         DMACH_MTOM_1,
 250         DMACH_MTOM_2,
 251         DMACH_MTOM_3,
 252         DMACH_MTOM_4,
 253         DMACH_MTOM_5,
 254         DMACH_MTOM_6,
 255         DMACH_MTOM_7,
 256 };
 257
 258 static struct dma_pl330_platdata exynos_mdma1_pdata = {
 259         .nr_valid_peri = ARRAY_SIZE(mdma_peri),
 260         .peri_id = mdma_peri,
 261 };
 262
 263 static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,
 264         EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
 265
 266 static int __init exynos_dma_init(void)
 267 {
 268         if (of_have_populated_dt())
 269                 return 0;
 270
 271         if (soc_is_exynos4210()) {
 272                 exynos_pdma0_pdata.nr_valid_peri =
 273                         ARRAY_SIZE(exynos4210_pdma0_peri);
 274                 exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
 275                 exynos_pdma1_pdata.nr_valid_peri =
 276                         ARRAY_SIZE(exynos4210_pdma1_peri);
 277                 exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
 278         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
 279                 exynos_pdma0_pdata.nr_valid_peri =
 280                         ARRAY_SIZE(exynos4212_pdma0_peri);
 281                 exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
 282                 exynos_pdma1_pdata.nr_valid_peri =
 283                         ARRAY_SIZE(exynos4212_pdma1_peri);
 284                 exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
 285         } else if (soc_is_exynos5250()) {
 286                 exynos_pdma0_pdata.nr_valid_peri =
 287                         ARRAY_SIZE(exynos5250_pdma0_peri);
 288                 exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
 289                 exynos_pdma1_pdata.nr_valid_peri =
 290                         ARRAY_SIZE(exynos5250_pdma1_peri);
 291                 exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
 292
 293                 exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
 294                 exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
 295                 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
 296                 exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
 297                 exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
 298                 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
 299                 exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
 300                 exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
 301                 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
 302         }
 303
 304         dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
 305         dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
 306         amba_device_register(&exynos_pdma0_device, &iomem_resource);
 307
 308         dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
 309         dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
 310         amba_device_register(&exynos_pdma1_device, &iomem_resource);
 311
 312         dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
 313         amba_device_register(&exynos_mdma1_device, &iomem_resource);
 314
 315         return 0;
 316 }
 317 arch_initcall(exynos_dma_init);