arch/arm/mach-msm/platsmp.c

   1 /*
   2  *  Copyright (C) 2002 ARM Ltd.
   3  *  All Rights Reserved
   4  *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/smp.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/hardware/gic.h>
  20 #include <asm/cacheflush.h>
  21 #include <asm/cputype.h>
  22 #include <asm/mach-types.h>
  23 #include <asm/smp_plat.h>
  24
  25 #include <mach/msm_iomap.h>
  26
  27 #include "scm-boot.h"
  28
  29 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
  30 #define SCSS_CPU1CORE_RESET 0xD80
  31 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
  32
  33 /* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
  34 #define GIC_PPI_EDGE_MASK 0xFFFFD7FF
  35
  36 extern void msm_secondary_startup(void);
  37 /*
  38  * control for which core is the next to come out of the secondary
  39  * boot "holding pen".
  40  */
  41 volatile int pen_release = -1;
  42
  43 static DEFINE_SPINLOCK(boot_lock);
  44
  45 static inline int get_core_count(void)
  46 {
  47         /* 1 + the PART[1:0] field of MIDR */
  48         return ((read_cpuid_id() >> 4) & 3) + 1;
  49 }
  50
  51 void __cpuinit platform_secondary_init(unsigned int cpu)
  52 {
  53         /* Configure edge-triggered PPIs */
  54         writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
  55
  56         /*
  57          * if any interrupts are already enabled for the primary
  58          * core (e.g. timer irq), then they will not have been enabled
  59          * for us: do so
  60          */
  61         gic_secondary_init(0);
  62
  63         /*
  64          * let the primary processor know we're out of the
  65          * pen, then head off into the C entry point
  66          */
  67         pen_release = -1;
  68         smp_wmb();
  69
  70         /*
  71          * Synchronise with the boot thread.
  72          */
  73         spin_lock(&boot_lock);
  74         spin_unlock(&boot_lock);
  75 }
  76
  77 static __cpuinit void prepare_cold_cpu(unsigned int cpu)
  78 {
  79         int ret;
  80         ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
  81                                 SCM_FLAG_COLDBOOT_CPU1);
  82         if (ret == 0) {
  83                 void __iomem *sc1_base_ptr;
  84                 sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
  85                 if (sc1_base_ptr) {
  86                         writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
  87                         writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
  88                         writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
  89                         iounmap(sc1_base_ptr);
  90                 }
  91         } else
  92                 printk(KERN_DEBUG "Failed to set secondary core boot "
  93                                   "address\n");
  94 }
  95
  96 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  97 {
  98         unsigned long timeout;
  99         static int cold_boot_done;
 100
 101         /* Only need to bring cpu out of reset this way once */
 102         if (cold_boot_done == false) {
 103                 prepare_cold_cpu(cpu);
 104                 cold_boot_done = true;
 105         }
 106
 107         /*
 108          * set synchronisation state between this boot processor
 109          * and the secondary one
 110          */
 111         spin_lock(&boot_lock);
 112
 113         /*
 114          * The secondary processor is waiting to be released from
 115          * the holding pen - release it, then wait for it to flag
 116          * that it has been released by resetting pen_release.
 117          *
 118          * Note that "pen_release" is the hardware CPU ID, whereas
 119          * "cpu" is Linux's internal ID.
 120          */
 121         pen_release = cpu_logical_map(cpu);
 122         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 123         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 124
 125         /*
 126          * Send the secondary CPU a soft interrupt, thereby causing
 127          * the boot monitor to read the system wide flags register,
 128          * and branch to the address found there.
 129          */
 130         gic_raise_softirq(cpumask_of(cpu), 0);
 131
 132         timeout = jiffies + (1 * HZ);
 133         while (time_before(jiffies, timeout)) {
 134                 smp_rmb();
 135                 if (pen_release == -1)
 136                         break;
 137
 138                 udelay(10);
 139         }
 140
 141         /*
 142          * now the secondary core is starting up let it run its
 143          * calibrations, then wait for it to finish
 144          */
 145         spin_unlock(&boot_lock);
 146
 147         return pen_release != -1 ? -ENOSYS : 0;
 148 }
 149
 150 /*
 151  * Initialise the CPU possible map early - this describes the CPUs
 152  * which may be present or become present in the system. The msm8x60
 153  * does not support the ARM SCU, so just set the possible cpu mask to
 154  * NR_CPUS.
 155  */
 156 void __init smp_init_cpus(void)
 157 {
 158         unsigned int i, ncores = get_core_count();
 159
 160         if (ncores > nr_cpu_ids) {
 161                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 162                         ncores, nr_cpu_ids);
 163                 ncores = nr_cpu_ids;
 164         }
 165
 166         for (i = 0; i < ncores; i++)
 167                 set_cpu_possible(i, true);
 168
 169         set_smp_cross_call(gic_raise_softirq);
 170 }
 171
 172 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 173 {
 174 }