| blob | 4fee00d414e87c78d8a09ef3e9662b7bb7234c66 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <linux/init.h>
23 #include <asm/processor.h>
24 #include <asm/page.h>
25 #include <asm/mmu.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/ptrace.h>
33 #include <asm/fixmap.h>
34 #include <asm/export.h>
36 /* Macro to make the code more readable. */
37 #ifdef CONFIG_8xx_CPU6
38 #define SPRN_MI_TWC_ADDR 0x2b80
39 #define SPRN_MI_RPN_ADDR 0x2d80
40 #define SPRN_MD_TWC_ADDR 0x3b80
41 #define SPRN_MD_RPN_ADDR 0x3d80
43 #define MTSPR_CPU6(spr, reg, treg) \
44 li treg, spr##_ADDR; \
45 stw treg, 12(r0); \
46 lwz treg, 12(r0); \
47 mtspr spr, reg
48 #else
49 #define MTSPR_CPU6(spr, reg, treg) \
50 mtspr spr, reg
51 #endif
53 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
54 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
55 #define SIMPLE_KERNEL_ADDRESS 1
56 #endif
58 /*
59 * We need an ITLB miss handler for kernel addresses if:
60 * - Either we have modules
61 * - Or we have not pinned the first 8M
62 */
63 #if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
64 defined(CONFIG_DEBUG_PAGEALLOC)
65 #define ITLB_MISS_KERNEL 1
66 #endif
68 /*
69 * Value for the bits that have fixed value in RPN entries.
70 * Also used for tagging DAR for DTLBerror.
71 */
72 #ifdef CONFIG_PPC_16K_PAGES
73 #define RPN_PATTERN (0x00f0 | MD_SPS16K)
74 #else
75 #define RPN_PATTERN 0x00f0
76 #endif
78 #define PAGE_SHIFT_512K 19
79 #define PAGE_SHIFT_8M 23
81 __HEAD
82 _ENTRY(_stext);
83 _ENTRY(_start);
85 /* MPC8xx
86 * This port was done on an MBX board with an 860. Right now I only
87 * support an ELF compressed (zImage) boot from EPPC-Bug because the
88 * code there loads up some registers before calling us:
89 * r3: ptr to board info data
90 * r4: initrd_start or if no initrd then 0
91 * r5: initrd_end - unused if r4 is 0
92 * r6: Start of command line string
93 * r7: End of command line string
94 *
95 * I decided to use conditional compilation instead of checking PVR and
96 * adding more processor specific branches around code I don't need.
97 * Since this is an embedded processor, I also appreciate any memory
98 * savings I can get.
99 *
100 * The MPC8xx does not have any BATs, but it supports large page sizes.
101 * We first initialize the MMU to support 8M byte pages, then load one
102 * entry into each of the instruction and data TLBs to map the first
103 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
104 * the "internal" processor registers before MMU_init is called.
105 *
106 * -- Dan
107 */
108 .globl __start
109 __start:
110 mr r31,r3 /* save device tree ptr */
112 /* We have to turn on the MMU right away so we get cache modes
113 * set correctly.
114 */
115 bl initial_mmu
117 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
118 * ready to work.
119 */
121 turn_on_mmu:
122 mfmsr r0
123 ori r0,r0,MSR_DR|MSR_IR
124 mtspr SPRN_SRR1,r0
125 lis r0,start_here@h
126 ori r0,r0,start_here@l
127 mtspr SPRN_SRR0,r0
128 rfi /* enables MMU */
130 /*
131 * Exception entry code. This code runs with address translation
132 * turned off, i.e. using physical addresses.
133 * We assume sprg3 has the physical address of the current
134 * task's thread_struct.
135 */
136 #define EXCEPTION_PROLOG \
137 EXCEPTION_PROLOG_0; \
138 mfcr r10; \
139 EXCEPTION_PROLOG_1; \
140 EXCEPTION_PROLOG_2
142 #define EXCEPTION_PROLOG_0 \
143 mtspr SPRN_SPRG_SCRATCH0,r10; \
144 mtspr SPRN_SPRG_SCRATCH1,r11
146 #define EXCEPTION_PROLOG_1 \
147 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
148 andi. r11,r11,MSR_PR; \
149 tophys(r11,r1); /* use tophys(r1) if kernel */ \
150 beq 1f; \
151 mfspr r11,SPRN_SPRG_THREAD; \
152 lwz r11,THREAD_INFO-THREAD(r11); \
153 addi r11,r11,THREAD_SIZE; \
154 tophys(r11,r11); \
155 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
158 #define EXCEPTION_PROLOG_2 \
159 stw r10,_CCR(r11); /* save registers */ \
160 stw r12,GPR12(r11); \
161 stw r9,GPR9(r11); \
162 mfspr r10,SPRN_SPRG_SCRATCH0; \
163 stw r10,GPR10(r11); \
164 mfspr r12,SPRN_SPRG_SCRATCH1; \
165 stw r12,GPR11(r11); \
166 mflr r10; \
167 stw r10,_LINK(r11); \
168 mfspr r12,SPRN_SRR0; \
169 mfspr r9,SPRN_SRR1; \
170 stw r1,GPR1(r11); \
171 stw r1,0(r11); \
172 tovirt(r1,r11); /* set new kernel sp */ \
173 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
174 mtmsr r10; \
175 stw r0,GPR0(r11); \
176 SAVE_4GPRS(3, r11); \
177 SAVE_2GPRS(7, r11)
179 /*
180 * Exception exit code.
181 */
182 #define EXCEPTION_EPILOG_0 \
183 mfspr r10,SPRN_SPRG_SCRATCH0; \
184 mfspr r11,SPRN_SPRG_SCRATCH1
186 /*
187 * Note: code which follows this uses cr0.eq (set if from kernel),
188 * r11, r12 (SRR0), and r9 (SRR1).
189 *
190 * Note2: once we have set r1 we are in a position to take exceptions
191 * again, and we could thus set MSR:RI at that point.
192 */
194 /*
195 * Exception vectors.
196 */
197 #define EXCEPTION(n, label, hdlr, xfer) \
198 . = n; \
199 label: \
200 EXCEPTION_PROLOG; \
201 addi r3,r1,STACK_FRAME_OVERHEAD; \
202 xfer(n, hdlr)
204 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
205 li r10,trap; \
206 stw r10,_TRAP(r11); \
207 li r10,MSR_KERNEL; \
208 copyee(r10, r9); \
209 bl tfer; \
210 i##n: \
211 .long hdlr; \
212 .long ret
214 #define COPY_EE(d, s) rlwimi d,s,0,16,16
215 #define NOCOPY(d, s)
217 #define EXC_XFER_STD(n, hdlr) \
218 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
219 ret_from_except_full)
221 #define EXC_XFER_LITE(n, hdlr) \
222 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
223 ret_from_except)
225 #define EXC_XFER_EE(n, hdlr) \
226 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
227 ret_from_except_full)
229 #define EXC_XFER_EE_LITE(n, hdlr) \
230 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
231 ret_from_except)
233 /* System reset */
234 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
236 /* Machine check */
237 . = 0x200
238 MachineCheck:
239 EXCEPTION_PROLOG
240 mfspr r4,SPRN_DAR
241 stw r4,_DAR(r11)
242 li r5,RPN_PATTERN
243 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
244 mfspr r5,SPRN_DSISR
245 stw r5,_DSISR(r11)
246 addi r3,r1,STACK_FRAME_OVERHEAD
247 EXC_XFER_STD(0x200, machine_check_exception)
249 /* Data access exception.
250 * This is "never generated" by the MPC8xx.
251 */
252 . = 0x300
253 DataAccess:
255 /* Instruction access exception.
256 * This is "never generated" by the MPC8xx.
257 */
258 . = 0x400
259 InstructionAccess:
261 /* External interrupt */
262 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
264 /* Alignment exception */
265 . = 0x600
266 Alignment:
267 EXCEPTION_PROLOG
268 mfspr r4,SPRN_DAR
269 stw r4,_DAR(r11)
270 li r5,RPN_PATTERN
271 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
272 mfspr r5,SPRN_DSISR
273 stw r5,_DSISR(r11)
274 addi r3,r1,STACK_FRAME_OVERHEAD
275 EXC_XFER_EE(0x600, alignment_exception)
277 /* Program check exception */
278 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
280 /* No FPU on MPC8xx. This exception is not supposed to happen.
281 */
282 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
284 /* Decrementer */
285 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
287 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
288 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
290 /* System call */
291 . = 0xc00
292 SystemCall:
293 EXCEPTION_PROLOG
294 EXC_XFER_EE_LITE(0xc00, DoSyscall)
296 /* Single step - not used on 601 */
297 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
298 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
299 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
301 /* On the MPC8xx, this is a software emulation interrupt. It occurs
302 * for all unimplemented and illegal instructions.
303 */
304 EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD)
306 . = 0x1100
307 /*
308 * For the MPC8xx, this is a software tablewalk to load the instruction
309 * TLB. The task switch loads the M_TW register with the pointer to the first
310 * level table.
311 * If we discover there is no second level table (value is zero) or if there
312 * is an invalid pte, we load that into the TLB, which causes another fault
313 * into the TLB Error interrupt where we can handle such problems.
314 * We have to use the MD_xxx registers for the tablewalk because the
315 * equivalent MI_xxx registers only perform the attribute functions.
316 */
318 #ifdef CONFIG_8xx_CPU15
319 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
320 addi tmp, addr, PAGE_SIZE; \
321 tlbie tmp; \
322 addi tmp, addr, -PAGE_SIZE; \
323 tlbie tmp
324 #else
325 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
326 #endif
328 InstructionTLBMiss:
329 #if defined(CONFIG_8xx_CPU6) || defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
330 mtspr SPRN_SPRG_SCRATCH2, r3
331 #endif
332 EXCEPTION_PROLOG_0
333 #ifdef CONFIG_PPC_8xx_PERF_EVENT
334 lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
335 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
336 addi r11, r11, 1
337 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
338 #endif
340 /* If we are faulting a kernel address, we have to use the
341 * kernel page tables.
342 */
343 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
344 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
345 /* Only modules will cause ITLB Misses as we always
346 * pin the first 8MB of kernel memory */
347 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
348 mfcr r3
349 #endif
350 #ifdef ITLB_MISS_KERNEL
351 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
352 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
353 #else
354 rlwinm r11, r10, 16, 0xfff8
355 cmpli cr0, r11, PAGE_OFFSET@h
356 #ifndef CONFIG_PIN_TLB_TEXT
357 /* It is assumed that kernel code fits into the first 8M page */
358 _ENTRY(ITLBMiss_cmp)
359 cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h
360 #endif
361 #endif
362 #endif
363 mfspr r11, SPRN_M_TW /* Get level 1 table */
364 #ifdef ITLB_MISS_KERNEL
365 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
366 beq+ 3f
367 #else
368 blt+ 3f
369 #endif
370 #ifndef CONFIG_PIN_TLB_TEXT
371 blt cr7, ITLBMissLinear
372 #endif
373 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
374 3:
375 #endif
376 /* Insert level 1 index */
377 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
378 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
380 /* Extract level 2 index */
381 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
382 #ifdef CONFIG_HUGETLB_PAGE
383 mtcr r11
384 bt- 28, 10f /* bit 28 = Large page (8M) */
385 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
386 #endif
387 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
388 lwz r10, 0(r10) /* Get the pte */
389 4:
390 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
391 mtcr r3
392 #endif
393 /* Insert the APG into the TWC from the Linux PTE. */
394 rlwimi r11, r10, 0, 25, 26
395 /* Load the MI_TWC with the attributes for this "segment." */
396 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
398 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
399 rlwimi r10, r11, 1, MI_SPS16K
400 #endif
401 #ifdef CONFIG_SWAP
402 rlwinm r11, r10, 32-5, _PAGE_PRESENT
403 and r11, r11, r10
404 rlwimi r10, r11, 0, _PAGE_PRESENT
405 #endif
406 li r11, RPN_PATTERN
407 /* The Linux PTE won't go exactly into the MMU TLB.
408 * Software indicator bits 20-23 and 28 must be clear.
409 * Software indicator bits 24, 25, 26, and 27 must be
410 * set. All other Linux PTE bits control the behavior
411 * of the MMU.
412 */
413 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
414 rlwimi r10, r11, 0, 0x0ff0 /* Set 24-27, clear 20-23 */
415 #else
416 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */
417 #endif
418 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
420 /* Restore registers */
421 #if defined(CONFIG_8xx_CPU6) || defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
422 mfspr r3, SPRN_SPRG_SCRATCH2
423 #endif
424 EXCEPTION_EPILOG_0
425 rfi
427 #ifdef CONFIG_HUGETLB_PAGE
428 10: /* 8M pages */
429 #ifdef CONFIG_PPC_16K_PAGES
430 /* Extract level 2 index */
431 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
432 /* Add level 2 base */
433 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
434 #else
435 /* Level 2 base */
436 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
437 #endif
438 lwz r10, 0(r10) /* Get the pte */
439 rlwinm r11, r11, 0, 0xf
440 b 4b
442 20: /* 512k pages */
443 /* Extract level 2 index */
444 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
445 /* Add level 2 base */
446 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
447 lwz r10, 0(r10) /* Get the pte */
448 rlwinm r11, r11, 0, 0xf
449 b 4b
450 #endif
452 . = 0x1200
453 DataStoreTLBMiss:
454 mtspr SPRN_SPRG_SCRATCH2, r3
455 EXCEPTION_PROLOG_0
456 #ifdef CONFIG_PPC_8xx_PERF_EVENT
457 lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
458 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
459 addi r11, r11, 1
460 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
461 #endif
462 mfcr r3
464 /* If we are faulting a kernel address, we have to use the
465 * kernel page tables.
466 */
467 mfspr r10, SPRN_MD_EPN
468 rlwinm r11, r10, 16, 0xfff8
469 cmpli cr0, r11, PAGE_OFFSET@h
470 mfspr r11, SPRN_M_TW /* Get level 1 table */
471 blt+ 3f
472 rlwinm r11, r10, 16, 0xfff8
473 #ifndef CONFIG_PIN_TLB_IMMR
474 cmpli cr0, r11, VIRT_IMMR_BASE@h
475 #endif
476 _ENTRY(DTLBMiss_cmp)
477 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
478 #ifndef CONFIG_PIN_TLB_IMMR
479 _ENTRY(DTLBMiss_jmp)
480 beq- DTLBMissIMMR
481 #endif
482 blt cr7, DTLBMissLinear
483 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
484 3:
486 /* Insert level 1 index */
487 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
488 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
490 /* We have a pte table, so load fetch the pte from the table.
491 */
492 /* Extract level 2 index */
493 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
494 #ifdef CONFIG_HUGETLB_PAGE
495 mtcr r11
496 bt- 28, 10f /* bit 28 = Large page (8M) */
497 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
498 #endif
499 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
500 lwz r10, 0(r10) /* Get the pte */
501 4:
502 mtcr r3
504 /* Insert the Guarded flag and APG into the TWC from the Linux PTE.
505 * It is bit 26-27 of both the Linux PTE and the TWC (at least
506 * I got that right :-). It will be better when we can put
507 * this into the Linux pgd/pmd and load it in the operation
508 * above.
509 */
510 rlwimi r11, r10, 0, 26, 27
511 /* Insert the WriteThru flag into the TWC from the Linux PTE.
512 * It is bit 25 in the Linux PTE and bit 30 in the TWC
513 */
514 rlwimi r11, r10, 32-5, 30, 30
515 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
517 /* In 4k pages mode, SPS (bit 28) in RPN must match PS[1] (bit 29)
518 * In 16k pages mode, SPS is always 1 */
519 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
520 rlwimi r10, r11, 1, MD_SPS16K
521 #endif
522 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
523 * We also need to know if the insn is a load/store, so:
524 * Clear _PAGE_PRESENT and load that which will
525 * trap into DTLB Error with store bit set accordinly.
526 */
527 /* PRESENT=0x1, ACCESSED=0x20
528 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
529 * r10 = (r10 & ~PRESENT) | r11;
530 */
531 #ifdef CONFIG_SWAP
532 rlwinm r11, r10, 32-5, _PAGE_PRESENT
533 and r11, r11, r10
534 rlwimi r10, r11, 0, _PAGE_PRESENT
535 #endif
536 /* The Linux PTE won't go exactly into the MMU TLB.
537 * Software indicator bits 22 and 28 must be clear.
538 * Software indicator bits 24, 25, 26, and 27 must be
539 * set. All other Linux PTE bits control the behavior
540 * of the MMU.
541 */
542 li r11, RPN_PATTERN
543 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
544 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
545 #else
546 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
547 #endif
548 rlwimi r10, r11, 0, 20, 20 /* clear 20 */
549 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
551 /* Restore registers */
552 mfspr r3, SPRN_SPRG_SCRATCH2
553 mtspr SPRN_DAR, r11 /* Tag DAR */
554 EXCEPTION_EPILOG_0
555 rfi
557 #ifdef CONFIG_HUGETLB_PAGE
558 10: /* 8M pages */
559 /* Extract level 2 index */
560 #ifdef CONFIG_PPC_16K_PAGES
561 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
562 /* Add level 2 base */
563 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
564 #else
565 /* Level 2 base */
566 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
567 #endif
568 lwz r10, 0(r10) /* Get the pte */
569 rlwinm r11, r11, 0, 0xf
570 b 4b
572 20: /* 512k pages */
573 /* Extract level 2 index */
574 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
575 /* Add level 2 base */
576 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
577 lwz r10, 0(r10) /* Get the pte */
578 rlwinm r11, r11, 0, 0xf
579 b 4b
580 #endif
582 /* This is an instruction TLB error on the MPC8xx. This could be due
583 * to many reasons, such as executing guarded memory or illegal instruction
584 * addresses. There is nothing to do but handle a big time error fault.
585 */
586 . = 0x1300
587 InstructionTLBError:
588 EXCEPTION_PROLOG
589 mr r4,r12
590 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
591 andis. r10,r9,SRR1_ISI_NOPT@h
592 beq+ 1f
593 tlbie r4
594 itlbie:
595 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
596 1: EXC_XFER_LITE(0x400, handle_page_fault)
598 /* This is the data TLB error on the MPC8xx. This could be due to
599 * many reasons, including a dirty update to a pte. We bail out to
600 * a higher level function that can handle it.
601 */
602 . = 0x1400
603 DataTLBError:
604 EXCEPTION_PROLOG_0
605 mfcr r10
607 mfspr r11, SPRN_DAR
608 cmpwi cr0, r11, RPN_PATTERN
609 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
610 DARFixed:/* Return from dcbx instruction bug workaround */
611 EXCEPTION_PROLOG_1
612 EXCEPTION_PROLOG_2
613 mfspr r5,SPRN_DSISR
614 stw r5,_DSISR(r11)
615 mfspr r4,SPRN_DAR
616 andis. r10,r5,DSISR_NOHPTE@h
617 beq+ 1f
618 tlbie r4
619 dtlbie:
620 1: li r10,RPN_PATTERN
621 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
622 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
623 EXC_XFER_LITE(0x300, handle_page_fault)
625 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
626 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
627 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
628 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
629 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
630 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
631 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
633 /* On the MPC8xx, these next four traps are used for development
634 * support of breakpoints and such. Someday I will get around to
635 * using them.
636 */
637 . = 0x1c00
638 DataBreakpoint:
639 EXCEPTION_PROLOG_0
640 mfcr r10
641 mfspr r11, SPRN_SRR0
642 cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
643 cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l
644 beq- cr0, 11f
645 beq- cr7, 11f
646 EXCEPTION_PROLOG_1
647 EXCEPTION_PROLOG_2
648 addi r3,r1,STACK_FRAME_OVERHEAD
649 mfspr r4,SPRN_BAR
650 stw r4,_DAR(r11)
651 mfspr r5,SPRN_DSISR
652 EXC_XFER_EE(0x1c00, do_break)
653 11:
654 mtcr r10
655 EXCEPTION_EPILOG_0
656 rfi
658 #ifdef CONFIG_PPC_8xx_PERF_EVENT
659 . = 0x1d00
660 InstructionBreakpoint:
661 EXCEPTION_PROLOG_0
662 lis r10, (instruction_counter - PAGE_OFFSET)@ha
663 lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10)
664 addi r11, r11, -1
665 stw r11, (instruction_counter - PAGE_OFFSET)@l(r10)
666 lis r10, 0xffff
667 ori r10, r10, 0x01
668 mtspr SPRN_COUNTA, r10
669 EXCEPTION_EPILOG_0
670 rfi
671 #else
672 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
673 #endif
674 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
675 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
677 . = 0x2000
679 /*
680 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM.
681 * not enough space in the DataStoreTLBMiss area.
682 */
683 DTLBMissIMMR:
684 mtcr r3
685 /* Set 512k byte guarded page and mark it valid */
686 li r10, MD_PS512K | MD_GUARDED | MD_SVALID
687 MTSPR_CPU6(SPRN_MD_TWC, r10, r11)
688 mfspr r10, SPRN_IMMR /* Get current IMMR */
689 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
690 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
691 _PAGE_PRESENT | _PAGE_NO_CACHE
692 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
694 li r11, RPN_PATTERN
695 mtspr SPRN_DAR, r11 /* Tag DAR */
696 mfspr r3, SPRN_SPRG_SCRATCH2
697 EXCEPTION_EPILOG_0
698 rfi
700 DTLBMissLinear:
701 mtcr r3
702 /* Set 8M byte page and mark it valid */
703 li r11, MD_PS8MEG | MD_SVALID
704 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
705 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
706 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
707 _PAGE_PRESENT
708 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
710 li r11, RPN_PATTERN
711 mtspr SPRN_DAR, r11 /* Tag DAR */
712 mfspr r3, SPRN_SPRG_SCRATCH2
713 EXCEPTION_EPILOG_0
714 rfi
716 #ifndef CONFIG_PIN_TLB_TEXT
717 ITLBMissLinear:
718 mtcr r3
719 /* Set 8M byte page and mark it valid */
720 li r11, MI_PS8MEG | MI_SVALID | _PAGE_EXEC
721 MTSPR_CPU6(SPRN_MI_TWC, r11, r3)
722 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
723 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
724 _PAGE_PRESENT
725 MTSPR_CPU6(SPRN_MI_RPN, r10, r11) /* Update TLB entry */
727 mfspr r3, SPRN_SPRG_SCRATCH2
728 EXCEPTION_EPILOG_0
729 rfi
730 #endif
732 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
733 * by decoding the registers used by the dcbx instruction and adding them.
734 * DAR is set to the calculated address.
735 */
736 /* define if you don't want to use self modifying code */
737 #define NO_SELF_MODIFYING_CODE
738 FixupDAR:/* Entry point for dcbx workaround. */
739 mtspr SPRN_SPRG_SCRATCH2, r10
740 /* fetch instruction from memory. */
741 mfspr r10, SPRN_SRR0
742 rlwinm r11, r10, 16, 0xfff8
743 cmpli cr0, r11, PAGE_OFFSET@h
744 mfspr r11, SPRN_M_TW /* Get level 1 table */
745 blt+ 3f
746 rlwinm r11, r10, 16, 0xfff8
747 _ENTRY(FixupDAR_cmp)
748 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
749 /* create physical page address from effective address */
750 tophys(r11, r10)
751 blt- cr7, 201f
752 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
753 /* Insert level 1 index */
754 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
755 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
756 mtcr r11
757 bt 28,200f /* bit 28 = Large page (8M) */
758 bt 29,202f /* bit 29 = Large page (8M or 512K) */
759 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
760 /* Insert level 2 index */
761 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
762 lwz r11, 0(r11) /* Get the pte */
763 /* concat physical page address(r11) and page offset(r10) */
764 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
765 201: lwz r11,0(r11)
766 /* Check if it really is a dcbx instruction. */
767 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
768 * no need to include them here */
769 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
770 rlwinm r10, r10, 0, 21, 5
771 cmpwi cr0, r10, 2028 /* Is dcbz? */
772 beq+ 142f
773 cmpwi cr0, r10, 940 /* Is dcbi? */
774 beq+ 142f
775 cmpwi cr0, r10, 108 /* Is dcbst? */
776 beq+ 144f /* Fix up store bit! */
777 cmpwi cr0, r10, 172 /* Is dcbf? */
778 beq+ 142f
779 cmpwi cr0, r10, 1964 /* Is icbi? */
780 beq+ 142f
781 141: mfspr r10,SPRN_SPRG_SCRATCH2
782 b DARFixed /* Nope, go back to normal TLB processing */
784 /* concat physical page address(r11) and page offset(r10) */
785 200:
786 #ifdef CONFIG_PPC_16K_PAGES
787 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
788 rlwimi r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
789 #else
790 rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK
791 #endif
792 lwz r11, 0(r11) /* Get the pte */
793 /* concat physical page address(r11) and page offset(r10) */
794 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
795 b 201b
797 202:
798 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
799 rlwimi r11, r10, 32 - (PAGE_SHIFT_512K - 2), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
800 lwz r11, 0(r11) /* Get the pte */
801 /* concat physical page address(r11) and page offset(r10) */
802 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
803 b 201b
805 144: mfspr r10, SPRN_DSISR
806 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
807 mtspr SPRN_DSISR, r10
808 142: /* continue, it was a dcbx, dcbi instruction. */
809 #ifndef NO_SELF_MODIFYING_CODE
810 andis. r10,r11,0x1f /* test if reg RA is r0 */
811 li r10,modified_instr@l
812 dcbtst r0,r10 /* touch for store */
813 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
814 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
815 ori r11,r11,532
816 stw r11,0(r10) /* store add/and instruction */
817 dcbf 0,r10 /* flush new instr. to memory. */
818 icbi 0,r10 /* invalidate instr. cache line */
819 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
820 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
821 isync /* Wait until new instr is loaded from memory */
822 modified_instr:
823 .space 4 /* this is where the add instr. is stored */
824 bne+ 143f
825 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
826 143: mtdar r10 /* store faulting EA in DAR */
827 mfspr r10,SPRN_SPRG_SCRATCH2
828 b DARFixed /* Go back to normal TLB handling */
829 #else
830 mfctr r10
831 mtdar r10 /* save ctr reg in DAR */
832 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
833 addi r10, r10, 150f@l /* add start of table */
834 mtctr r10 /* load ctr with jump address */
835 xor r10, r10, r10 /* sum starts at zero */
836 bctr /* jump into table */
837 150:
838 add r10, r10, r0 ;b 151f
839 add r10, r10, r1 ;b 151f
840 add r10, r10, r2 ;b 151f
841 add r10, r10, r3 ;b 151f
842 add r10, r10, r4 ;b 151f
843 add r10, r10, r5 ;b 151f
844 add r10, r10, r6 ;b 151f
845 add r10, r10, r7 ;b 151f
846 add r10, r10, r8 ;b 151f
847 add r10, r10, r9 ;b 151f
848 mtctr r11 ;b 154f /* r10 needs special handling */
849 mtctr r11 ;b 153f /* r11 needs special handling */
850 add r10, r10, r12 ;b 151f
851 add r10, r10, r13 ;b 151f
852 add r10, r10, r14 ;b 151f
853 add r10, r10, r15 ;b 151f
854 add r10, r10, r16 ;b 151f
855 add r10, r10, r17 ;b 151f
856 add r10, r10, r18 ;b 151f
857 add r10, r10, r19 ;b 151f
858 add r10, r10, r20 ;b 151f
859 add r10, r10, r21 ;b 151f
860 add r10, r10, r22 ;b 151f
861 add r10, r10, r23 ;b 151f
862 add r10, r10, r24 ;b 151f
863 add r10, r10, r25 ;b 151f
864 add r10, r10, r26 ;b 151f
865 add r10, r10, r27 ;b 151f
866 add r10, r10, r28 ;b 151f
867 add r10, r10, r29 ;b 151f
868 add r10, r10, r30 ;b 151f
869 add r10, r10, r31
870 151:
871 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
872 beq 152f /* if reg RA is zero, don't add it */
873 addi r11, r11, 150b@l /* add start of table */
874 mtctr r11 /* load ctr with jump address */
875 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
876 bctr /* jump into table */
877 152:
878 mfdar r11
879 mtctr r11 /* restore ctr reg from DAR */
880 mtdar r10 /* save fault EA to DAR */
881 mfspr r10,SPRN_SPRG_SCRATCH2
882 b DARFixed /* Go back to normal TLB handling */
884 /* special handling for r10,r11 since these are modified already */
885 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
886 add r10, r10, r11 /* add it */
887 mfctr r11 /* restore r11 */
888 b 151b
889 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
890 add r10, r10, r11 /* add it */
891 mfctr r11 /* restore r11 */
892 b 151b
893 #endif
895 /*
896 * This is where the main kernel code starts.
897 */
898 start_here:
899 /* ptr to current */
900 lis r2,init_task@h
901 ori r2,r2,init_task@l
903 /* ptr to phys current thread */
904 tophys(r4,r2)
905 addi r4,r4,THREAD /* init task's THREAD */
906 mtspr SPRN_SPRG_THREAD,r4
908 /* stack */
909 lis r1,init_thread_union@ha
910 addi r1,r1,init_thread_union@l
911 li r0,0
912 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
914 bl early_init /* We have to do this with MMU on */
916 /*
917 * Decide what sort of machine this is and initialize the MMU.
918 */
919 li r3,0
920 mr r4,r31
921 bl machine_init
922 bl MMU_init
924 /*
925 * Go back to running unmapped so we can load up new values
926 * and change to using our exception vectors.
927 * On the 8xx, all we have to do is invalidate the TLB to clear
928 * the old 8M byte TLB mappings and load the page table base register.
929 */
930 /* The right way to do this would be to track it down through
931 * init's THREAD like the context switch code does, but this is
932 * easier......until someone changes init's static structures.
933 */
934 lis r6, swapper_pg_dir@ha
935 tophys(r6,r6)
936 #ifdef CONFIG_8xx_CPU6
937 lis r4, cpu6_errata_word@h
938 ori r4, r4, cpu6_errata_word@l
939 li r3, 0x3f80
940 stw r3, 12(r4)
941 lwz r3, 12(r4)
942 #endif
943 mtspr SPRN_M_TW, r6
944 lis r4,2f@h
945 ori r4,r4,2f@l
946 tophys(r4,r4)
947 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
948 mtspr SPRN_SRR0,r4
949 mtspr SPRN_SRR1,r3
950 rfi
951 /* Load up the kernel context */
952 2:
953 tlbia /* Clear all TLB entries */
954 sync /* wait for tlbia/tlbie to finish */
956 /* set up the PTE pointers for the Abatron bdiGDB.
957 */
958 tovirt(r6,r6)
959 lis r5, abatron_pteptrs@h
960 ori r5, r5, abatron_pteptrs@l
961 stw r5, 0xf0(r0) /* Must match your Abatron config file */
962 tophys(r5,r5)
963 stw r6, 0(r5)
965 /* Now turn on the MMU for real! */
966 li r4,MSR_KERNEL
967 lis r3,start_kernel@h
968 ori r3,r3,start_kernel@l
969 mtspr SPRN_SRR0,r3
970 mtspr SPRN_SRR1,r4
971 rfi /* enable MMU and jump to start_kernel */
973 /* Set up the initial MMU state so we can do the first level of
974 * kernel initialization. This maps the first 8 MBytes of memory 1:1
975 * virtual to physical. Also, set the cache mode since that is defined
976 * by TLB entries and perform any additional mapping (like of the IMMR).
977 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
978 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
979 * these mappings is mapped by page tables.
980 */
981 initial_mmu:
982 li r8, 0
983 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
984 lis r10, MD_RESETVAL@h
985 #ifndef CONFIG_8xx_COPYBACK
986 oris r10, r10, MD_WTDEF@h
987 #endif
988 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
990 tlbia /* Invalidate all TLB entries */
991 #ifdef CONFIG_PIN_TLB_TEXT
992 lis r8, MI_RSV4I@h
993 ori r8, r8, 0x1c00
995 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
996 #endif
998 #ifdef CONFIG_PIN_TLB_DATA
999 oris r10, r10, MD_RSV4I@h
1000 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
1001 #endif
1003 /* Now map the lower 8 Meg into the ITLB. */
1004 lis r8, KERNELBASE@h /* Create vaddr for TLB */
1005 ori r8, r8, MI_EVALID /* Mark it valid */
1006 mtspr SPRN_MI_EPN, r8
1007 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */
1008 ori r8, r8, MI_SVALID /* Make it valid */
1009 mtspr SPRN_MI_TWC, r8
1010 li r8, MI_BOOTINIT /* Create RPN for address 0 */
1011 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
1013 lis r8, MI_APG_INIT@h /* Set protection modes */
1014 ori r8, r8, MI_APG_INIT@l
1015 mtspr SPRN_MI_AP, r8
1016 lis r8, MD_APG_INIT@h
1017 ori r8, r8, MD_APG_INIT@l
1018 mtspr SPRN_MD_AP, r8
1020 /* Map a 512k page for the IMMR to get the processor
1021 * internal registers (among other things).
1022 */
1023 #ifdef CONFIG_PIN_TLB_IMMR
1024 oris r10, r10, MD_RSV4I@h
1025 ori r10, r10, 0x1c00
1026 mtspr SPRN_MD_CTR, r10
1028 mfspr r9, 638 /* Get current IMMR */
1029 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
1031 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
1032 ori r8, r8, MD_EVALID /* Mark it valid */
1033 mtspr SPRN_MD_EPN, r8
1034 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
1035 ori r8, r8, MD_SVALID /* Make it valid */
1036 mtspr SPRN_MD_TWC, r8
1037 mr r8, r9 /* Create paddr for TLB */
1038 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
1039 mtspr SPRN_MD_RPN, r8
1040 #endif
1042 /* Since the cache is enabled according to the information we
1043 * just loaded into the TLB, invalidate and enable the caches here.
1044 * We should probably check/set other modes....later.
1045 */
1046 lis r8, IDC_INVALL@h
1047 mtspr SPRN_IC_CST, r8
1048 mtspr SPRN_DC_CST, r8
1049 lis r8, IDC_ENABLE@h
1050 mtspr SPRN_IC_CST, r8
1051 #ifdef CONFIG_8xx_COPYBACK
1052 mtspr SPRN_DC_CST, r8
1053 #else
1054 /* For a debug option, I left this here to easily enable
1055 * the write through cache mode
1056 */
1057 lis r8, DC_SFWT@h
1058 mtspr SPRN_DC_CST, r8
1059 lis r8, IDC_ENABLE@h
1060 mtspr SPRN_DC_CST, r8
1061 #endif
1062 /* Disable debug mode entry on breakpoints */
1063 mfspr r8, SPRN_DER
1064 #ifdef CONFIG_PPC_8xx_PERF_EVENT
1065 rlwinm r8, r8, 0, ~0xc
1066 #else
1067 rlwinm r8, r8, 0, ~0x8
1068 #endif
1069 mtspr SPRN_DER, r8
1070 blr
1073 /*
1074 * We put a few things here that have to be page-aligned.
1075 * This stuff goes at the beginning of the data segment,
1076 * which is page-aligned.
1077 */
1078 .data
1079 .globl sdata
1080 sdata:
1081 .globl empty_zero_page
1082 .align PAGE_SHIFT
1083 empty_zero_page:
1084 .space PAGE_SIZE
1085 EXPORT_SYMBOL(empty_zero_page)
1087 .globl swapper_pg_dir
1088 swapper_pg_dir:
1089 .space PGD_TABLE_SIZE
1091 /* Room for two PTE table poiners, usually the kernel and current user
1092 * pointer to their respective root page table (pgdir).
1093 */
1094 abatron_pteptrs:
1095 .space 8
1097 #ifdef CONFIG_8xx_CPU6
1098 .globl cpu6_errata_word
1099 cpu6_errata_word:
1100 .space 16
1101 #endif
1103 #ifdef CONFIG_PPC_8xx_PERF_EVENT
1104 .globl itlb_miss_counter
1105 itlb_miss_counter:
1106 .space 4
1108 .globl dtlb_miss_counter
1109 dtlb_miss_counter:
1110 .space 4
1112 .globl instruction_counter
1113 instruction_counter:
1114 .space 4
1115 #endif