arch/powerpc/platforms/83xx/mpc836x_mds.c

   1 /*
   2  * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
   3  *
   4  * Author: Li Yang <LeoLi@freescale.com>
   5  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   6  *
   7  * Description:
   8  * MPC8360E MDS board specific routines.
   9  *
  10  * Changelog:
  11  * Jun 21, 2006 Initial version
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/compiler.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/reboot.h>
  25 #include <linux/pci.h>
  26 #include <linux/kdev_t.h>
  27 #include <linux/major.h>
  28 #include <linux/console.h>
  29 #include <linux/delay.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/root_dev.h>
  32 #include <linux/initrd.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/of_device.h>
  35
  36 #include <linux/atomic.h>
  37 #include <asm/time.h>
  38 #include <asm/io.h>
  39 #include <asm/machdep.h>
  40 #include <asm/ipic.h>
  41 #include <asm/irq.h>
  42 #include <asm/prom.h>
  43 #include <asm/udbg.h>
  44 #include <sysdev/fsl_soc.h>
  45 #include <sysdev/fsl_pci.h>
  46 #include <sysdev/simple_gpio.h>
  47 #include <soc/fsl/qe/qe.h>
  48 #include <soc/fsl/qe/qe_ic.h>
  49
  50 #include "mpc83xx.h"
  51
  52 #undef DEBUG
  53 #ifdef DEBUG
  54 #define DBG(fmt...) udbg_printf(fmt)
  55 #else
  56 #define DBG(fmt...)
  57 #endif
  58
  59 /* ************************************************************************
  60  *
  61  * Setup the architecture
  62  *
  63  */
  64 static void __init mpc836x_mds_setup_arch(void)
  65 {
  66         struct device_node *np;
  67         u8 __iomem *bcsr_regs = NULL;
  68
  69         mpc83xx_setup_arch();
  70
  71         /* Map BCSR area */
  72         np = of_find_node_by_name(NULL, "bcsr");
  73         if (np) {
  74                 struct resource res;
  75
  76                 of_address_to_resource(np, 0, &res);
  77                 bcsr_regs = ioremap(res.start, resource_size(&res));
  78                 of_node_put(np);
  79         }
  80
  81 #ifdef CONFIG_QUICC_ENGINE
  82         if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  83                 par_io_init(np);
  84                 of_node_put(np);
  85
  86                 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  87                         par_io_of_config(np);
  88 #ifdef CONFIG_QE_USB
  89                 /* Must fixup Par IO before QE GPIO chips are registered. */
  90                 par_io_config_pin(1,  2, 1, 0, 3, 0); /* USBOE  */
  91                 par_io_config_pin(1,  3, 1, 0, 3, 0); /* USBTP  */
  92                 par_io_config_pin(1,  8, 1, 0, 1, 0); /* USBTN  */
  93                 par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
  94                 par_io_config_pin(1,  9, 2, 1, 3, 0); /* USBRP  */
  95                 par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN  */
  96                 par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21  */
  97 #endif /* CONFIG_QE_USB */
  98         }
  99
 100         if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
 101                         != NULL){
 102                 uint svid;
 103
 104                 /* Reset the Ethernet PHY */
 105 #define BCSR9_GETHRST 0x20
 106                 clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
 107                 udelay(1000);
 108                 setbits8(&bcsr_regs[9], BCSR9_GETHRST);
 109
 110                 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
 111                 svid = mfspr(SPRN_SVR);
 112                 if (svid == 0x80480021) {
 113                         void __iomem *immap;
 114
 115                         immap = ioremap(get_immrbase() + 0x14a8, 8);
 116
 117                         /*
 118                          * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
 119                          * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
 120                          */
 121                         setbits32(immap, 0x0c003000);
 122
 123                         /*
 124                          * IMMR + 0x14AC[20:27] = 10101010
 125                          * (data delay for both UCC's)
 126                          */
 127                         clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
 128
 129                         iounmap(immap);
 130                 }
 131
 132                 iounmap(bcsr_regs);
 133                 of_node_put(np);
 134         }
 135 #endif                          /* CONFIG_QUICC_ENGINE */
 136 }
 137
 138 machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
 139
 140 #ifdef CONFIG_QE_USB
 141 static int __init mpc836x_usb_cfg(void)
 142 {
 143         u8 __iomem *bcsr;
 144         struct device_node *np;
 145         const char *mode;
 146         int ret = 0;
 147
 148         np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
 149         if (!np)
 150                 return -ENODEV;
 151
 152         bcsr = of_iomap(np, 0);
 153         of_node_put(np);
 154         if (!bcsr)
 155                 return -ENOMEM;
 156
 157         np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
 158         if (!np) {
 159                 ret = -ENODEV;
 160                 goto err;
 161         }
 162
 163 #define BCSR8_TSEC1M_MASK       (0x3 << 6)
 164 #define BCSR8_TSEC1M_RGMII      (0x0 << 6)
 165 #define BCSR8_TSEC2M_MASK       (0x3 << 4)
 166 #define BCSR8_TSEC2M_RGMII      (0x0 << 4)
 167         /*
 168          * Default is GMII (2), but we should set it to RGMII (0) if we use
 169          * USB (Eth PHY is in RGMII mode anyway).
 170          */
 171         clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
 172                                BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
 173
 174 #define BCSR13_USBMASK  0x0f
 175 #define BCSR13_nUSBEN   0x08 /* 1 - Disable, 0 - Enable                 */
 176 #define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low                       */
 177 #define BCSR13_USBMODE  0x02 /* 1 - Host, 0 - Function                  */
 178 #define BCSR13_nUSBVCC  0x01 /* 1 - gets VBUS, 0 - supplies VBUS        */
 179
 180         clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
 181
 182         mode = of_get_property(np, "mode", NULL);
 183         if (mode && !strcmp(mode, "peripheral")) {
 184                 setbits8(&bcsr[13], BCSR13_nUSBVCC);
 185                 qe_usb_clock_set(QE_CLK21, 48000000);
 186         } else {
 187                 setbits8(&bcsr[13], BCSR13_USBMODE);
 188                 /*
 189                  * The BCSR GPIOs are used to control power and
 190                  * speed of the USB transceiver. This is needed for
 191                  * the USB Host only.
 192                  */
 193                 simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
 194         }
 195
 196         of_node_put(np);
 197 err:
 198         iounmap(bcsr);
 199         return ret;
 200 }
 201 machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
 202 #endif /* CONFIG_QE_USB */
 203
 204 /*
 205  * Called very early, MMU is off, device-tree isn't unflattened
 206  */
 207 static int __init mpc836x_mds_probe(void)
 208 {
 209         return of_machine_is_compatible("MPC836xMDS");
 210 }
 211
 212 define_machine(mpc836x_mds) {
 213         .name           = "MPC836x MDS",
 214         .probe          = mpc836x_mds_probe,
 215         .setup_arch     = mpc836x_mds_setup_arch,
 216         .init_IRQ       = mpc83xx_ipic_and_qe_init_IRQ,
 217         .get_irq        = ipic_get_irq,
 218         .restart        = mpc83xx_restart,
 219         .time_init      = mpc83xx_time_init,
 220         .calibrate_decr = generic_calibrate_decr,
 221         .progress       = udbg_progress,
 222 };