2 * linux/arch/arm/mach-mmp/pxa168.c
4 * Code specific to PXA168
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/list.h>
16 #include <linux/clk.h>
18 #include <asm/mach/time.h>
19 #include <mach/addr-map.h>
20 #include <mach/cputype.h>
21 #include <mach/regs-apbc.h>
22 #include <mach/irqs.h>
23 #include <mach/gpio.h>
25 #include <mach/devices.h>
31 #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
33 static struct mfp_addr_map pxa168_mfp_addr_map
[] __initdata
=
35 MFP_ADDR_X(GPIO0
, GPIO36
, 0x04c),
36 MFP_ADDR_X(GPIO37
, GPIO55
, 0x000),
37 MFP_ADDR_X(GPIO56
, GPIO123
, 0x0e0),
38 MFP_ADDR_X(GPIO124
, GPIO127
, 0x0f4),
43 #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
45 static void __init
pxa168_init_gpio(void)
49 /* enable GPIO clock */
50 __raw_writel(APBC_APBCLK
| APBC_FNCLK
, APBC_PXA168_GPIO
);
52 /* unmask GPIO edge detection for all 4 banks - APMASKx */
53 for (i
= 0; i
< 4; i
++)
54 __raw_writel(0xffffffff, APMASK(i
));
56 pxa_init_gpio(IRQ_PXA168_GPIOX
, 0, 127, NULL
);
59 void __init
pxa168_init_irq(void)
65 /* APB peripheral clocks */
66 static APBC_CLK(uart1
, PXA168_UART1
, 1, 14745600);
67 static APBC_CLK(uart2
, PXA168_UART2
, 1, 14745600);
68 static APBC_CLK(twsi0
, PXA168_TWSI0
, 1, 33000000);
69 static APBC_CLK(twsi1
, PXA168_TWSI1
, 1, 33000000);
70 static APBC_CLK(pwm1
, PXA168_PWM1
, 1, 13000000);
71 static APBC_CLK(pwm2
, PXA168_PWM2
, 1, 13000000);
72 static APBC_CLK(pwm3
, PXA168_PWM3
, 1, 13000000);
73 static APBC_CLK(pwm4
, PXA168_PWM4
, 1, 13000000);
75 /* device and clock bindings */
76 static struct clk_lookup pxa168_clkregs
[] = {
77 INIT_CLKREG(&clk_uart1
, "pxa2xx-uart.0", NULL
),
78 INIT_CLKREG(&clk_uart2
, "pxa2xx-uart.1", NULL
),
79 INIT_CLKREG(&clk_twsi0
, "pxa2xx-i2c.0", NULL
),
80 INIT_CLKREG(&clk_twsi1
, "pxa2xx-i2c.1", NULL
),
81 INIT_CLKREG(&clk_pwm1
, "pxa168-pwm.0", NULL
),
82 INIT_CLKREG(&clk_pwm2
, "pxa168-pwm.1", NULL
),
83 INIT_CLKREG(&clk_pwm3
, "pxa168-pwm.2", NULL
),
84 INIT_CLKREG(&clk_pwm4
, "pxa168-pwm.3", NULL
),
87 static int __init
pxa168_init(void)
89 if (cpu_is_pxa168()) {
90 mfp_init_base(MFPR_VIRT_BASE
);
91 mfp_init_addr(pxa168_mfp_addr_map
);
92 pxa_init_dma(IRQ_PXA168_DMA_INT0
, 32);
93 clks_register(ARRAY_AND_SIZE(pxa168_clkregs
));
98 postcore_initcall(pxa168_init
);
100 /* system timer - clock enabled, 3.25MHz */
101 #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
103 static void __init
pxa168_timer_init(void)
105 /* this is early, we have to initialize the CCU registers by
106 * ourselves instead of using clk_* API. Clock rate is defined
107 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
109 __raw_writel(APBC_APBCLK
| APBC_RST
, APBC_PXA168_TIMERS
);
111 /* 3.25MHz, bus/functional clock enabled, release reset */
112 __raw_writel(TIMER_CLK_RST
, APBC_PXA168_TIMERS
);
114 timer_init(IRQ_PXA168_TIMER1
);
117 struct sys_timer pxa168_timer
= {
118 .init
= pxa168_timer_init
,
121 /* on-chip devices */
122 PXA168_DEVICE(uart1
, "pxa2xx-uart", 0, UART1
, 0xd4017000, 0x30, 21, 22);
123 PXA168_DEVICE(uart2
, "pxa2xx-uart", 1, UART2
, 0xd4018000, 0x30, 23, 24);
124 PXA168_DEVICE(twsi0
, "pxa2xx-i2c", 0, TWSI0
, 0xd4011000, 0x28);
125 PXA168_DEVICE(twsi1
, "pxa2xx-i2c", 1, TWSI1
, 0xd4025000, 0x28);
126 PXA168_DEVICE(pwm1
, "pxa168-pwm", 0, NONE
, 0xd401a000, 0x10);
127 PXA168_DEVICE(pwm2
, "pxa168-pwm", 1, NONE
, 0xd401a400, 0x10);
128 PXA168_DEVICE(pwm3
, "pxa168-pwm", 2, NONE
, 0xd401a800, 0x10);
129 PXA168_DEVICE(pwm4
, "pxa168-pwm", 3, NONE
, 0xd401ac00, 0x10);