arch/arm/plat-mxc/irq.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <mach/common.h>
  24 #include <asm/mach/irq.h>
  25 #include <mach/hardware.h>
  26
  27 #define AVIC_INTCNTL            0x00    /* int control reg */
  28 #define AVIC_NIMASK             0x04    /* int mask reg */
  29 #define AVIC_INTENNUM           0x08    /* int enable number reg */
  30 #define AVIC_INTDISNUM          0x0C    /* int disable number reg */
  31 #define AVIC_INTENABLEH         0x10    /* int enable reg high */
  32 #define AVIC_INTENABLEL         0x14    /* int enable reg low */
  33 #define AVIC_INTTYPEH           0x18    /* int type reg high */
  34 #define AVIC_INTTYPEL           0x1C    /* int type reg low */
  35 #define AVIC_NIPRIORITY(x)      (0x20 + 4 * (7 - (x))) /* int priority */
  36 #define AVIC_NIVECSR            0x40    /* norm int vector/status */
  37 #define AVIC_FIVECSR            0x44    /* fast int vector/status */
  38 #define AVIC_INTSRCH            0x48    /* int source reg high */
  39 #define AVIC_INTSRCL            0x4C    /* int source reg low */
  40 #define AVIC_INTFRCH            0x50    /* int force reg high */
  41 #define AVIC_INTFRCL            0x54    /* int force reg low */
  42 #define AVIC_NIPNDH             0x58    /* norm int pending high */
  43 #define AVIC_NIPNDL             0x5C    /* norm int pending low */
  44 #define AVIC_FIPNDH             0x60    /* fast int pending high */
  45 #define AVIC_FIPNDL             0x64    /* fast int pending low */
  46
  47 static void __iomem *avic_base;
  48
  49 int imx_irq_set_priority(unsigned char irq, unsigned char prio)
  50 {
  51 #ifdef CONFIG_MXC_IRQ_PRIOR
  52         unsigned int temp;
  53         unsigned int mask = 0x0F << irq % 8 * 4;
  54
  55         if (irq >= MXC_INTERNAL_IRQS)
  56                 return -EINVAL;;
  57
  58         temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
  59         temp &= ~mask;
  60         temp |= prio & mask;
  61
  62         __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
  63
  64         return 0;
  65 #else
  66         return -ENOSYS;
  67 #endif
  68 }
  69 EXPORT_SYMBOL(imx_irq_set_priority);
  70
  71 #ifdef CONFIG_FIQ
  72 int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
  73 {
  74         unsigned int irqt;
  75
  76         if (irq >= MXC_INTERNAL_IRQS)
  77                 return -EINVAL;
  78
  79         if (irq < MXC_INTERNAL_IRQS / 2) {
  80                 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
  81                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
  82         } else {
  83                 irq -= MXC_INTERNAL_IRQS / 2;
  84                 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
  85                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
  86         }
  87
  88         return 0;
  89 }
  90 EXPORT_SYMBOL(mxc_set_irq_fiq);
  91 #endif /* CONFIG_FIQ */
  92
  93 /* Disable interrupt number "irq" in the AVIC */
  94 static void mxc_mask_irq(unsigned int irq)
  95 {
  96         __raw_writel(irq, avic_base + AVIC_INTDISNUM);
  97 }
  98
  99 /* Enable interrupt number "irq" in the AVIC */
 100 static void mxc_unmask_irq(unsigned int irq)
 101 {
 102         __raw_writel(irq, avic_base + AVIC_INTENNUM);
 103 }
 104
 105 static struct irq_chip mxc_avic_chip = {
 106         .ack = mxc_mask_irq,
 107         .mask = mxc_mask_irq,
 108         .unmask = mxc_unmask_irq,
 109 };
 110
 111 /*
 112  * This function initializes the AVIC hardware and disables all the
 113  * interrupts. It registers the interrupt enable and disable functions
 114  * to the kernel for each interrupt source.
 115  */
 116 void __init mxc_init_irq(void)
 117 {
 118         int i;
 119
 120         avic_base = IO_ADDRESS(AVIC_BASE_ADDR);
 121
 122         /* put the AVIC into the reset value with
 123          * all interrupts disabled
 124          */
 125         __raw_writel(0, avic_base + AVIC_INTCNTL);
 126         __raw_writel(0x1f, avic_base + AVIC_NIMASK);
 127
 128         /* disable all interrupts */
 129         __raw_writel(0, avic_base + AVIC_INTENABLEH);
 130         __raw_writel(0, avic_base + AVIC_INTENABLEL);
 131
 132         /* all IRQ no FIQ */
 133         __raw_writel(0, avic_base + AVIC_INTTYPEH);
 134         __raw_writel(0, avic_base + AVIC_INTTYPEL);
 135         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
 136                 set_irq_chip(i, &mxc_avic_chip);
 137                 set_irq_handler(i, handle_level_irq);
 138                 set_irq_flags(i, IRQF_VALID);
 139         }
 140
 141         /* Set default priority value (0) for all IRQ's */
 142         for (i = 0; i < 8; i++)
 143                 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 144
 145         /* init architectures chained interrupt handler */
 146         mxc_register_gpios();
 147
 148 #ifdef CONFIG_FIQ
 149         /* Initialize FIQ */
 150         init_FIQ();
 151 #endif
 152
 153         printk(KERN_INFO "MXC IRQ initialized\n");
 154 }
 155