arch/blackfin/mach-bf527/include/mach/anomaly.h

   1 /*
   2  * File: include/asm-blackfin/mach-bf527/anomaly.h
   3  * Bugs: Enter bugs at http://blackfin.uclinux.org/
   4  *
   5  * Copyright (C) 2004-2009 Analog Devices Inc.
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 /* This file should be up to date with:
  10  *  - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List
  11  *  - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
  12  */
  13
  14 #ifndef _MACH_ANOMALY_H_
  15 #define _MACH_ANOMALY_H_
  16
  17 /* We do not support old silicon - sorry */
  18 #if __SILICON_REVISION__ < 0
  19 # error will not work on BF526/BF527 silicon version
  20 #endif
  21
  22 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
  23 # define ANOMALY_BF526 1
  24 #else
  25 # define ANOMALY_BF526 0
  26 #endif
  27 #if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
  28 # define ANOMALY_BF527 1
  29 #else
  30 # define ANOMALY_BF527 0
  31 #endif
  32
  33 #define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
  34 #define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
  35 #define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
  36
  37 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
  38 #define ANOMALY_05000074 (1)
  39 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
  40 #define ANOMALY_05000119 (1)    /* note: brokenness is noted in documentation, not anomaly sheet */
  41 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
  42 #define ANOMALY_05000122 (1)
  43 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
  44 #define ANOMALY_05000245 (1)
  45 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
  46 #define ANOMALY_05000254 (1)
  47 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
  48 #define ANOMALY_05000265 (1)
  49 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
  50 #define ANOMALY_05000310 (1)
  51 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
  52 #define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
  53 /* Incorrect Access of OTP_STATUS During otp_write() Function */
  54 #define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
  55 /* Host DMA Boot Modes Are Not Functional */
  56 #define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
  57 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
  58 #define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
  59 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
  60 #define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
  61 /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
  62 #define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
  63 /* USB Calibration Value Is Not Initialized */
  64 #define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
  65 /* USB Calibration Value to use */
  66 #define ANOMALY_05000346_value 0xE510
  67 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */
  68 #define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
  69 /* Security Features Are Not Functional */
  70 #define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
  71 /* bfrom_SysControl() Firmware Function Performs Improper System Reset */
  72 #define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
  73 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
  74 #define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
  75 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
  76 #define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
  77 /* Incorrect Revision Number in DSPID Register */
  78 #define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
  79 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
  80 #define ANOMALY_05000366 (1)
  81 /* Incorrect Default CSEL Value in PLL_DIV */
  82 #define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
  83 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
  84 #define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
  85 /* Authentication Fails To Initiate */
  86 #define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
  87 /* Data Read From L3 Memory by USB DMA May be Corrupted */
  88 #define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
  89 /* 8-Bit NAND Flash Boot Mode Not Functional */
  90 #define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
  91 /* Boot from OTP Memory Not Functional */
  92 #define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
  93 /* bfrom_SysControl() Firmware Routine Not Functional */
  94 #define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
  95 /* Programmable Preboot Settings Not Functional */
  96 #define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
  97 /* CRC32 Checksum Support Not Functional */
  98 #define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
  99 /* Reset Vector Must Not Be in SDRAM Memory Space */
 100 #define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
 101 /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
 102 #define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
 103 /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
 104 #define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
 105 /* Log Buffer Not Functional */
 106 #define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
 107 /* Hook Routine Not Functional */
 108 #define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
 109 /* Header Indirect Bit Not Functional */
 110 #define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
 111 /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
 112 #define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
 113 /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
 114 #define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
 115 /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
 116 #define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
 117 /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
 118 #define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
 119 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 120 #define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
 121 /* Lockbox SESR Disallows Certain User Interrupts */
 122 #define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
 123 /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
 124 #define ANOMALY_05000405 (1)
 125 /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
 126 #define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
 127 /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
 128 #define ANOMALY_05000408 (1)
 129 /* Lockbox firmware leaves MDMA0 channel enabled */
 130 #define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
 131 /* Incorrect Default Internal Voltage Regulator Setting */
 132 #define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
 133 /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
 134 #define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))
 135 /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
 136 #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
 137 /* DEB2_URGENT Bit Not Functional */
 138 #define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
 139 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
 140 #define ANOMALY_05000416 (1)
 141 /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
 142 #define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
 143 /* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
 144 #define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
 145 /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
 146 #define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
 147 /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
 148 #define ANOMALY_05000421 (1)
 149 /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
 150 #define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
 151 /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
 152 #define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
 153 /* Internal Voltage Regulator Not Trimmed */
 154 #define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
 155 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
 156 #define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
 157 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
 158 #define ANOMALY_05000426 (1)
 159 /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
 160 #define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
 161 /* Software System Reset Corrupts PLL_LOCKCNT Register */
 162 #define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
 163 /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
 164 #define ANOMALY_05000431 (1)
 165 /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
 166 #define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
 167 /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
 168 #define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
 169 /* Preboot Cannot be Used to Alter the PLL_DIV Register */
 170 #define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
 171 /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
 172 #define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
 173 /* OTP Write Accesses Not Supported */
 174 #define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
 175 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 176 #define ANOMALY_05000443 (1)
 177 /* The WURESET Bit in the SYSCR Register is not Functional */
 178 #define ANOMALY_05000445 (1)
 179 /* USB DMA Short Packet Data Corruption */
 180 #define ANOMALY_05000450 (1)
 181 /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
 182 #define ANOMALY_05000451 (1)
 183 /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
 184 #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
 185 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
 186 #define ANOMALY_05000456 (1)
 187 /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
 188 #define ANOMALY_05000457 (1)
 189 /* False Hardware Error when RETI Points to Invalid Memory */
 190 #define ANOMALY_05000461 (1)
 191 /* USB Rx DMA hang */
 192 #define ANOMALY_05000465 (1)
 193 /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
 194 #define ANOMALY_05000467 (1)
 195
 196 /* Anomalies that don't exist on this proc */
 197 #define ANOMALY_05000099 (0)
 198 #define ANOMALY_05000120 (0)
 199 #define ANOMALY_05000125 (0)
 200 #define ANOMALY_05000149 (0)
 201 #define ANOMALY_05000158 (0)
 202 #define ANOMALY_05000171 (0)
 203 #define ANOMALY_05000179 (0)
 204 #define ANOMALY_05000182 (0)
 205 #define ANOMALY_05000183 (0)
 206 #define ANOMALY_05000189 (0)
 207 #define ANOMALY_05000198 (0)
 208 #define ANOMALY_05000202 (0)
 209 #define ANOMALY_05000215 (0)
 210 #define ANOMALY_05000220 (0)
 211 #define ANOMALY_05000227 (0)
 212 #define ANOMALY_05000230 (0)
 213 #define ANOMALY_05000231 (0)
 214 #define ANOMALY_05000233 (0)
 215 #define ANOMALY_05000234 (0)
 216 #define ANOMALY_05000242 (0)
 217 #define ANOMALY_05000244 (0)
 218 #define ANOMALY_05000248 (0)
 219 #define ANOMALY_05000250 (0)
 220 #define ANOMALY_05000257 (0)
 221 #define ANOMALY_05000261 (0)
 222 #define ANOMALY_05000263 (0)
 223 #define ANOMALY_05000266 (0)
 224 #define ANOMALY_05000273 (0)
 225 #define ANOMALY_05000274 (0)
 226 #define ANOMALY_05000278 (0)
 227 #define ANOMALY_05000281 (0)
 228 #define ANOMALY_05000283 (0)
 229 #define ANOMALY_05000285 (0)
 230 #define ANOMALY_05000287 (0)
 231 #define ANOMALY_05000301 (0)
 232 #define ANOMALY_05000305 (0)
 233 #define ANOMALY_05000307 (0)
 234 #define ANOMALY_05000311 (0)
 235 #define ANOMALY_05000312 (0)
 236 #define ANOMALY_05000315 (0)
 237 #define ANOMALY_05000323 (0)
 238 #define ANOMALY_05000362 (1)
 239 #define ANOMALY_05000363 (0)
 240 #define ANOMALY_05000400 (0)
 241 #define ANOMALY_05000412 (0)
 242 #define ANOMALY_05000447 (0)
 243 #define ANOMALY_05000448 (0)
 244
 245 #endif