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hamradio/scc: add missing block braces to multi-statement if
[linux/fpc-iii.git] / drivers / s390 / net / qeth_core_main.c
blob436bf1f6d4a602935dd94776e95909a450737bc3
1 /*
2 * drivers/s390/net/qeth_core_main.c
3 *
4 * Copyright IBM Corp. 2007
5 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
6 * Frank Pavlic <fpavlic@de.ibm.com>,
7 * Thomas Spatzier <tspat@de.ibm.com>,
8 * Frank Blaschka <frank.blaschka@de.ibm.com>
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/string.h>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/ip.h>
17 #include <linux/ipv6.h>
18 #include <linux/tcp.h>
19 #include <linux/mii.h>
20 #include <linux/kthread.h>
21
22 #include <asm-s390/ebcdic.h>
23 #include <asm-s390/io.h>
24 #include <asm/s390_rdev.h>
25
26 #include "qeth_core.h"
27 #include "qeth_core_offl.h"
28
29 struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
30 /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
31 /* N P A M L V H */
32 [QETH_DBF_SETUP] = {"qeth_setup",
33 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
34 [QETH_DBF_QERR] = {"qeth_qerr",
35 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
36 [QETH_DBF_TRACE] = {"qeth_trace",
37 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
38 [QETH_DBF_MSG] = {"qeth_msg",
39 8, 1, 128, 3, &debug_sprintf_view, NULL},
40 [QETH_DBF_SENSE] = {"qeth_sense",
41 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
42 [QETH_DBF_MISC] = {"qeth_misc",
43 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
44 [QETH_DBF_CTRL] = {"qeth_control",
45 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
46 };
47 EXPORT_SYMBOL_GPL(qeth_dbf);
48
49 struct qeth_card_list_struct qeth_core_card_list;
50 EXPORT_SYMBOL_GPL(qeth_core_card_list);
51
52 static struct device *qeth_core_root_dev;
53 static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
54 static struct lock_class_key qdio_out_skb_queue_key;
55
56 static void qeth_send_control_data_cb(struct qeth_channel *,
57 struct qeth_cmd_buffer *);
58 static int qeth_issue_next_read(struct qeth_card *);
59 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
60 static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
61 static void qeth_free_buffer_pool(struct qeth_card *);
62 static int qeth_qdio_establish(struct qeth_card *);
63
64
65 static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
66 struct qdio_buffer *buffer, int is_tso,
67 int *next_element_to_fill)
68 {
69 struct skb_frag_struct *frag;
70 int fragno;
71 unsigned long addr;
72 int element, cnt, dlen;
73
74 fragno = skb_shinfo(skb)->nr_frags;
75 element = *next_element_to_fill;
76 dlen = 0;
77
78 if (is_tso)
79 buffer->element[element].flags =
80 SBAL_FLAGS_MIDDLE_FRAG;
81 else
82 buffer->element[element].flags =
83 SBAL_FLAGS_FIRST_FRAG;
84 dlen = skb->len - skb->data_len;
85 if (dlen) {
86 buffer->element[element].addr = skb->data;
87 buffer->element[element].length = dlen;
88 element++;
89 }
90 for (cnt = 0; cnt < fragno; cnt++) {
91 frag = &skb_shinfo(skb)->frags[cnt];
92 addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
93 frag->page_offset;
94 buffer->element[element].addr = (char *)addr;
95 buffer->element[element].length = frag->size;
96 if (cnt < (fragno - 1))
97 buffer->element[element].flags =
98 SBAL_FLAGS_MIDDLE_FRAG;
99 else
100 buffer->element[element].flags =
101 SBAL_FLAGS_LAST_FRAG;
102 element++;
103 }
104 *next_element_to_fill = element;
105 }
106
107 static inline const char *qeth_get_cardname(struct qeth_card *card)
108 {
109 if (card->info.guestlan) {
110 switch (card->info.type) {
111 case QETH_CARD_TYPE_OSAE:
112 return " Guest LAN QDIO";
113 case QETH_CARD_TYPE_IQD:
114 return " Guest LAN Hiper";
115 default:
116 return " unknown";
117 }
118 } else {
119 switch (card->info.type) {
120 case QETH_CARD_TYPE_OSAE:
121 return " OSD Express";
122 case QETH_CARD_TYPE_IQD:
123 return " HiperSockets";
124 case QETH_CARD_TYPE_OSN:
125 return " OSN QDIO";
126 default:
127 return " unknown";
128 }
129 }
130 return " n/a";
131 }
132
133 /* max length to be returned: 14 */
134 const char *qeth_get_cardname_short(struct qeth_card *card)
135 {
136 if (card->info.guestlan) {
137 switch (card->info.type) {
138 case QETH_CARD_TYPE_OSAE:
139 return "GuestLAN QDIO";
140 case QETH_CARD_TYPE_IQD:
141 return "GuestLAN Hiper";
142 default:
143 return "unknown";
144 }
145 } else {
146 switch (card->info.type) {
147 case QETH_CARD_TYPE_OSAE:
148 switch (card->info.link_type) {
149 case QETH_LINK_TYPE_FAST_ETH:
150 return "OSD_100";
151 case QETH_LINK_TYPE_HSTR:
152 return "HSTR";
153 case QETH_LINK_TYPE_GBIT_ETH:
154 return "OSD_1000";
155 case QETH_LINK_TYPE_10GBIT_ETH:
156 return "OSD_10GIG";
157 case QETH_LINK_TYPE_LANE_ETH100:
158 return "OSD_FE_LANE";
159 case QETH_LINK_TYPE_LANE_TR:
160 return "OSD_TR_LANE";
161 case QETH_LINK_TYPE_LANE_ETH1000:
162 return "OSD_GbE_LANE";
163 case QETH_LINK_TYPE_LANE:
164 return "OSD_ATM_LANE";
165 default:
166 return "OSD_Express";
167 }
168 case QETH_CARD_TYPE_IQD:
169 return "HiperSockets";
170 case QETH_CARD_TYPE_OSN:
171 return "OSN";
172 default:
173 return "unknown";
174 }
175 }
176 return "n/a";
177 }
178
179 void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
180 int clear_start_mask)
181 {
182 unsigned long flags;
183
184 spin_lock_irqsave(&card->thread_mask_lock, flags);
185 card->thread_allowed_mask = threads;
186 if (clear_start_mask)
187 card->thread_start_mask &= threads;
188 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
189 wake_up(&card->wait_q);
190 }
191 EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
192
193 int qeth_threads_running(struct qeth_card *card, unsigned long threads)
194 {
195 unsigned long flags;
196 int rc = 0;
197
198 spin_lock_irqsave(&card->thread_mask_lock, flags);
199 rc = (card->thread_running_mask & threads);
200 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
201 return rc;
202 }
203 EXPORT_SYMBOL_GPL(qeth_threads_running);
204
205 int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
206 {
207 return wait_event_interruptible(card->wait_q,
208 qeth_threads_running(card, threads) == 0);
209 }
210 EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
211
212 void qeth_clear_working_pool_list(struct qeth_card *card)
213 {
214 struct qeth_buffer_pool_entry *pool_entry, *tmp;
215
216 QETH_DBF_TEXT(TRACE, 5, "clwrklst");
217 list_for_each_entry_safe(pool_entry, tmp,
218 &card->qdio.in_buf_pool.entry_list, list){
219 list_del(&pool_entry->list);
220 }
221 }
222 EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
223
224 static int qeth_alloc_buffer_pool(struct qeth_card *card)
225 {
226 struct qeth_buffer_pool_entry *pool_entry;
227 void *ptr;
228 int i, j;
229
230 QETH_DBF_TEXT(TRACE, 5, "alocpool");
231 for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
232 pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
233 if (!pool_entry) {
234 qeth_free_buffer_pool(card);
235 return -ENOMEM;
236 }
237 for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
238 ptr = (void *) __get_free_page(GFP_KERNEL);
239 if (!ptr) {
240 while (j > 0)
241 free_page((unsigned long)
242 pool_entry->elements[--j]);
243 kfree(pool_entry);
244 qeth_free_buffer_pool(card);
245 return -ENOMEM;
246 }
247 pool_entry->elements[j] = ptr;
248 }
249 list_add(&pool_entry->init_list,
250 &card->qdio.init_pool.entry_list);
251 }
252 return 0;
253 }
254
255 int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
256 {
257 QETH_DBF_TEXT(TRACE, 2, "realcbp");
258
259 if ((card->state != CARD_STATE_DOWN) &&
260 (card->state != CARD_STATE_RECOVER))
261 return -EPERM;
262
263 /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
264 qeth_clear_working_pool_list(card);
265 qeth_free_buffer_pool(card);
266 card->qdio.in_buf_pool.buf_count = bufcnt;
267 card->qdio.init_pool.buf_count = bufcnt;
268 return qeth_alloc_buffer_pool(card);
269 }
270
271 int qeth_set_large_send(struct qeth_card *card,
272 enum qeth_large_send_types type)
273 {
274 int rc = 0;
275
276 if (card->dev == NULL) {
277 card->options.large_send = type;
278 return 0;
279 }
280 if (card->state == CARD_STATE_UP)
281 netif_tx_disable(card->dev);
282 card->options.large_send = type;
283 switch (card->options.large_send) {
284 case QETH_LARGE_SEND_EDDP:
285 card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
286 NETIF_F_HW_CSUM;
287 break;
288 case QETH_LARGE_SEND_TSO:
289 if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
290 card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
291 NETIF_F_HW_CSUM;
292 } else {
293 PRINT_WARN("TSO not supported on %s. "
294 "large_send set to 'no'.\n",
295 card->dev->name);
296 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
297 NETIF_F_HW_CSUM);
298 card->options.large_send = QETH_LARGE_SEND_NO;
299 rc = -EOPNOTSUPP;
300 }
301 break;
302 default: /* includes QETH_LARGE_SEND_NO */
303 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
304 NETIF_F_HW_CSUM);
305 break;
306 }
307 if (card->state == CARD_STATE_UP)
308 netif_wake_queue(card->dev);
309 return rc;
310 }
311 EXPORT_SYMBOL_GPL(qeth_set_large_send);
312
313 static int qeth_issue_next_read(struct qeth_card *card)
314 {
315 int rc;
316 struct qeth_cmd_buffer *iob;
317
318 QETH_DBF_TEXT(TRACE, 5, "issnxrd");
319 if (card->read.state != CH_STATE_UP)
320 return -EIO;
321 iob = qeth_get_buffer(&card->read);
322 if (!iob) {
323 PRINT_WARN("issue_next_read failed: no iob available!\n");
324 return -ENOMEM;
325 }
326 qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
327 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
328 rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
329 (addr_t) iob, 0, 0);
330 if (rc) {
331 PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
332 atomic_set(&card->read.irq_pending, 0);
333 qeth_schedule_recovery(card);
334 wake_up(&card->wait_q);
335 }
336 return rc;
337 }
338
339 static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
340 {
341 struct qeth_reply *reply;
342
343 reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
344 if (reply) {
345 atomic_set(&reply->refcnt, 1);
346 atomic_set(&reply->received, 0);
347 reply->card = card;
348 };
349 return reply;
350 }
351
352 static void qeth_get_reply(struct qeth_reply *reply)
353 {
354 WARN_ON(atomic_read(&reply->refcnt) <= 0);
355 atomic_inc(&reply->refcnt);
356 }
357
358 static void qeth_put_reply(struct qeth_reply *reply)
359 {
360 WARN_ON(atomic_read(&reply->refcnt) <= 0);
361 if (atomic_dec_and_test(&reply->refcnt))
362 kfree(reply);
363 }
364
365 static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
366 struct qeth_card *card)
367 {
368 char *ipa_name;
369 int com = cmd->hdr.command;
370 ipa_name = qeth_get_ipa_cmd_name(com);
371 if (rc)
372 QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
373 ipa_name, com, QETH_CARD_IFNAME(card),
374 rc, qeth_get_ipa_msg(rc));
375 else
376 QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
377 ipa_name, com, QETH_CARD_IFNAME(card));
378 }
379
380 static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
381 struct qeth_cmd_buffer *iob)
382 {
383 struct qeth_ipa_cmd *cmd = NULL;
384
385 QETH_DBF_TEXT(TRACE, 5, "chkipad");
386 if (IS_IPA(iob->data)) {
387 cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
388 if (IS_IPA_REPLY(cmd)) {
389 if (cmd->hdr.command < IPA_CMD_SETCCID ||
390 cmd->hdr.command > IPA_CMD_MODCCID)
391 qeth_issue_ipa_msg(cmd,
392 cmd->hdr.return_code, card);
393 return cmd;
394 } else {
395 switch (cmd->hdr.command) {
396 case IPA_CMD_STOPLAN:
397 PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
398 "there is a network problem or "
399 "someone pulled the cable or "
400 "disabled the port.\n",
401 QETH_CARD_IFNAME(card),
402 card->info.chpid);
403 card->lan_online = 0;
404 if (card->dev && netif_carrier_ok(card->dev))
405 netif_carrier_off(card->dev);
406 return NULL;
407 case IPA_CMD_STARTLAN:
408 PRINT_INFO("Link reestablished on %s "
409 "(CHPID 0x%X). Scheduling "
410 "IP address reset.\n",
411 QETH_CARD_IFNAME(card),
412 card->info.chpid);
413 netif_carrier_on(card->dev);
414 card->lan_online = 1;
415 qeth_schedule_recovery(card);
416 return NULL;
417 case IPA_CMD_MODCCID:
418 return cmd;
419 case IPA_CMD_REGISTER_LOCAL_ADDR:
420 QETH_DBF_TEXT(TRACE, 3, "irla");
421 break;
422 case IPA_CMD_UNREGISTER_LOCAL_ADDR:
423 QETH_DBF_TEXT(TRACE, 3, "urla");
424 break;
425 default:
426 PRINT_WARN("Received data is IPA "
427 "but not a reply!\n");
428 break;
429 }
430 }
431 }
432 return cmd;
433 }
434
435 void qeth_clear_ipacmd_list(struct qeth_card *card)
436 {
437 struct qeth_reply *reply, *r;
438 unsigned long flags;
439
440 QETH_DBF_TEXT(TRACE, 4, "clipalst");
441
442 spin_lock_irqsave(&card->lock, flags);
443 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
444 qeth_get_reply(reply);
445 reply->rc = -EIO;
446 atomic_inc(&reply->received);
447 list_del_init(&reply->list);
448 wake_up(&reply->wait_q);
449 qeth_put_reply(reply);
450 }
451 spin_unlock_irqrestore(&card->lock, flags);
452 }
453 EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
454
455 static int qeth_check_idx_response(unsigned char *buffer)
456 {
457 if (!buffer)
458 return 0;
459
460 QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
461 if ((buffer[2] & 0xc0) == 0xc0) {
462 PRINT_WARN("received an IDX TERMINATE "
463 "with cause code 0x%02x%s\n",
464 buffer[4],
465 ((buffer[4] == 0x22) ?
466 " -- try another portname" : ""));
467 QETH_DBF_TEXT(TRACE, 2, "ckidxres");
468 QETH_DBF_TEXT(TRACE, 2, " idxterm");
469 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
470 return -EIO;
471 }
472 return 0;
473 }
474
475 static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
476 __u32 len)
477 {
478 struct qeth_card *card;
479
480 QETH_DBF_TEXT(TRACE, 4, "setupccw");
481 card = CARD_FROM_CDEV(channel->ccwdev);
482 if (channel == &card->read)
483 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
484 else
485 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
486 channel->ccw.count = len;
487 channel->ccw.cda = (__u32) __pa(iob);
488 }
489
490 static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
491 {
492 __u8 index;
493
494 QETH_DBF_TEXT(TRACE, 6, "getbuff");
495 index = channel->io_buf_no;
496 do {
497 if (channel->iob[index].state == BUF_STATE_FREE) {
498 channel->iob[index].state = BUF_STATE_LOCKED;
499 channel->io_buf_no = (channel->io_buf_no + 1) %
500 QETH_CMD_BUFFER_NO;
501 memset(channel->iob[index].data, 0, QETH_BUFSIZE);
502 return channel->iob + index;
503 }
504 index = (index + 1) % QETH_CMD_BUFFER_NO;
505 } while (index != channel->io_buf_no);
506
507 return NULL;
508 }
509
510 void qeth_release_buffer(struct qeth_channel *channel,
511 struct qeth_cmd_buffer *iob)
512 {
513 unsigned long flags;
514
515 QETH_DBF_TEXT(TRACE, 6, "relbuff");
516 spin_lock_irqsave(&channel->iob_lock, flags);
517 memset(iob->data, 0, QETH_BUFSIZE);
518 iob->state = BUF_STATE_FREE;
519 iob->callback = qeth_send_control_data_cb;
520 iob->rc = 0;
521 spin_unlock_irqrestore(&channel->iob_lock, flags);
522 }
523 EXPORT_SYMBOL_GPL(qeth_release_buffer);
524
525 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
526 {
527 struct qeth_cmd_buffer *buffer = NULL;
528 unsigned long flags;
529
530 spin_lock_irqsave(&channel->iob_lock, flags);
531 buffer = __qeth_get_buffer(channel);
532 spin_unlock_irqrestore(&channel->iob_lock, flags);
533 return buffer;
534 }
535
536 struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
537 {
538 struct qeth_cmd_buffer *buffer;
539 wait_event(channel->wait_q,
540 ((buffer = qeth_get_buffer(channel)) != NULL));
541 return buffer;
542 }
543 EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
544
545 void qeth_clear_cmd_buffers(struct qeth_channel *channel)
546 {
547 int cnt;
548
549 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
550 qeth_release_buffer(channel, &channel->iob[cnt]);
551 channel->buf_no = 0;
552 channel->io_buf_no = 0;
553 }
554 EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
555
556 static void qeth_send_control_data_cb(struct qeth_channel *channel,
557 struct qeth_cmd_buffer *iob)
558 {
559 struct qeth_card *card;
560 struct qeth_reply *reply, *r;
561 struct qeth_ipa_cmd *cmd;
562 unsigned long flags;
563 int keep_reply;
564
565 QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
566
567 card = CARD_FROM_CDEV(channel->ccwdev);
568 if (qeth_check_idx_response(iob->data)) {
569 qeth_clear_ipacmd_list(card);
570 qeth_schedule_recovery(card);
571 goto out;
572 }
573
574 cmd = qeth_check_ipa_data(card, iob);
575 if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
576 goto out;
577 /*in case of OSN : check if cmd is set */
578 if (card->info.type == QETH_CARD_TYPE_OSN &&
579 cmd &&
580 cmd->hdr.command != IPA_CMD_STARTLAN &&
581 card->osn_info.assist_cb != NULL) {
582 card->osn_info.assist_cb(card->dev, cmd);
583 goto out;
584 }
585
586 spin_lock_irqsave(&card->lock, flags);
587 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
588 if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
589 ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
590 qeth_get_reply(reply);
591 list_del_init(&reply->list);
592 spin_unlock_irqrestore(&card->lock, flags);
593 keep_reply = 0;
594 if (reply->callback != NULL) {
595 if (cmd) {
596 reply->offset = (__u16)((char *)cmd -
597 (char *)iob->data);
598 keep_reply = reply->callback(card,
599 reply,
600 (unsigned long)cmd);
601 } else
602 keep_reply = reply->callback(card,
603 reply,
604 (unsigned long)iob);
605 }
606 if (cmd)
607 reply->rc = (u16) cmd->hdr.return_code;
608 else if (iob->rc)
609 reply->rc = iob->rc;
610 if (keep_reply) {
611 spin_lock_irqsave(&card->lock, flags);
612 list_add_tail(&reply->list,
613 &card->cmd_waiter_list);
614 spin_unlock_irqrestore(&card->lock, flags);
615 } else {
616 atomic_inc(&reply->received);
617 wake_up(&reply->wait_q);
618 }
619 qeth_put_reply(reply);
620 goto out;
621 }
622 }
623 spin_unlock_irqrestore(&card->lock, flags);
624 out:
625 memcpy(&card->seqno.pdu_hdr_ack,
626 QETH_PDU_HEADER_SEQ_NO(iob->data),
627 QETH_SEQ_NO_LENGTH);
628 qeth_release_buffer(channel, iob);
629 }
630
631 static int qeth_setup_channel(struct qeth_channel *channel)
632 {
633 int cnt;
634
635 QETH_DBF_TEXT(SETUP, 2, "setupch");
636 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
637 channel->iob[cnt].data = (char *)
638 kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
639 if (channel->iob[cnt].data == NULL)
640 break;
641 channel->iob[cnt].state = BUF_STATE_FREE;
642 channel->iob[cnt].channel = channel;
643 channel->iob[cnt].callback = qeth_send_control_data_cb;
644 channel->iob[cnt].rc = 0;
645 }
646 if (cnt < QETH_CMD_BUFFER_NO) {
647 while (cnt-- > 0)
648 kfree(channel->iob[cnt].data);
649 return -ENOMEM;
650 }
651 channel->buf_no = 0;
652 channel->io_buf_no = 0;
653 atomic_set(&channel->irq_pending, 0);
654 spin_lock_init(&channel->iob_lock);
655
656 init_waitqueue_head(&channel->wait_q);
657 return 0;
658 }
659
660 static int qeth_set_thread_start_bit(struct qeth_card *card,
661 unsigned long thread)
662 {
663 unsigned long flags;
664
665 spin_lock_irqsave(&card->thread_mask_lock, flags);
666 if (!(card->thread_allowed_mask & thread) ||
667 (card->thread_start_mask & thread)) {
668 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
669 return -EPERM;
670 }
671 card->thread_start_mask |= thread;
672 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
673 return 0;
674 }
675
676 void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
677 {
678 unsigned long flags;
679
680 spin_lock_irqsave(&card->thread_mask_lock, flags);
681 card->thread_start_mask &= ~thread;
682 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
683 wake_up(&card->wait_q);
684 }
685 EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
686
687 void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
688 {
689 unsigned long flags;
690
691 spin_lock_irqsave(&card->thread_mask_lock, flags);
692 card->thread_running_mask &= ~thread;
693 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
694 wake_up(&card->wait_q);
695 }
696 EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
697
698 static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
699 {
700 unsigned long flags;
701 int rc = 0;
702
703 spin_lock_irqsave(&card->thread_mask_lock, flags);
704 if (card->thread_start_mask & thread) {
705 if ((card->thread_allowed_mask & thread) &&
706 !(card->thread_running_mask & thread)) {
707 rc = 1;
708 card->thread_start_mask &= ~thread;
709 card->thread_running_mask |= thread;
710 } else
711 rc = -EPERM;
712 }
713 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
714 return rc;
715 }
716
717 int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
718 {
719 int rc = 0;
720
721 wait_event(card->wait_q,
722 (rc = __qeth_do_run_thread(card, thread)) >= 0);
723 return rc;
724 }
725 EXPORT_SYMBOL_GPL(qeth_do_run_thread);
726
727 void qeth_schedule_recovery(struct qeth_card *card)
728 {
729 QETH_DBF_TEXT(TRACE, 2, "startrec");
730 if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
731 schedule_work(&card->kernel_thread_starter);
732 }
733 EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
734
735 static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
736 {
737 int dstat, cstat;
738 char *sense;
739
740 sense = (char *) irb->ecw;
741 cstat = irb->scsw.cstat;
742 dstat = irb->scsw.dstat;
743
744 if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
745 SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
746 SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
747 QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
748 PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
749 cdev->dev.bus_id, dstat, cstat);
750 print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
751 16, 1, irb, 64, 1);
752 return 1;
753 }
754
755 if (dstat & DEV_STAT_UNIT_CHECK) {
756 if (sense[SENSE_RESETTING_EVENT_BYTE] &
757 SENSE_RESETTING_EVENT_FLAG) {
758 QETH_DBF_TEXT(TRACE, 2, "REVIND");
759 return 1;
760 }
761 if (sense[SENSE_COMMAND_REJECT_BYTE] &
762 SENSE_COMMAND_REJECT_FLAG) {
763 QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
764 return 0;
765 }
766 if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
767 QETH_DBF_TEXT(TRACE, 2, "AFFE");
768 return 1;
769 }
770 if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
771 QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
772 return 0;
773 }
774 QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
775 return 1;
776 }
777 return 0;
778 }
779
780 static long __qeth_check_irb_error(struct ccw_device *cdev,
781 unsigned long intparm, struct irb *irb)
782 {
783 if (!IS_ERR(irb))
784 return 0;
785
786 switch (PTR_ERR(irb)) {
787 case -EIO:
788 PRINT_WARN("i/o-error on device %s\n", cdev->dev.bus_id);
789 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
790 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
791 break;
792 case -ETIMEDOUT:
793 PRINT_WARN("timeout on device %s\n", cdev->dev.bus_id);
794 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
795 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
796 if (intparm == QETH_RCD_PARM) {
797 struct qeth_card *card = CARD_FROM_CDEV(cdev);
798
799 if (card && (card->data.ccwdev == cdev)) {
800 card->data.state = CH_STATE_DOWN;
801 wake_up(&card->wait_q);
802 }
803 }
804 break;
805 default:
806 PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
807 cdev->dev.bus_id);
808 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
809 QETH_DBF_TEXT(TRACE, 2, " rc???");
810 }
811 return PTR_ERR(irb);
812 }
813
814 static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
815 struct irb *irb)
816 {
817 int rc;
818 int cstat, dstat;
819 struct qeth_cmd_buffer *buffer;
820 struct qeth_channel *channel;
821 struct qeth_card *card;
822 struct qeth_cmd_buffer *iob;
823 __u8 index;
824
825 QETH_DBF_TEXT(TRACE, 5, "irq");
826
827 if (__qeth_check_irb_error(cdev, intparm, irb))
828 return;
829 cstat = irb->scsw.cstat;
830 dstat = irb->scsw.dstat;
831
832 card = CARD_FROM_CDEV(cdev);
833 if (!card)
834 return;
835
836 if (card->read.ccwdev == cdev) {
837 channel = &card->read;
838 QETH_DBF_TEXT(TRACE, 5, "read");
839 } else if (card->write.ccwdev == cdev) {
840 channel = &card->write;
841 QETH_DBF_TEXT(TRACE, 5, "write");
842 } else {
843 channel = &card->data;
844 QETH_DBF_TEXT(TRACE, 5, "data");
845 }
846 atomic_set(&channel->irq_pending, 0);
847
848 if (irb->scsw.fctl & (SCSW_FCTL_CLEAR_FUNC))
849 channel->state = CH_STATE_STOPPED;
850
851 if (irb->scsw.fctl & (SCSW_FCTL_HALT_FUNC))
852 channel->state = CH_STATE_HALTED;
853
854 /*let's wake up immediately on data channel*/
855 if ((channel == &card->data) && (intparm != 0) &&
856 (intparm != QETH_RCD_PARM))
857 goto out;
858
859 if (intparm == QETH_CLEAR_CHANNEL_PARM) {
860 QETH_DBF_TEXT(TRACE, 6, "clrchpar");
861 /* we don't have to handle this further */
862 intparm = 0;
863 }
864 if (intparm == QETH_HALT_CHANNEL_PARM) {
865 QETH_DBF_TEXT(TRACE, 6, "hltchpar");
866 /* we don't have to handle this further */
867 intparm = 0;
868 }
869 if ((dstat & DEV_STAT_UNIT_EXCEP) ||
870 (dstat & DEV_STAT_UNIT_CHECK) ||
871 (cstat)) {
872 if (irb->esw.esw0.erw.cons) {
873 /* TODO: we should make this s390dbf */
874 PRINT_WARN("sense data available on channel %s.\n",
875 CHANNEL_ID(channel));
876 PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
877 print_hex_dump(KERN_WARNING, "qeth: irb ",
878 DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
879 print_hex_dump(KERN_WARNING, "qeth: sense data ",
880 DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
881 }
882 if (intparm == QETH_RCD_PARM) {
883 channel->state = CH_STATE_DOWN;
884 goto out;
885 }
886 rc = qeth_get_problem(cdev, irb);
887 if (rc) {
888 qeth_schedule_recovery(card);
889 goto out;
890 }
891 }
892
893 if (intparm == QETH_RCD_PARM) {
894 channel->state = CH_STATE_RCD_DONE;
895 goto out;
896 }
897 if (intparm) {
898 buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
899 buffer->state = BUF_STATE_PROCESSED;
900 }
901 if (channel == &card->data)
902 return;
903 if (channel == &card->read &&
904 channel->state == CH_STATE_UP)
905 qeth_issue_next_read(card);
906
907 iob = channel->iob;
908 index = channel->buf_no;
909 while (iob[index].state == BUF_STATE_PROCESSED) {
910 if (iob[index].callback != NULL)
911 iob[index].callback(channel, iob + index);
912
913 index = (index + 1) % QETH_CMD_BUFFER_NO;
914 }
915 channel->buf_no = index;
916 out:
917 wake_up(&card->wait_q);
918 return;
919 }
920
921 static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
922 struct qeth_qdio_out_buffer *buf)
923 {
924 int i;
925 struct sk_buff *skb;
926
927 /* is PCI flag set on buffer? */
928 if (buf->buffer->element[0].flags & 0x40)
929 atomic_dec(&queue->set_pci_flags_count);
930
931 skb = skb_dequeue(&buf->skb_list);
932 while (skb) {
933 atomic_dec(&skb->users);
934 dev_kfree_skb_any(skb);
935 skb = skb_dequeue(&buf->skb_list);
936 }
937 qeth_eddp_buf_release_contexts(buf);
938 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
939 buf->buffer->element[i].length = 0;
940 buf->buffer->element[i].addr = NULL;
941 buf->buffer->element[i].flags = 0;
942 }
943 buf->next_element_to_fill = 0;
944 atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
945 }
946
947 void qeth_clear_qdio_buffers(struct qeth_card *card)
948 {
949 int i, j;
950
951 QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
952 /* clear outbound buffers to free skbs */
953 for (i = 0; i < card->qdio.no_out_queues; ++i)
954 if (card->qdio.out_qs[i]) {
955 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
956 qeth_clear_output_buffer(card->qdio.out_qs[i],
957 &card->qdio.out_qs[i]->bufs[j]);
958 }
959 }
960 EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
961
962 static void qeth_free_buffer_pool(struct qeth_card *card)
963 {
964 struct qeth_buffer_pool_entry *pool_entry, *tmp;
965 int i = 0;
966 QETH_DBF_TEXT(TRACE, 5, "freepool");
967 list_for_each_entry_safe(pool_entry, tmp,
968 &card->qdio.init_pool.entry_list, init_list){
969 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
970 free_page((unsigned long)pool_entry->elements[i]);
971 list_del(&pool_entry->init_list);
972 kfree(pool_entry);
973 }
974 }
975
976 static void qeth_free_qdio_buffers(struct qeth_card *card)
977 {
978 int i, j;
979
980 QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
981 if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
982 QETH_QDIO_UNINITIALIZED)
983 return;
984 kfree(card->qdio.in_q);
985 card->qdio.in_q = NULL;
986 /* inbound buffer pool */
987 qeth_free_buffer_pool(card);
988 /* free outbound qdio_qs */
989 if (card->qdio.out_qs) {
990 for (i = 0; i < card->qdio.no_out_queues; ++i) {
991 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
992 qeth_clear_output_buffer(card->qdio.out_qs[i],
993 &card->qdio.out_qs[i]->bufs[j]);
994 kfree(card->qdio.out_qs[i]);
995 }
996 kfree(card->qdio.out_qs);
997 card->qdio.out_qs = NULL;
998 }
999 }
1000
1001 static void qeth_clean_channel(struct qeth_channel *channel)
1002 {
1003 int cnt;
1004
1005 QETH_DBF_TEXT(SETUP, 2, "freech");
1006 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
1007 kfree(channel->iob[cnt].data);
1008 }
1009
1010 static int qeth_is_1920_device(struct qeth_card *card)
1011 {
1012 int single_queue = 0;
1013 struct ccw_device *ccwdev;
1014 struct channelPath_dsc {
1015 u8 flags;
1016 u8 lsn;
1017 u8 desc;
1018 u8 chpid;
1019 u8 swla;
1020 u8 zeroes;
1021 u8 chla;
1022 u8 chpp;
1023 } *chp_dsc;
1024
1025 QETH_DBF_TEXT(SETUP, 2, "chk_1920");
1026
1027 ccwdev = card->data.ccwdev;
1028 chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
1029 if (chp_dsc != NULL) {
1030 /* CHPP field bit 6 == 1 -> single queue */
1031 single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
1032 kfree(chp_dsc);
1033 }
1034 QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
1035 return single_queue;
1036 }
1037
1038 static void qeth_init_qdio_info(struct qeth_card *card)
1039 {
1040 QETH_DBF_TEXT(SETUP, 4, "intqdinf");
1041 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
1042 /* inbound */
1043 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1044 card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
1045 card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
1046 INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
1047 INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
1048 }
1049
1050 static void qeth_set_intial_options(struct qeth_card *card)
1051 {
1052 card->options.route4.type = NO_ROUTER;
1053 card->options.route6.type = NO_ROUTER;
1054 card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
1055 card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
1056 card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
1057 card->options.fake_broadcast = 0;
1058 card->options.add_hhlen = DEFAULT_ADD_HHLEN;
1059 card->options.fake_ll = 0;
1060 card->options.performance_stats = 0;
1061 card->options.rx_sg_cb = QETH_RX_SG_CB;
1062 }
1063
1064 static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
1065 {
1066 unsigned long flags;
1067 int rc = 0;
1068
1069 spin_lock_irqsave(&card->thread_mask_lock, flags);
1070 QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
1071 (u8) card->thread_start_mask,
1072 (u8) card->thread_allowed_mask,
1073 (u8) card->thread_running_mask);
1074 rc = (card->thread_start_mask & thread);
1075 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
1076 return rc;
1077 }
1078
1079 static void qeth_start_kernel_thread(struct work_struct *work)
1080 {
1081 struct qeth_card *card = container_of(work, struct qeth_card,
1082 kernel_thread_starter);
1083 QETH_DBF_TEXT(TRACE , 2, "strthrd");
1084
1085 if (card->read.state != CH_STATE_UP &&
1086 card->write.state != CH_STATE_UP)
1087 return;
1088 if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
1089 kthread_run(card->discipline.recover, (void *) card,
1090 "qeth_recover");
1091 }
1092
1093 static int qeth_setup_card(struct qeth_card *card)
1094 {
1095
1096 QETH_DBF_TEXT(SETUP, 2, "setupcrd");
1097 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
1098
1099 card->read.state = CH_STATE_DOWN;
1100 card->write.state = CH_STATE_DOWN;
1101 card->data.state = CH_STATE_DOWN;
1102 card->state = CARD_STATE_DOWN;
1103 card->lan_online = 0;
1104 card->use_hard_stop = 0;
1105 card->dev = NULL;
1106 spin_lock_init(&card->vlanlock);
1107 spin_lock_init(&card->mclock);
1108 card->vlangrp = NULL;
1109 spin_lock_init(&card->lock);
1110 spin_lock_init(&card->ip_lock);
1111 spin_lock_init(&card->thread_mask_lock);
1112 card->thread_start_mask = 0;
1113 card->thread_allowed_mask = 0;
1114 card->thread_running_mask = 0;
1115 INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
1116 INIT_LIST_HEAD(&card->ip_list);
1117 card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
1118 if (!card->ip_tbd_list) {
1119 QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
1120 return -ENOMEM;
1121 }
1122 INIT_LIST_HEAD(card->ip_tbd_list);
1123 INIT_LIST_HEAD(&card->cmd_waiter_list);
1124 init_waitqueue_head(&card->wait_q);
1125 /* intial options */
1126 qeth_set_intial_options(card);
1127 /* IP address takeover */
1128 INIT_LIST_HEAD(&card->ipato.entries);
1129 card->ipato.enabled = 0;
1130 card->ipato.invert4 = 0;
1131 card->ipato.invert6 = 0;
1132 /* init QDIO stuff */
1133 qeth_init_qdio_info(card);
1134 return 0;
1135 }
1136
1137 static struct qeth_card *qeth_alloc_card(void)
1138 {
1139 struct qeth_card *card;
1140
1141 QETH_DBF_TEXT(SETUP, 2, "alloccrd");
1142 card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
1143 if (!card)
1144 return NULL;
1145 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
1146 if (qeth_setup_channel(&card->read)) {
1147 kfree(card);
1148 return NULL;
1149 }
1150 if (qeth_setup_channel(&card->write)) {
1151 qeth_clean_channel(&card->read);
1152 kfree(card);
1153 return NULL;
1154 }
1155 card->options.layer2 = -1;
1156 return card;
1157 }
1158
1159 static int qeth_determine_card_type(struct qeth_card *card)
1160 {
1161 int i = 0;
1162
1163 QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
1164
1165 card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
1166 card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
1167 while (known_devices[i][4]) {
1168 if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
1169 (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
1170 card->info.type = known_devices[i][4];
1171 card->qdio.no_out_queues = known_devices[i][8];
1172 card->info.is_multicast_different = known_devices[i][9];
1173 if (qeth_is_1920_device(card)) {
1174 PRINT_INFO("Priority Queueing not able "
1175 "due to hardware limitations!\n");
1176 card->qdio.no_out_queues = 1;
1177 card->qdio.default_out_queue = 0;
1178 }
1179 return 0;
1180 }
1181 i++;
1182 }
1183 card->info.type = QETH_CARD_TYPE_UNKNOWN;
1184 PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
1185 return -ENOENT;
1186 }
1187
1188 static int qeth_clear_channel(struct qeth_channel *channel)
1189 {
1190 unsigned long flags;
1191 struct qeth_card *card;
1192 int rc;
1193
1194 QETH_DBF_TEXT(TRACE, 3, "clearch");
1195 card = CARD_FROM_CDEV(channel->ccwdev);
1196 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1197 rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
1198 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1199
1200 if (rc)
1201 return rc;
1202 rc = wait_event_interruptible_timeout(card->wait_q,
1203 channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
1204 if (rc == -ERESTARTSYS)
1205 return rc;
1206 if (channel->state != CH_STATE_STOPPED)
1207 return -ETIME;
1208 channel->state = CH_STATE_DOWN;
1209 return 0;
1210 }
1211
1212 static int qeth_halt_channel(struct qeth_channel *channel)
1213 {
1214 unsigned long flags;
1215 struct qeth_card *card;
1216 int rc;
1217
1218 QETH_DBF_TEXT(TRACE, 3, "haltch");
1219 card = CARD_FROM_CDEV(channel->ccwdev);
1220 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1221 rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
1222 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1223
1224 if (rc)
1225 return rc;
1226 rc = wait_event_interruptible_timeout(card->wait_q,
1227 channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
1228 if (rc == -ERESTARTSYS)
1229 return rc;
1230 if (channel->state != CH_STATE_HALTED)
1231 return -ETIME;
1232 return 0;
1233 }
1234
1235 static int qeth_halt_channels(struct qeth_card *card)
1236 {
1237 int rc1 = 0, rc2 = 0, rc3 = 0;
1238
1239 QETH_DBF_TEXT(TRACE, 3, "haltchs");
1240 rc1 = qeth_halt_channel(&card->read);
1241 rc2 = qeth_halt_channel(&card->write);
1242 rc3 = qeth_halt_channel(&card->data);
1243 if (rc1)
1244 return rc1;
1245 if (rc2)
1246 return rc2;
1247 return rc3;
1248 }
1249
1250 static int qeth_clear_channels(struct qeth_card *card)
1251 {
1252 int rc1 = 0, rc2 = 0, rc3 = 0;
1253
1254 QETH_DBF_TEXT(TRACE, 3, "clearchs");
1255 rc1 = qeth_clear_channel(&card->read);
1256 rc2 = qeth_clear_channel(&card->write);
1257 rc3 = qeth_clear_channel(&card->data);
1258 if (rc1)
1259 return rc1;
1260 if (rc2)
1261 return rc2;
1262 return rc3;
1263 }
1264
1265 static int qeth_clear_halt_card(struct qeth_card *card, int halt)
1266 {
1267 int rc = 0;
1268
1269 QETH_DBF_TEXT(TRACE, 3, "clhacrd");
1270 QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
1271
1272 if (halt)
1273 rc = qeth_halt_channels(card);
1274 if (rc)
1275 return rc;
1276 return qeth_clear_channels(card);
1277 }
1278
1279 int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
1280 {
1281 int rc = 0;
1282
1283 QETH_DBF_TEXT(TRACE, 3, "qdioclr");
1284 switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
1285 QETH_QDIO_CLEANING)) {
1286 case QETH_QDIO_ESTABLISHED:
1287 if (card->info.type == QETH_CARD_TYPE_IQD)
1288 rc = qdio_cleanup(CARD_DDEV(card),
1289 QDIO_FLAG_CLEANUP_USING_HALT);
1290 else
1291 rc = qdio_cleanup(CARD_DDEV(card),
1292 QDIO_FLAG_CLEANUP_USING_CLEAR);
1293 if (rc)
1294 QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
1295 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
1296 break;
1297 case QETH_QDIO_CLEANING:
1298 return rc;
1299 default:
1300 break;
1301 }
1302 rc = qeth_clear_halt_card(card, use_halt);
1303 if (rc)
1304 QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
1305 card->state = CARD_STATE_DOWN;
1306 return rc;
1307 }
1308 EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
1309
1310 static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
1311 int *length)
1312 {
1313 struct ciw *ciw;
1314 char *rcd_buf;
1315 int ret;
1316 struct qeth_channel *channel = &card->data;
1317 unsigned long flags;
1318
1319 /*
1320 * scan for RCD command in extended SenseID data
1321 */
1322 ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
1323 if (!ciw || ciw->cmd == 0)
1324 return -EOPNOTSUPP;
1325 rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
1326 if (!rcd_buf)
1327 return -ENOMEM;
1328
1329 channel->ccw.cmd_code = ciw->cmd;
1330 channel->ccw.cda = (__u32) __pa(rcd_buf);
1331 channel->ccw.count = ciw->count;
1332 channel->ccw.flags = CCW_FLAG_SLI;
1333 channel->state = CH_STATE_RCD;
1334 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1335 ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
1336 QETH_RCD_PARM, LPM_ANYPATH, 0,
1337 QETH_RCD_TIMEOUT);
1338 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1339 if (!ret)
1340 wait_event(card->wait_q,
1341 (channel->state == CH_STATE_RCD_DONE ||
1342 channel->state == CH_STATE_DOWN));
1343 if (channel->state == CH_STATE_DOWN)
1344 ret = -EIO;
1345 else
1346 channel->state = CH_STATE_DOWN;
1347 if (ret) {
1348 kfree(rcd_buf);
1349 *buffer = NULL;
1350 *length = 0;
1351 } else {
1352 *length = ciw->count;
1353 *buffer = rcd_buf;
1354 }
1355 return ret;
1356 }
1357
1358 static int qeth_get_unitaddr(struct qeth_card *card)
1359 {
1360 int length;
1361 char *prcd;
1362 int rc;
1363
1364 QETH_DBF_TEXT(SETUP, 2, "getunit");
1365 rc = qeth_read_conf_data(card, (void **) &prcd, &length);
1366 if (rc) {
1367 PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
1368 CARD_DDEV_ID(card), rc);
1369 return rc;
1370 }
1371 card->info.chpid = prcd[30];
1372 card->info.unit_addr2 = prcd[31];
1373 card->info.cula = prcd[63];
1374 card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
1375 (prcd[0x11] == _ascebc['M']));
1376 kfree(prcd);
1377 return 0;
1378 }
1379
1380 static void qeth_init_tokens(struct qeth_card *card)
1381 {
1382 card->token.issuer_rm_w = 0x00010103UL;
1383 card->token.cm_filter_w = 0x00010108UL;
1384 card->token.cm_connection_w = 0x0001010aUL;
1385 card->token.ulp_filter_w = 0x0001010bUL;
1386 card->token.ulp_connection_w = 0x0001010dUL;
1387 }
1388
1389 static void qeth_init_func_level(struct qeth_card *card)
1390 {
1391 if (card->ipato.enabled) {
1392 if (card->info.type == QETH_CARD_TYPE_IQD)
1393 card->info.func_level =
1394 QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
1395 else
1396 card->info.func_level =
1397 QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
1398 } else {
1399 if (card->info.type == QETH_CARD_TYPE_IQD)
1400 /*FIXME:why do we have same values for dis and ena for
1401 osae??? */
1402 card->info.func_level =
1403 QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
1404 else
1405 card->info.func_level =
1406 QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
1407 }
1408 }
1409
1410 static inline __u16 qeth_raw_devno_from_bus_id(char *id)
1411 {
1412 id += (strlen(id) - 4);
1413 return (__u16) simple_strtoul(id, &id, 16);
1414 }
1415
1416 static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
1417 void (*idx_reply_cb)(struct qeth_channel *,
1418 struct qeth_cmd_buffer *))
1419 {
1420 struct qeth_cmd_buffer *iob;
1421 unsigned long flags;
1422 int rc;
1423 struct qeth_card *card;
1424
1425 QETH_DBF_TEXT(SETUP, 2, "idxanswr");
1426 card = CARD_FROM_CDEV(channel->ccwdev);
1427 iob = qeth_get_buffer(channel);
1428 iob->callback = idx_reply_cb;
1429 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
1430 channel->ccw.count = QETH_BUFSIZE;
1431 channel->ccw.cda = (__u32) __pa(iob->data);
1432
1433 wait_event(card->wait_q,
1434 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
1435 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
1436 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1437 rc = ccw_device_start(channel->ccwdev,
1438 &channel->ccw, (addr_t) iob, 0, 0);
1439 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1440
1441 if (rc) {
1442 PRINT_ERR("Error2 in activating channel rc=%d\n", rc);
1443 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
1444 atomic_set(&channel->irq_pending, 0);
1445 wake_up(&card->wait_q);
1446 return rc;
1447 }
1448 rc = wait_event_interruptible_timeout(card->wait_q,
1449 channel->state == CH_STATE_UP, QETH_TIMEOUT);
1450 if (rc == -ERESTARTSYS)
1451 return rc;
1452 if (channel->state != CH_STATE_UP) {
1453 rc = -ETIME;
1454 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
1455 qeth_clear_cmd_buffers(channel);
1456 } else
1457 rc = 0;
1458 return rc;
1459 }
1460
1461 static int qeth_idx_activate_channel(struct qeth_channel *channel,
1462 void (*idx_reply_cb)(struct qeth_channel *,
1463 struct qeth_cmd_buffer *))
1464 {
1465 struct qeth_card *card;
1466 struct qeth_cmd_buffer *iob;
1467 unsigned long flags;
1468 __u16 temp;
1469 __u8 tmp;
1470 int rc;
1471
1472 card = CARD_FROM_CDEV(channel->ccwdev);
1473
1474 QETH_DBF_TEXT(SETUP, 2, "idxactch");
1475
1476 iob = qeth_get_buffer(channel);
1477 iob->callback = idx_reply_cb;
1478 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
1479 channel->ccw.count = IDX_ACTIVATE_SIZE;
1480 channel->ccw.cda = (__u32) __pa(iob->data);
1481 if (channel == &card->write) {
1482 memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
1483 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1484 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1485 card->seqno.trans_hdr++;
1486 } else {
1487 memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
1488 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1489 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1490 }
1491 tmp = ((__u8)card->info.portno) | 0x80;
1492 memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
1493 memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1494 &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
1495 memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
1496 &card->info.func_level, sizeof(__u16));
1497 temp = qeth_raw_devno_from_bus_id(CARD_DDEV_ID(card));
1498 memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp, 2);
1499 temp = (card->info.cula << 8) + card->info.unit_addr2;
1500 memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
1501
1502 wait_event(card->wait_q,
1503 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
1504 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
1505 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1506 rc = ccw_device_start(channel->ccwdev,
1507 &channel->ccw, (addr_t) iob, 0, 0);
1508 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1509
1510 if (rc) {
1511 PRINT_ERR("Error1 in activating channel. rc=%d\n", rc);
1512 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
1513 atomic_set(&channel->irq_pending, 0);
1514 wake_up(&card->wait_q);
1515 return rc;
1516 }
1517 rc = wait_event_interruptible_timeout(card->wait_q,
1518 channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
1519 if (rc == -ERESTARTSYS)
1520 return rc;
1521 if (channel->state != CH_STATE_ACTIVATING) {
1522 PRINT_WARN("IDX activate timed out!\n");
1523 QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
1524 qeth_clear_cmd_buffers(channel);
1525 return -ETIME;
1526 }
1527 return qeth_idx_activate_get_answer(channel, idx_reply_cb);
1528 }
1529
1530 static int qeth_peer_func_level(int level)
1531 {
1532 if ((level & 0xff) == 8)
1533 return (level & 0xff) + 0x400;
1534 if (((level >> 8) & 3) == 1)
1535 return (level & 0xff) + 0x200;
1536 return level;
1537 }
1538
1539 static void qeth_idx_write_cb(struct qeth_channel *channel,
1540 struct qeth_cmd_buffer *iob)
1541 {
1542 struct qeth_card *card;
1543 __u16 temp;
1544
1545 QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
1546
1547 if (channel->state == CH_STATE_DOWN) {
1548 channel->state = CH_STATE_ACTIVATING;
1549 goto out;
1550 }
1551 card = CARD_FROM_CDEV(channel->ccwdev);
1552
1553 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1554 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1555 PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
1556 "adapter exclusively used by another host\n",
1557 CARD_WDEV_ID(card));
1558 else
1559 PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
1560 "negative reply\n", CARD_WDEV_ID(card));
1561 goto out;
1562 }
1563 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1564 if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
1565 PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
1566 "function level mismatch "
1567 "(sent: 0x%x, received: 0x%x)\n",
1568 CARD_WDEV_ID(card), card->info.func_level, temp);
1569 goto out;
1570 }
1571 channel->state = CH_STATE_UP;
1572 out:
1573 qeth_release_buffer(channel, iob);
1574 }
1575
1576 static void qeth_idx_read_cb(struct qeth_channel *channel,
1577 struct qeth_cmd_buffer *iob)
1578 {
1579 struct qeth_card *card;
1580 __u16 temp;
1581
1582 QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
1583 if (channel->state == CH_STATE_DOWN) {
1584 channel->state = CH_STATE_ACTIVATING;
1585 goto out;
1586 }
1587
1588 card = CARD_FROM_CDEV(channel->ccwdev);
1589 if (qeth_check_idx_response(iob->data))
1590 goto out;
1591
1592 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1593 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1594 PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
1595 "adapter exclusively used by another host\n",
1596 CARD_RDEV_ID(card));
1597 else
1598 PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
1599 "negative reply\n", CARD_RDEV_ID(card));
1600 goto out;
1601 }
1602
1603 /**
1604 * temporary fix for microcode bug
1605 * to revert it,replace OR by AND
1606 */
1607 if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
1608 (card->info.type == QETH_CARD_TYPE_OSAE))
1609 card->info.portname_required = 1;
1610
1611 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1612 if (temp != qeth_peer_func_level(card->info.func_level)) {
1613 PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
1614 "level mismatch (sent: 0x%x, received: 0x%x)\n",
1615 CARD_RDEV_ID(card), card->info.func_level, temp);
1616 goto out;
1617 }
1618 memcpy(&card->token.issuer_rm_r,
1619 QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1620 QETH_MPC_TOKEN_LENGTH);
1621 memcpy(&card->info.mcl_level[0],
1622 QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
1623 channel->state = CH_STATE_UP;
1624 out:
1625 qeth_release_buffer(channel, iob);
1626 }
1627
1628 void qeth_prepare_control_data(struct qeth_card *card, int len,
1629 struct qeth_cmd_buffer *iob)
1630 {
1631 qeth_setup_ccw(&card->write, iob->data, len);
1632 iob->callback = qeth_release_buffer;
1633
1634 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1635 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1636 card->seqno.trans_hdr++;
1637 memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
1638 &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
1639 card->seqno.pdu_hdr++;
1640 memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
1641 &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
1642 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
1643 }
1644 EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
1645
1646 int qeth_send_control_data(struct qeth_card *card, int len,
1647 struct qeth_cmd_buffer *iob,
1648 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
1649 unsigned long),
1650 void *reply_param)
1651 {
1652 int rc;
1653 unsigned long flags;
1654 struct qeth_reply *reply = NULL;
1655 unsigned long timeout;
1656
1657 QETH_DBF_TEXT(TRACE, 2, "sendctl");
1658
1659 reply = qeth_alloc_reply(card);
1660 if (!reply) {
1661 PRINT_WARN("Could not alloc qeth_reply!\n");
1662 return -ENOMEM;
1663 }
1664 reply->callback = reply_cb;
1665 reply->param = reply_param;
1666 if (card->state == CARD_STATE_DOWN)
1667 reply->seqno = QETH_IDX_COMMAND_SEQNO;
1668 else
1669 reply->seqno = card->seqno.ipa++;
1670 init_waitqueue_head(&reply->wait_q);
1671 spin_lock_irqsave(&card->lock, flags);
1672 list_add_tail(&reply->list, &card->cmd_waiter_list);
1673 spin_unlock_irqrestore(&card->lock, flags);
1674 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
1675
1676 while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
1677 qeth_prepare_control_data(card, len, iob);
1678
1679 if (IS_IPA(iob->data))
1680 timeout = jiffies + QETH_IPA_TIMEOUT;
1681 else
1682 timeout = jiffies + QETH_TIMEOUT;
1683
1684 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
1685 spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
1686 rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
1687 (addr_t) iob, 0, 0);
1688 spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
1689 if (rc) {
1690 PRINT_WARN("qeth_send_control_data: "
1691 "ccw_device_start rc = %i\n", rc);
1692 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
1693 spin_lock_irqsave(&card->lock, flags);
1694 list_del_init(&reply->list);
1695 qeth_put_reply(reply);
1696 spin_unlock_irqrestore(&card->lock, flags);
1697 qeth_release_buffer(iob->channel, iob);
1698 atomic_set(&card->write.irq_pending, 0);
1699 wake_up(&card->wait_q);
1700 return rc;
1701 }
1702 while (!atomic_read(&reply->received)) {
1703 if (time_after(jiffies, timeout)) {
1704 spin_lock_irqsave(&reply->card->lock, flags);
1705 list_del_init(&reply->list);
1706 spin_unlock_irqrestore(&reply->card->lock, flags);
1707 reply->rc = -ETIME;
1708 atomic_inc(&reply->received);
1709 wake_up(&reply->wait_q);
1710 }
1711 cpu_relax();
1712 };
1713 rc = reply->rc;
1714 qeth_put_reply(reply);
1715 return rc;
1716 }
1717 EXPORT_SYMBOL_GPL(qeth_send_control_data);
1718
1719 static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1720 unsigned long data)
1721 {
1722 struct qeth_cmd_buffer *iob;
1723
1724 QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
1725
1726 iob = (struct qeth_cmd_buffer *) data;
1727 memcpy(&card->token.cm_filter_r,
1728 QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
1729 QETH_MPC_TOKEN_LENGTH);
1730 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1731 return 0;
1732 }
1733
1734 static int qeth_cm_enable(struct qeth_card *card)
1735 {
1736 int rc;
1737 struct qeth_cmd_buffer *iob;
1738
1739 QETH_DBF_TEXT(SETUP, 2, "cmenable");
1740
1741 iob = qeth_wait_for_buffer(&card->write);
1742 memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
1743 memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
1744 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1745 memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
1746 &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
1747
1748 rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
1749 qeth_cm_enable_cb, NULL);
1750 return rc;
1751 }
1752
1753 static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
1754 unsigned long data)
1755 {
1756
1757 struct qeth_cmd_buffer *iob;
1758
1759 QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
1760
1761 iob = (struct qeth_cmd_buffer *) data;
1762 memcpy(&card->token.cm_connection_r,
1763 QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
1764 QETH_MPC_TOKEN_LENGTH);
1765 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1766 return 0;
1767 }
1768
1769 static int qeth_cm_setup(struct qeth_card *card)
1770 {
1771 int rc;
1772 struct qeth_cmd_buffer *iob;
1773
1774 QETH_DBF_TEXT(SETUP, 2, "cmsetup");
1775
1776 iob = qeth_wait_for_buffer(&card->write);
1777 memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
1778 memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
1779 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1780 memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
1781 &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
1782 memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
1783 &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
1784 rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
1785 qeth_cm_setup_cb, NULL);
1786 return rc;
1787
1788 }
1789
1790 static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
1791 {
1792 switch (card->info.type) {
1793 case QETH_CARD_TYPE_UNKNOWN:
1794 return 1500;
1795 case QETH_CARD_TYPE_IQD:
1796 return card->info.max_mtu;
1797 case QETH_CARD_TYPE_OSAE:
1798 switch (card->info.link_type) {
1799 case QETH_LINK_TYPE_HSTR:
1800 case QETH_LINK_TYPE_LANE_TR:
1801 return 2000;
1802 default:
1803 return 1492;
1804 }
1805 default:
1806 return 1500;
1807 }
1808 }
1809
1810 static inline int qeth_get_max_mtu_for_card(int cardtype)
1811 {
1812 switch (cardtype) {
1813
1814 case QETH_CARD_TYPE_UNKNOWN:
1815 case QETH_CARD_TYPE_OSAE:
1816 case QETH_CARD_TYPE_OSN:
1817 return 61440;
1818 case QETH_CARD_TYPE_IQD:
1819 return 57344;
1820 default:
1821 return 1500;
1822 }
1823 }
1824
1825 static inline int qeth_get_mtu_out_of_mpc(int cardtype)
1826 {
1827 switch (cardtype) {
1828 case QETH_CARD_TYPE_IQD:
1829 return 1;
1830 default:
1831 return 0;
1832 }
1833 }
1834
1835 static inline int qeth_get_mtu_outof_framesize(int framesize)
1836 {
1837 switch (framesize) {
1838 case 0x4000:
1839 return 8192;
1840 case 0x6000:
1841 return 16384;
1842 case 0xa000:
1843 return 32768;
1844 case 0xffff:
1845 return 57344;
1846 default:
1847 return 0;
1848 }
1849 }
1850
1851 static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
1852 {
1853 switch (card->info.type) {
1854 case QETH_CARD_TYPE_OSAE:
1855 return ((mtu >= 576) && (mtu <= 61440));
1856 case QETH_CARD_TYPE_IQD:
1857 return ((mtu >= 576) &&
1858 (mtu <= card->info.max_mtu + 4096 - 32));
1859 case QETH_CARD_TYPE_OSN:
1860 case QETH_CARD_TYPE_UNKNOWN:
1861 default:
1862 return 1;
1863 }
1864 }
1865
1866 static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1867 unsigned long data)
1868 {
1869
1870 __u16 mtu, framesize;
1871 __u16 len;
1872 __u8 link_type;
1873 struct qeth_cmd_buffer *iob;
1874
1875 QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
1876
1877 iob = (struct qeth_cmd_buffer *) data;
1878 memcpy(&card->token.ulp_filter_r,
1879 QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
1880 QETH_MPC_TOKEN_LENGTH);
1881 if (qeth_get_mtu_out_of_mpc(card->info.type)) {
1882 memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
1883 mtu = qeth_get_mtu_outof_framesize(framesize);
1884 if (!mtu) {
1885 iob->rc = -EINVAL;
1886 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1887 return 0;
1888 }
1889 card->info.max_mtu = mtu;
1890 card->info.initial_mtu = mtu;
1891 card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
1892 } else {
1893 card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
1894 card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
1895 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1896 }
1897
1898 memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
1899 if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
1900 memcpy(&link_type,
1901 QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
1902 card->info.link_type = link_type;
1903 } else
1904 card->info.link_type = 0;
1905 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1906 return 0;
1907 }
1908
1909 static int qeth_ulp_enable(struct qeth_card *card)
1910 {
1911 int rc;
1912 char prot_type;
1913 struct qeth_cmd_buffer *iob;
1914
1915 /*FIXME: trace view callbacks*/
1916 QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
1917
1918 iob = qeth_wait_for_buffer(&card->write);
1919 memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
1920
1921 *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
1922 (__u8) card->info.portno;
1923 if (card->options.layer2)
1924 if (card->info.type == QETH_CARD_TYPE_OSN)
1925 prot_type = QETH_PROT_OSN2;
1926 else
1927 prot_type = QETH_PROT_LAYER2;
1928 else
1929 prot_type = QETH_PROT_TCPIP;
1930
1931 memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
1932 memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
1933 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
1934 memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
1935 &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
1936 memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
1937 card->info.portname, 9);
1938 rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
1939 qeth_ulp_enable_cb, NULL);
1940 return rc;
1941
1942 }
1943
1944 static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
1945 unsigned long data)
1946 {
1947 struct qeth_cmd_buffer *iob;
1948
1949 QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
1950
1951 iob = (struct qeth_cmd_buffer *) data;
1952 memcpy(&card->token.ulp_connection_r,
1953 QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
1954 QETH_MPC_TOKEN_LENGTH);
1955 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1956 return 0;
1957 }
1958
1959 static int qeth_ulp_setup(struct qeth_card *card)
1960 {
1961 int rc;
1962 __u16 temp;
1963 struct qeth_cmd_buffer *iob;
1964 struct ccw_dev_id dev_id;
1965
1966 QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
1967
1968 iob = qeth_wait_for_buffer(&card->write);
1969 memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
1970
1971 memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
1972 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
1973 memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
1974 &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
1975 memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
1976 &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
1977
1978 ccw_device_get_id(CARD_DDEV(card), &dev_id);
1979 memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
1980 temp = (card->info.cula << 8) + card->info.unit_addr2;
1981 memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
1982 rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
1983 qeth_ulp_setup_cb, NULL);
1984 return rc;
1985 }
1986
1987 static int qeth_alloc_qdio_buffers(struct qeth_card *card)
1988 {
1989 int i, j;
1990
1991 QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
1992
1993 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
1994 QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
1995 return 0;
1996
1997 card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
1998 GFP_KERNEL);
1999 if (!card->qdio.in_q)
2000 goto out_nomem;
2001 QETH_DBF_TEXT(SETUP, 2, "inq");
2002 QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
2003 memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
2004 /* give inbound qeth_qdio_buffers their qdio_buffers */
2005 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
2006 card->qdio.in_q->bufs[i].buffer =
2007 &card->qdio.in_q->qdio_bufs[i];
2008 /* inbound buffer pool */
2009 if (qeth_alloc_buffer_pool(card))
2010 goto out_freeinq;
2011 /* outbound */
2012 card->qdio.out_qs =
2013 kmalloc(card->qdio.no_out_queues *
2014 sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
2015 if (!card->qdio.out_qs)
2016 goto out_freepool;
2017 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2018 card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
2019 GFP_KERNEL);
2020 if (!card->qdio.out_qs[i])
2021 goto out_freeoutq;
2022 QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
2023 QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
2024 memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
2025 card->qdio.out_qs[i]->queue_no = i;
2026 /* give outbound qeth_qdio_buffers their qdio_buffers */
2027 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2028 card->qdio.out_qs[i]->bufs[j].buffer =
2029 &card->qdio.out_qs[i]->qdio_bufs[j];
2030 skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
2031 skb_list);
2032 lockdep_set_class(
2033 &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
2034 &qdio_out_skb_queue_key);
2035 INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
2036 }
2037 }
2038 return 0;
2039
2040 out_freeoutq:
2041 while (i > 0)
2042 kfree(card->qdio.out_qs[--i]);
2043 kfree(card->qdio.out_qs);
2044 card->qdio.out_qs = NULL;
2045 out_freepool:
2046 qeth_free_buffer_pool(card);
2047 out_freeinq:
2048 kfree(card->qdio.in_q);
2049 card->qdio.in_q = NULL;
2050 out_nomem:
2051 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
2052 return -ENOMEM;
2053 }
2054
2055 static void qeth_create_qib_param_field(struct qeth_card *card,
2056 char *param_field)
2057 {
2058
2059 param_field[0] = _ascebc['P'];
2060 param_field[1] = _ascebc['C'];
2061 param_field[2] = _ascebc['I'];
2062 param_field[3] = _ascebc['T'];
2063 *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
2064 *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
2065 *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
2066 }
2067
2068 static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
2069 char *param_field)
2070 {
2071 param_field[16] = _ascebc['B'];
2072 param_field[17] = _ascebc['L'];
2073 param_field[18] = _ascebc['K'];
2074 param_field[19] = _ascebc['T'];
2075 *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
2076 *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
2077 *((unsigned int *) (&param_field[28])) =
2078 card->info.blkt.inter_packet_jumbo;
2079 }
2080
2081 static int qeth_qdio_activate(struct qeth_card *card)
2082 {
2083 QETH_DBF_TEXT(SETUP, 3, "qdioact");
2084 return qdio_activate(CARD_DDEV(card), 0);
2085 }
2086
2087 static int qeth_dm_act(struct qeth_card *card)
2088 {
2089 int rc;
2090 struct qeth_cmd_buffer *iob;
2091
2092 QETH_DBF_TEXT(SETUP, 2, "dmact");
2093
2094 iob = qeth_wait_for_buffer(&card->write);
2095 memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
2096
2097 memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
2098 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
2099 memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
2100 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2101 rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
2102 return rc;
2103 }
2104
2105 static int qeth_mpc_initialize(struct qeth_card *card)
2106 {
2107 int rc;
2108
2109 QETH_DBF_TEXT(SETUP, 2, "mpcinit");
2110
2111 rc = qeth_issue_next_read(card);
2112 if (rc) {
2113 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
2114 return rc;
2115 }
2116 rc = qeth_cm_enable(card);
2117 if (rc) {
2118 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
2119 goto out_qdio;
2120 }
2121 rc = qeth_cm_setup(card);
2122 if (rc) {
2123 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
2124 goto out_qdio;
2125 }
2126 rc = qeth_ulp_enable(card);
2127 if (rc) {
2128 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
2129 goto out_qdio;
2130 }
2131 rc = qeth_ulp_setup(card);
2132 if (rc) {
2133 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
2134 goto out_qdio;
2135 }
2136 rc = qeth_alloc_qdio_buffers(card);
2137 if (rc) {
2138 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
2139 goto out_qdio;
2140 }
2141 rc = qeth_qdio_establish(card);
2142 if (rc) {
2143 QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
2144 qeth_free_qdio_buffers(card);
2145 goto out_qdio;
2146 }
2147 rc = qeth_qdio_activate(card);
2148 if (rc) {
2149 QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
2150 goto out_qdio;
2151 }
2152 rc = qeth_dm_act(card);
2153 if (rc) {
2154 QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
2155 goto out_qdio;
2156 }
2157
2158 return 0;
2159 out_qdio:
2160 qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
2161 return rc;
2162 }
2163
2164 static void qeth_print_status_with_portname(struct qeth_card *card)
2165 {
2166 char dbf_text[15];
2167 int i;
2168
2169 sprintf(dbf_text, "%s", card->info.portname + 1);
2170 for (i = 0; i < 8; i++)
2171 dbf_text[i] =
2172 (char) _ebcasc[(__u8) dbf_text[i]];
2173 dbf_text[8] = 0;
2174 PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
2175 "with link type %s (portname: %s)\n",
2176 CARD_RDEV_ID(card),
2177 CARD_WDEV_ID(card),
2178 CARD_DDEV_ID(card),
2179 qeth_get_cardname(card),
2180 (card->info.mcl_level[0]) ? " (level: " : "",
2181 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2182 (card->info.mcl_level[0]) ? ")" : "",
2183 qeth_get_cardname_short(card),
2184 dbf_text);
2185
2186 }
2187
2188 static void qeth_print_status_no_portname(struct qeth_card *card)
2189 {
2190 if (card->info.portname[0])
2191 PRINT_INFO("Device %s/%s/%s is a%s "
2192 "card%s%s%s\nwith link type %s "
2193 "(no portname needed by interface).\n",
2194 CARD_RDEV_ID(card),
2195 CARD_WDEV_ID(card),
2196 CARD_DDEV_ID(card),
2197 qeth_get_cardname(card),
2198 (card->info.mcl_level[0]) ? " (level: " : "",
2199 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2200 (card->info.mcl_level[0]) ? ")" : "",
2201 qeth_get_cardname_short(card));
2202 else
2203 PRINT_INFO("Device %s/%s/%s is a%s "
2204 "card%s%s%s\nwith link type %s.\n",
2205 CARD_RDEV_ID(card),
2206 CARD_WDEV_ID(card),
2207 CARD_DDEV_ID(card),
2208 qeth_get_cardname(card),
2209 (card->info.mcl_level[0]) ? " (level: " : "",
2210 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2211 (card->info.mcl_level[0]) ? ")" : "",
2212 qeth_get_cardname_short(card));
2213 }
2214
2215 void qeth_print_status_message(struct qeth_card *card)
2216 {
2217 switch (card->info.type) {
2218 case QETH_CARD_TYPE_OSAE:
2219 /* VM will use a non-zero first character
2220 * to indicate a HiperSockets like reporting
2221 * of the level OSA sets the first character to zero
2222 * */
2223 if (!card->info.mcl_level[0]) {
2224 sprintf(card->info.mcl_level, "%02x%02x",
2225 card->info.mcl_level[2],
2226 card->info.mcl_level[3]);
2227
2228 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2229 break;
2230 }
2231 /* fallthrough */
2232 case QETH_CARD_TYPE_IQD:
2233 if (card->info.guestlan) {
2234 card->info.mcl_level[0] = (char) _ebcasc[(__u8)
2235 card->info.mcl_level[0]];
2236 card->info.mcl_level[1] = (char) _ebcasc[(__u8)
2237 card->info.mcl_level[1]];
2238 card->info.mcl_level[2] = (char) _ebcasc[(__u8)
2239 card->info.mcl_level[2]];
2240 card->info.mcl_level[3] = (char) _ebcasc[(__u8)
2241 card->info.mcl_level[3]];
2242 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2243 }
2244 break;
2245 default:
2246 memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
2247 }
2248 if (card->info.portname_required)
2249 qeth_print_status_with_portname(card);
2250 else
2251 qeth_print_status_no_portname(card);
2252 }
2253 EXPORT_SYMBOL_GPL(qeth_print_status_message);
2254
2255 static void qeth_initialize_working_pool_list(struct qeth_card *card)
2256 {
2257 struct qeth_buffer_pool_entry *entry;
2258
2259 QETH_DBF_TEXT(TRACE, 5, "inwrklst");
2260
2261 list_for_each_entry(entry,
2262 &card->qdio.init_pool.entry_list, init_list) {
2263 qeth_put_buffer_pool_entry(card, entry);
2264 }
2265 }
2266
2267 static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
2268 struct qeth_card *card)
2269 {
2270 struct list_head *plh;
2271 struct qeth_buffer_pool_entry *entry;
2272 int i, free;
2273 struct page *page;
2274
2275 if (list_empty(&card->qdio.in_buf_pool.entry_list))
2276 return NULL;
2277
2278 list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
2279 entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
2280 free = 1;
2281 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2282 if (page_count(virt_to_page(entry->elements[i])) > 1) {
2283 free = 0;
2284 break;
2285 }
2286 }
2287 if (free) {
2288 list_del_init(&entry->list);
2289 return entry;
2290 }
2291 }
2292
2293 /* no free buffer in pool so take first one and swap pages */
2294 entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
2295 struct qeth_buffer_pool_entry, list);
2296 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2297 if (page_count(virt_to_page(entry->elements[i])) > 1) {
2298 page = alloc_page(GFP_ATOMIC);
2299 if (!page) {
2300 return NULL;
2301 } else {
2302 free_page((unsigned long)entry->elements[i]);
2303 entry->elements[i] = page_address(page);
2304 if (card->options.performance_stats)
2305 card->perf_stats.sg_alloc_page_rx++;
2306 }
2307 }
2308 }
2309 list_del_init(&entry->list);
2310 return entry;
2311 }
2312
2313 static int qeth_init_input_buffer(struct qeth_card *card,
2314 struct qeth_qdio_buffer *buf)
2315 {
2316 struct qeth_buffer_pool_entry *pool_entry;
2317 int i;
2318
2319 pool_entry = qeth_find_free_buffer_pool_entry(card);
2320 if (!pool_entry)
2321 return 1;
2322
2323 /*
2324 * since the buffer is accessed only from the input_tasklet
2325 * there shouldn't be a need to synchronize; also, since we use
2326 * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
2327 * buffers
2328 */
2329 BUG_ON(!pool_entry);
2330
2331 buf->pool_entry = pool_entry;
2332 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2333 buf->buffer->element[i].length = PAGE_SIZE;
2334 buf->buffer->element[i].addr = pool_entry->elements[i];
2335 if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
2336 buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
2337 else
2338 buf->buffer->element[i].flags = 0;
2339 }
2340 return 0;
2341 }
2342
2343 int qeth_init_qdio_queues(struct qeth_card *card)
2344 {
2345 int i, j;
2346 int rc;
2347
2348 QETH_DBF_TEXT(SETUP, 2, "initqdqs");
2349
2350 /* inbound queue */
2351 memset(card->qdio.in_q->qdio_bufs, 0,
2352 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2353 qeth_initialize_working_pool_list(card);
2354 /*give only as many buffers to hardware as we have buffer pool entries*/
2355 for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
2356 qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
2357 card->qdio.in_q->next_buf_to_init =
2358 card->qdio.in_buf_pool.buf_count - 1;
2359 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
2360 card->qdio.in_buf_pool.buf_count - 1, NULL);
2361 if (rc) {
2362 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
2363 return rc;
2364 }
2365 rc = qdio_synchronize(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0);
2366 if (rc) {
2367 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
2368 return rc;
2369 }
2370 /* outbound queue */
2371 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2372 memset(card->qdio.out_qs[i]->qdio_bufs, 0,
2373 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2374 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2375 qeth_clear_output_buffer(card->qdio.out_qs[i],
2376 &card->qdio.out_qs[i]->bufs[j]);
2377 }
2378 card->qdio.out_qs[i]->card = card;
2379 card->qdio.out_qs[i]->next_buf_to_fill = 0;
2380 card->qdio.out_qs[i]->do_pack = 0;
2381 atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
2382 atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
2383 atomic_set(&card->qdio.out_qs[i]->state,
2384 QETH_OUT_Q_UNLOCKED);
2385 }
2386 return 0;
2387 }
2388 EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
2389
2390 static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
2391 {
2392 switch (link_type) {
2393 case QETH_LINK_TYPE_HSTR:
2394 return 2;
2395 default:
2396 return 1;
2397 }
2398 }
2399
2400 static void qeth_fill_ipacmd_header(struct qeth_card *card,
2401 struct qeth_ipa_cmd *cmd, __u8 command,
2402 enum qeth_prot_versions prot)
2403 {
2404 memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
2405 cmd->hdr.command = command;
2406 cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
2407 cmd->hdr.seqno = card->seqno.ipa;
2408 cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
2409 cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
2410 if (card->options.layer2)
2411 cmd->hdr.prim_version_no = 2;
2412 else
2413 cmd->hdr.prim_version_no = 1;
2414 cmd->hdr.param_count = 1;
2415 cmd->hdr.prot_version = prot;
2416 cmd->hdr.ipa_supported = 0;
2417 cmd->hdr.ipa_enabled = 0;
2418 }
2419
2420 struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
2421 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2422 {
2423 struct qeth_cmd_buffer *iob;
2424 struct qeth_ipa_cmd *cmd;
2425
2426 iob = qeth_wait_for_buffer(&card->write);
2427 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2428 qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
2429
2430 return iob;
2431 }
2432 EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
2433
2434 void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2435 char prot_type)
2436 {
2437 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
2438 memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
2439 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
2440 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2441 }
2442 EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
2443
2444 int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2445 int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
2446 unsigned long),
2447 void *reply_param)
2448 {
2449 int rc;
2450 char prot_type;
2451
2452 QETH_DBF_TEXT(TRACE, 4, "sendipa");
2453
2454 if (card->options.layer2)
2455 if (card->info.type == QETH_CARD_TYPE_OSN)
2456 prot_type = QETH_PROT_OSN2;
2457 else
2458 prot_type = QETH_PROT_LAYER2;
2459 else
2460 prot_type = QETH_PROT_TCPIP;
2461 qeth_prepare_ipa_cmd(card, iob, prot_type);
2462 rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
2463 iob, reply_cb, reply_param);
2464 return rc;
2465 }
2466 EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
2467
2468 static int qeth_send_startstoplan(struct qeth_card *card,
2469 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2470 {
2471 int rc;
2472 struct qeth_cmd_buffer *iob;
2473
2474 iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
2475 rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
2476
2477 return rc;
2478 }
2479
2480 int qeth_send_startlan(struct qeth_card *card)
2481 {
2482 int rc;
2483
2484 QETH_DBF_TEXT(SETUP, 2, "strtlan");
2485
2486 rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
2487 return rc;
2488 }
2489 EXPORT_SYMBOL_GPL(qeth_send_startlan);
2490
2491 int qeth_send_stoplan(struct qeth_card *card)
2492 {
2493 int rc = 0;
2494
2495 /*
2496 * TODO: according to the IPA format document page 14,
2497 * TCP/IP (we!) never issue a STOPLAN
2498 * is this right ?!?
2499 */
2500 QETH_DBF_TEXT(SETUP, 2, "stoplan");
2501
2502 rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
2503 return rc;
2504 }
2505 EXPORT_SYMBOL_GPL(qeth_send_stoplan);
2506
2507 int qeth_default_setadapterparms_cb(struct qeth_card *card,
2508 struct qeth_reply *reply, unsigned long data)
2509 {
2510 struct qeth_ipa_cmd *cmd;
2511
2512 QETH_DBF_TEXT(TRACE, 4, "defadpcb");
2513
2514 cmd = (struct qeth_ipa_cmd *) data;
2515 if (cmd->hdr.return_code == 0)
2516 cmd->hdr.return_code =
2517 cmd->data.setadapterparms.hdr.return_code;
2518 return 0;
2519 }
2520 EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
2521
2522 static int qeth_query_setadapterparms_cb(struct qeth_card *card,
2523 struct qeth_reply *reply, unsigned long data)
2524 {
2525 struct qeth_ipa_cmd *cmd;
2526
2527 QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
2528
2529 cmd = (struct qeth_ipa_cmd *) data;
2530 if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
2531 card->info.link_type =
2532 cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
2533 card->options.adp.supported_funcs =
2534 cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
2535 return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
2536 }
2537
2538 struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
2539 __u32 command, __u32 cmdlen)
2540 {
2541 struct qeth_cmd_buffer *iob;
2542 struct qeth_ipa_cmd *cmd;
2543
2544 iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
2545 QETH_PROT_IPV4);
2546 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2547 cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
2548 cmd->data.setadapterparms.hdr.command_code = command;
2549 cmd->data.setadapterparms.hdr.used_total = 1;
2550 cmd->data.setadapterparms.hdr.seq_no = 1;
2551
2552 return iob;
2553 }
2554 EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
2555
2556 int qeth_query_setadapterparms(struct qeth_card *card)
2557 {
2558 int rc;
2559 struct qeth_cmd_buffer *iob;
2560
2561 QETH_DBF_TEXT(TRACE, 3, "queryadp");
2562 iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
2563 sizeof(struct qeth_ipacmd_setadpparms));
2564 rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
2565 return rc;
2566 }
2567 EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
2568
2569 int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
2570 unsigned int siga_error, const char *dbftext)
2571 {
2572 if (qdio_error || siga_error) {
2573 QETH_DBF_TEXT(TRACE, 2, dbftext);
2574 QETH_DBF_TEXT(QERR, 2, dbftext);
2575 QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
2576 buf->element[15].flags & 0xff);
2577 QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
2578 buf->element[14].flags & 0xff);
2579 QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
2580 QETH_DBF_TEXT_(QERR, 2, " serr=%X", siga_error);
2581 return 1;
2582 }
2583 return 0;
2584 }
2585 EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
2586
2587 void qeth_queue_input_buffer(struct qeth_card *card, int index)
2588 {
2589 struct qeth_qdio_q *queue = card->qdio.in_q;
2590 int count;
2591 int i;
2592 int rc;
2593 int newcount = 0;
2594
2595 count = (index < queue->next_buf_to_init)?
2596 card->qdio.in_buf_pool.buf_count -
2597 (queue->next_buf_to_init - index) :
2598 card->qdio.in_buf_pool.buf_count -
2599 (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
2600 /* only requeue at a certain threshold to avoid SIGAs */
2601 if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
2602 for (i = queue->next_buf_to_init;
2603 i < queue->next_buf_to_init + count; ++i) {
2604 if (qeth_init_input_buffer(card,
2605 &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
2606 break;
2607 } else {
2608 newcount++;
2609 }
2610 }
2611
2612 if (newcount < count) {
2613 /* we are in memory shortage so we switch back to
2614 traditional skb allocation and drop packages */
2615 if (!atomic_read(&card->force_alloc_skb) &&
2616 net_ratelimit())
2617 PRINT_WARN("Switch to alloc skb\n");
2618 atomic_set(&card->force_alloc_skb, 3);
2619 count = newcount;
2620 } else {
2621 if ((atomic_read(&card->force_alloc_skb) == 1) &&
2622 net_ratelimit())
2623 PRINT_WARN("Switch to sg\n");
2624 atomic_add_unless(&card->force_alloc_skb, -1, 0);
2625 }
2626
2627 /*
2628 * according to old code it should be avoided to requeue all
2629 * 128 buffers in order to benefit from PCI avoidance.
2630 * this function keeps at least one buffer (the buffer at
2631 * 'index') un-requeued -> this buffer is the first buffer that
2632 * will be requeued the next time
2633 */
2634 if (card->options.performance_stats) {
2635 card->perf_stats.inbound_do_qdio_cnt++;
2636 card->perf_stats.inbound_do_qdio_start_time =
2637 qeth_get_micros();
2638 }
2639 rc = do_QDIO(CARD_DDEV(card),
2640 QDIO_FLAG_SYNC_INPUT | QDIO_FLAG_UNDER_INTERRUPT,
2641 0, queue->next_buf_to_init, count, NULL);
2642 if (card->options.performance_stats)
2643 card->perf_stats.inbound_do_qdio_time +=
2644 qeth_get_micros() -
2645 card->perf_stats.inbound_do_qdio_start_time;
2646 if (rc) {
2647 PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
2648 "return %i (device %s).\n",
2649 rc, CARD_DDEV_ID(card));
2650 QETH_DBF_TEXT(TRACE, 2, "qinberr");
2651 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
2652 }
2653 queue->next_buf_to_init = (queue->next_buf_to_init + count) %
2654 QDIO_MAX_BUFFERS_PER_Q;
2655 }
2656 }
2657 EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
2658
2659 static int qeth_handle_send_error(struct qeth_card *card,
2660 struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err,
2661 unsigned int siga_err)
2662 {
2663 int sbalf15 = buffer->buffer->element[15].flags & 0xff;
2664 int cc = siga_err & 3;
2665
2666 QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
2667 qeth_check_qdio_errors(buffer->buffer, qdio_err, siga_err, "qouterr");
2668 switch (cc) {
2669 case 0:
2670 if (qdio_err) {
2671 QETH_DBF_TEXT(TRACE, 1, "lnkfail");
2672 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2673 QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
2674 (u16)qdio_err, (u8)sbalf15);
2675 return QETH_SEND_ERROR_LINK_FAILURE;
2676 }
2677 return QETH_SEND_ERROR_NONE;
2678 case 2:
2679 if (siga_err & QDIO_SIGA_ERROR_B_BIT_SET) {
2680 QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
2681 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2682 return QETH_SEND_ERROR_KICK_IT;
2683 }
2684 if ((sbalf15 >= 15) && (sbalf15 <= 31))
2685 return QETH_SEND_ERROR_RETRY;
2686 return QETH_SEND_ERROR_LINK_FAILURE;
2687 /* look at qdio_error and sbalf 15 */
2688 case 1:
2689 QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
2690 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2691 return QETH_SEND_ERROR_LINK_FAILURE;
2692 case 3:
2693 default:
2694 QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
2695 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2696 return QETH_SEND_ERROR_KICK_IT;
2697 }
2698 }
2699
2700 /*
2701 * Switched to packing state if the number of used buffers on a queue
2702 * reaches a certain limit.
2703 */
2704 static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
2705 {
2706 if (!queue->do_pack) {
2707 if (atomic_read(&queue->used_buffers)
2708 >= QETH_HIGH_WATERMARK_PACK){
2709 /* switch non-PACKING -> PACKING */
2710 QETH_DBF_TEXT(TRACE, 6, "np->pack");
2711 if (queue->card->options.performance_stats)
2712 queue->card->perf_stats.sc_dp_p++;
2713 queue->do_pack = 1;
2714 }
2715 }
2716 }
2717
2718 /*
2719 * Switches from packing to non-packing mode. If there is a packing
2720 * buffer on the queue this buffer will be prepared to be flushed.
2721 * In that case 1 is returned to inform the caller. If no buffer
2722 * has to be flushed, zero is returned.
2723 */
2724 static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
2725 {
2726 struct qeth_qdio_out_buffer *buffer;
2727 int flush_count = 0;
2728
2729 if (queue->do_pack) {
2730 if (atomic_read(&queue->used_buffers)
2731 <= QETH_LOW_WATERMARK_PACK) {
2732 /* switch PACKING -> non-PACKING */
2733 QETH_DBF_TEXT(TRACE, 6, "pack->np");
2734 if (queue->card->options.performance_stats)
2735 queue->card->perf_stats.sc_p_dp++;
2736 queue->do_pack = 0;
2737 /* flush packing buffers */
2738 buffer = &queue->bufs[queue->next_buf_to_fill];
2739 if ((atomic_read(&buffer->state) ==
2740 QETH_QDIO_BUF_EMPTY) &&
2741 (buffer->next_element_to_fill > 0)) {
2742 atomic_set(&buffer->state,
2743 QETH_QDIO_BUF_PRIMED);
2744 flush_count++;
2745 queue->next_buf_to_fill =
2746 (queue->next_buf_to_fill + 1) %
2747 QDIO_MAX_BUFFERS_PER_Q;
2748 }
2749 }
2750 }
2751 return flush_count;
2752 }
2753
2754 /*
2755 * Called to flush a packing buffer if no more pci flags are on the queue.
2756 * Checks if there is a packing buffer and prepares it to be flushed.
2757 * In that case returns 1, otherwise zero.
2758 */
2759 static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
2760 {
2761 struct qeth_qdio_out_buffer *buffer;
2762
2763 buffer = &queue->bufs[queue->next_buf_to_fill];
2764 if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
2765 (buffer->next_element_to_fill > 0)) {
2766 /* it's a packing buffer */
2767 atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
2768 queue->next_buf_to_fill =
2769 (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
2770 return 1;
2771 }
2772 return 0;
2773 }
2774
2775 static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int under_int,
2776 int index, int count)
2777 {
2778 struct qeth_qdio_out_buffer *buf;
2779 int rc;
2780 int i;
2781 unsigned int qdio_flags;
2782
2783 for (i = index; i < index + count; ++i) {
2784 buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2785 buf->buffer->element[buf->next_element_to_fill - 1].flags |=
2786 SBAL_FLAGS_LAST_ENTRY;
2787
2788 if (queue->card->info.type == QETH_CARD_TYPE_IQD)
2789 continue;
2790
2791 if (!queue->do_pack) {
2792 if ((atomic_read(&queue->used_buffers) >=
2793 (QETH_HIGH_WATERMARK_PACK -
2794 QETH_WATERMARK_PACK_FUZZ)) &&
2795 !atomic_read(&queue->set_pci_flags_count)) {
2796 /* it's likely that we'll go to packing
2797 * mode soon */
2798 atomic_inc(&queue->set_pci_flags_count);
2799 buf->buffer->element[0].flags |= 0x40;
2800 }
2801 } else {
2802 if (!atomic_read(&queue->set_pci_flags_count)) {
2803 /*
2804 * there's no outstanding PCI any more, so we
2805 * have to request a PCI to be sure the the PCI
2806 * will wake at some time in the future then we
2807 * can flush packed buffers that might still be
2808 * hanging around, which can happen if no
2809 * further send was requested by the stack
2810 */
2811 atomic_inc(&queue->set_pci_flags_count);
2812 buf->buffer->element[0].flags |= 0x40;
2813 }
2814 }
2815 }
2816
2817 queue->card->dev->trans_start = jiffies;
2818 if (queue->card->options.performance_stats) {
2819 queue->card->perf_stats.outbound_do_qdio_cnt++;
2820 queue->card->perf_stats.outbound_do_qdio_start_time =
2821 qeth_get_micros();
2822 }
2823 qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
2824 if (under_int)
2825 qdio_flags |= QDIO_FLAG_UNDER_INTERRUPT;
2826 if (atomic_read(&queue->set_pci_flags_count))
2827 qdio_flags |= QDIO_FLAG_PCI_OUT;
2828 rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
2829 queue->queue_no, index, count, NULL);
2830 if (queue->card->options.performance_stats)
2831 queue->card->perf_stats.outbound_do_qdio_time +=
2832 qeth_get_micros() -
2833 queue->card->perf_stats.outbound_do_qdio_start_time;
2834 if (rc) {
2835 QETH_DBF_TEXT(TRACE, 2, "flushbuf");
2836 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
2837 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
2838 queue->card->stats.tx_errors += count;
2839 /* this must not happen under normal circumstances. if it
2840 * happens something is really wrong -> recover */
2841 qeth_schedule_recovery(queue->card);
2842 return;
2843 }
2844 atomic_add(count, &queue->used_buffers);
2845 if (queue->card->options.performance_stats)
2846 queue->card->perf_stats.bufs_sent += count;
2847 }
2848
2849 static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
2850 {
2851 int index;
2852 int flush_cnt = 0;
2853 int q_was_packing = 0;
2854
2855 /*
2856 * check if weed have to switch to non-packing mode or if
2857 * we have to get a pci flag out on the queue
2858 */
2859 if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
2860 !atomic_read(&queue->set_pci_flags_count)) {
2861 if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
2862 QETH_OUT_Q_UNLOCKED) {
2863 /*
2864 * If we get in here, there was no action in
2865 * do_send_packet. So, we check if there is a
2866 * packing buffer to be flushed here.
2867 */
2868 netif_stop_queue(queue->card->dev);
2869 index = queue->next_buf_to_fill;
2870 q_was_packing = queue->do_pack;
2871 /* queue->do_pack may change */
2872 barrier();
2873 flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
2874 if (!flush_cnt &&
2875 !atomic_read(&queue->set_pci_flags_count))
2876 flush_cnt +=
2877 qeth_flush_buffers_on_no_pci(queue);
2878 if (queue->card->options.performance_stats &&
2879 q_was_packing)
2880 queue->card->perf_stats.bufs_sent_pack +=
2881 flush_cnt;
2882 if (flush_cnt)
2883 qeth_flush_buffers(queue, 1, index, flush_cnt);
2884 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
2885 }
2886 }
2887 }
2888
2889 void qeth_qdio_output_handler(struct ccw_device *ccwdev, unsigned int status,
2890 unsigned int qdio_error, unsigned int siga_error,
2891 unsigned int __queue, int first_element, int count,
2892 unsigned long card_ptr)
2893 {
2894 struct qeth_card *card = (struct qeth_card *) card_ptr;
2895 struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
2896 struct qeth_qdio_out_buffer *buffer;
2897 int i;
2898
2899 QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
2900 if (status & QDIO_STATUS_LOOK_FOR_ERROR) {
2901 if (status & QDIO_STATUS_ACTIVATE_CHECK_CONDITION) {
2902 QETH_DBF_TEXT(TRACE, 2, "achkcond");
2903 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
2904 QETH_DBF_TEXT_(TRACE, 2, "%08x", status);
2905 netif_stop_queue(card->dev);
2906 qeth_schedule_recovery(card);
2907 return;
2908 }
2909 }
2910 if (card->options.performance_stats) {
2911 card->perf_stats.outbound_handler_cnt++;
2912 card->perf_stats.outbound_handler_start_time =
2913 qeth_get_micros();
2914 }
2915 for (i = first_element; i < (first_element + count); ++i) {
2916 buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2917 /*we only handle the KICK_IT error by doing a recovery */
2918 if (qeth_handle_send_error(card, buffer,
2919 qdio_error, siga_error)
2920 == QETH_SEND_ERROR_KICK_IT){
2921 netif_stop_queue(card->dev);
2922 qeth_schedule_recovery(card);
2923 return;
2924 }
2925 qeth_clear_output_buffer(queue, buffer);
2926 }
2927 atomic_sub(count, &queue->used_buffers);
2928 /* check if we need to do something on this outbound queue */
2929 if (card->info.type != QETH_CARD_TYPE_IQD)
2930 qeth_check_outbound_queue(queue);
2931
2932 netif_wake_queue(queue->card->dev);
2933 if (card->options.performance_stats)
2934 card->perf_stats.outbound_handler_time += qeth_get_micros() -
2935 card->perf_stats.outbound_handler_start_time;
2936 }
2937 EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
2938
2939 int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
2940 {
2941 int cast_type = RTN_UNSPEC;
2942
2943 if (card->info.type == QETH_CARD_TYPE_OSN)
2944 return cast_type;
2945
2946 if (skb->dst && skb->dst->neighbour) {
2947 cast_type = skb->dst->neighbour->type;
2948 if ((cast_type == RTN_BROADCAST) ||
2949 (cast_type == RTN_MULTICAST) ||
2950 (cast_type == RTN_ANYCAST))
2951 return cast_type;
2952 else
2953 return RTN_UNSPEC;
2954 }
2955 /* try something else */
2956 if (skb->protocol == ETH_P_IPV6)
2957 return (skb_network_header(skb)[24] == 0xff) ?
2958 RTN_MULTICAST : 0;
2959 else if (skb->protocol == ETH_P_IP)
2960 return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
2961 RTN_MULTICAST : 0;
2962 /* ... */
2963 if (!memcmp(skb->data, skb->dev->broadcast, 6))
2964 return RTN_BROADCAST;
2965 else {
2966 u16 hdr_mac;
2967
2968 hdr_mac = *((u16 *)skb->data);
2969 /* tr multicast? */
2970 switch (card->info.link_type) {
2971 case QETH_LINK_TYPE_HSTR:
2972 case QETH_LINK_TYPE_LANE_TR:
2973 if ((hdr_mac == QETH_TR_MAC_NC) ||
2974 (hdr_mac == QETH_TR_MAC_C))
2975 return RTN_MULTICAST;
2976 break;
2977 /* eth or so multicast? */
2978 default:
2979 if ((hdr_mac == QETH_ETH_MAC_V4) ||
2980 (hdr_mac == QETH_ETH_MAC_V6))
2981 return RTN_MULTICAST;
2982 }
2983 }
2984 return cast_type;
2985 }
2986 EXPORT_SYMBOL_GPL(qeth_get_cast_type);
2987
2988 int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
2989 int ipv, int cast_type)
2990 {
2991 if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
2992 return card->qdio.default_out_queue;
2993 switch (card->qdio.no_out_queues) {
2994 case 4:
2995 if (cast_type && card->info.is_multicast_different)
2996 return card->info.is_multicast_different &
2997 (card->qdio.no_out_queues - 1);
2998 if (card->qdio.do_prio_queueing && (ipv == 4)) {
2999 const u8 tos = ip_hdr(skb)->tos;
3000
3001 if (card->qdio.do_prio_queueing ==
3002 QETH_PRIO_Q_ING_TOS) {
3003 if (tos & IP_TOS_NOTIMPORTANT)
3004 return 3;
3005 if (tos & IP_TOS_HIGHRELIABILITY)
3006 return 2;
3007 if (tos & IP_TOS_HIGHTHROUGHPUT)
3008 return 1;
3009 if (tos & IP_TOS_LOWDELAY)
3010 return 0;
3011 }
3012 if (card->qdio.do_prio_queueing ==
3013 QETH_PRIO_Q_ING_PREC)
3014 return 3 - (tos >> 6);
3015 } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
3016 /* TODO: IPv6!!! */
3017 }
3018 return card->qdio.default_out_queue;
3019 case 1: /* fallthrough for single-out-queue 1920-device */
3020 default:
3021 return card->qdio.default_out_queue;
3022 }
3023 }
3024 EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
3025
3026 int qeth_get_elements_no(struct qeth_card *card, void *hdr,
3027 struct sk_buff *skb, int elems)
3028 {
3029 int elements_needed = 0;
3030
3031 if (skb_shinfo(skb)->nr_frags > 0)
3032 elements_needed = (skb_shinfo(skb)->nr_frags + 1);
3033 if (elements_needed == 0)
3034 elements_needed = 1 + (((((unsigned long) hdr) % PAGE_SIZE)
3035 + skb->len) >> PAGE_SHIFT);
3036 if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
3037 PRINT_ERR("Invalid size of IP packet "
3038 "(Number=%d / Length=%d). Discarded.\n",
3039 (elements_needed+elems), skb->len);
3040 return 0;
3041 }
3042 return elements_needed;
3043 }
3044 EXPORT_SYMBOL_GPL(qeth_get_elements_no);
3045
3046 static inline void __qeth_fill_buffer(struct sk_buff *skb,
3047 struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill)
3048 {
3049 int length = skb->len;
3050 int length_here;
3051 int element;
3052 char *data;
3053 int first_lap ;
3054
3055 element = *next_element_to_fill;
3056 data = skb->data;
3057 first_lap = (is_tso == 0 ? 1 : 0);
3058
3059 while (length > 0) {
3060 /* length_here is the remaining amount of data in this page */
3061 length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
3062 if (length < length_here)
3063 length_here = length;
3064
3065 buffer->element[element].addr = data;
3066 buffer->element[element].length = length_here;
3067 length -= length_here;
3068 if (!length) {
3069 if (first_lap)
3070 buffer->element[element].flags = 0;
3071 else
3072 buffer->element[element].flags =
3073 SBAL_FLAGS_LAST_FRAG;
3074 } else {
3075 if (first_lap)
3076 buffer->element[element].flags =
3077 SBAL_FLAGS_FIRST_FRAG;
3078 else
3079 buffer->element[element].flags =
3080 SBAL_FLAGS_MIDDLE_FRAG;
3081 }
3082 data += length_here;
3083 element++;
3084 first_lap = 0;
3085 }
3086 *next_element_to_fill = element;
3087 }
3088
3089 static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
3090 struct qeth_qdio_out_buffer *buf, struct sk_buff *skb)
3091 {
3092 struct qdio_buffer *buffer;
3093 struct qeth_hdr_tso *hdr;
3094 int flush_cnt = 0, hdr_len, large_send = 0;
3095
3096 buffer = buf->buffer;
3097 atomic_inc(&skb->users);
3098 skb_queue_tail(&buf->skb_list, skb);
3099
3100 hdr = (struct qeth_hdr_tso *) skb->data;
3101 /*check first on TSO ....*/
3102 if (hdr->hdr.hdr.l3.id == QETH_HEADER_TYPE_TSO) {
3103 int element = buf->next_element_to_fill;
3104
3105 hdr_len = sizeof(struct qeth_hdr_tso) + hdr->ext.dg_hdr_len;
3106 /*fill first buffer entry only with header information */
3107 buffer->element[element].addr = skb->data;
3108 buffer->element[element].length = hdr_len;
3109 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
3110 buf->next_element_to_fill++;
3111 skb->data += hdr_len;
3112 skb->len -= hdr_len;
3113 large_send = 1;
3114 }
3115 if (skb_shinfo(skb)->nr_frags == 0)
3116 __qeth_fill_buffer(skb, buffer, large_send,
3117 (int *)&buf->next_element_to_fill);
3118 else
3119 __qeth_fill_buffer_frag(skb, buffer, large_send,
3120 (int *)&buf->next_element_to_fill);
3121
3122 if (!queue->do_pack) {
3123 QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
3124 /* set state to PRIMED -> will be flushed */
3125 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3126 flush_cnt = 1;
3127 } else {
3128 QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
3129 if (queue->card->options.performance_stats)
3130 queue->card->perf_stats.skbs_sent_pack++;
3131 if (buf->next_element_to_fill >=
3132 QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
3133 /*
3134 * packed buffer if full -> set state PRIMED
3135 * -> will be flushed
3136 */
3137 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3138 flush_cnt = 1;
3139 }
3140 }
3141 return flush_cnt;
3142 }
3143
3144 int qeth_do_send_packet_fast(struct qeth_card *card,
3145 struct qeth_qdio_out_q *queue, struct sk_buff *skb,
3146 struct qeth_hdr *hdr, int elements_needed,
3147 struct qeth_eddp_context *ctx)
3148 {
3149 struct qeth_qdio_out_buffer *buffer;
3150 int buffers_needed = 0;
3151 int flush_cnt = 0;
3152 int index;
3153
3154 /* spin until we get the queue ... */
3155 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3156 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3157 /* ... now we've got the queue */
3158 index = queue->next_buf_to_fill;
3159 buffer = &queue->bufs[queue->next_buf_to_fill];
3160 /*
3161 * check if buffer is empty to make sure that we do not 'overtake'
3162 * ourselves and try to fill a buffer that is already primed
3163 */
3164 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
3165 goto out;
3166 if (ctx == NULL)
3167 queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
3168 QDIO_MAX_BUFFERS_PER_Q;
3169 else {
3170 buffers_needed = qeth_eddp_check_buffers_for_context(queue,
3171 ctx);
3172 if (buffers_needed < 0)
3173 goto out;
3174 queue->next_buf_to_fill =
3175 (queue->next_buf_to_fill + buffers_needed) %
3176 QDIO_MAX_BUFFERS_PER_Q;
3177 }
3178 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3179 if (ctx == NULL) {
3180 qeth_fill_buffer(queue, buffer, skb);
3181 qeth_flush_buffers(queue, 0, index, 1);
3182 } else {
3183 flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
3184 WARN_ON(buffers_needed != flush_cnt);
3185 qeth_flush_buffers(queue, 0, index, flush_cnt);
3186 }
3187 return 0;
3188 out:
3189 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3190 return -EBUSY;
3191 }
3192 EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
3193
3194 int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
3195 struct sk_buff *skb, struct qeth_hdr *hdr,
3196 int elements_needed, struct qeth_eddp_context *ctx)
3197 {
3198 struct qeth_qdio_out_buffer *buffer;
3199 int start_index;
3200 int flush_count = 0;
3201 int do_pack = 0;
3202 int tmp;
3203 int rc = 0;
3204
3205 /* spin until we get the queue ... */
3206 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3207 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3208 start_index = queue->next_buf_to_fill;
3209 buffer = &queue->bufs[queue->next_buf_to_fill];
3210 /*
3211 * check if buffer is empty to make sure that we do not 'overtake'
3212 * ourselves and try to fill a buffer that is already primed
3213 */
3214 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
3215 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3216 return -EBUSY;
3217 }
3218 /* check if we need to switch packing state of this queue */
3219 qeth_switch_to_packing_if_needed(queue);
3220 if (queue->do_pack) {
3221 do_pack = 1;
3222 if (ctx == NULL) {
3223 /* does packet fit in current buffer? */
3224 if ((QETH_MAX_BUFFER_ELEMENTS(card) -
3225 buffer->next_element_to_fill) < elements_needed) {
3226 /* ... no -> set state PRIMED */
3227 atomic_set(&buffer->state,
3228 QETH_QDIO_BUF_PRIMED);
3229 flush_count++;
3230 queue->next_buf_to_fill =
3231 (queue->next_buf_to_fill + 1) %
3232 QDIO_MAX_BUFFERS_PER_Q;
3233 buffer = &queue->bufs[queue->next_buf_to_fill];
3234 /* we did a step forward, so check buffer state
3235 * again */
3236 if (atomic_read(&buffer->state) !=
3237 QETH_QDIO_BUF_EMPTY){
3238 qeth_flush_buffers(queue, 0,
3239 start_index, flush_count);
3240 atomic_set(&queue->state,
3241 QETH_OUT_Q_UNLOCKED);
3242 return -EBUSY;
3243 }
3244 }
3245 } else {
3246 /* check if we have enough elements (including following
3247 * free buffers) to handle eddp context */
3248 if (qeth_eddp_check_buffers_for_context(queue, ctx)
3249 < 0) {
3250 if (net_ratelimit())
3251 PRINT_WARN("eddp tx_dropped 1\n");
3252 rc = -EBUSY;
3253 goto out;
3254 }
3255 }
3256 }
3257 if (ctx == NULL)
3258 tmp = qeth_fill_buffer(queue, buffer, skb);
3259 else {
3260 tmp = qeth_eddp_fill_buffer(queue, ctx,
3261 queue->next_buf_to_fill);
3262 if (tmp < 0) {
3263 PRINT_ERR("eddp tx_dropped 2\n");
3264 rc = -EBUSY;
3265 goto out;
3266 }
3267 }
3268 queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
3269 QDIO_MAX_BUFFERS_PER_Q;
3270 flush_count += tmp;
3271 out:
3272 if (flush_count)
3273 qeth_flush_buffers(queue, 0, start_index, flush_count);
3274 else if (!atomic_read(&queue->set_pci_flags_count))
3275 atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
3276 /*
3277 * queue->state will go from LOCKED -> UNLOCKED or from
3278 * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
3279 * (switch packing state or flush buffer to get another pci flag out).
3280 * In that case we will enter this loop
3281 */
3282 while (atomic_dec_return(&queue->state)) {
3283 flush_count = 0;
3284 start_index = queue->next_buf_to_fill;
3285 /* check if we can go back to non-packing state */
3286 flush_count += qeth_switch_to_nonpacking_if_needed(queue);
3287 /*
3288 * check if we need to flush a packing buffer to get a pci
3289 * flag out on the queue
3290 */
3291 if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
3292 flush_count += qeth_flush_buffers_on_no_pci(queue);
3293 if (flush_count)
3294 qeth_flush_buffers(queue, 0, start_index, flush_count);
3295 }
3296 /* at this point the queue is UNLOCKED again */
3297 if (queue->card->options.performance_stats && do_pack)
3298 queue->card->perf_stats.bufs_sent_pack += flush_count;
3299
3300 return rc;
3301 }
3302 EXPORT_SYMBOL_GPL(qeth_do_send_packet);
3303
3304 static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
3305 struct qeth_reply *reply, unsigned long data)
3306 {
3307 struct qeth_ipa_cmd *cmd;
3308 struct qeth_ipacmd_setadpparms *setparms;
3309
3310 QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
3311
3312 cmd = (struct qeth_ipa_cmd *) data;
3313 setparms = &(cmd->data.setadapterparms);
3314
3315 qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
3316 if (cmd->hdr.return_code) {
3317 QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
3318 setparms->data.mode = SET_PROMISC_MODE_OFF;
3319 }
3320 card->info.promisc_mode = setparms->data.mode;
3321 return 0;
3322 }
3323
3324 void qeth_setadp_promisc_mode(struct qeth_card *card)
3325 {
3326 enum qeth_ipa_promisc_modes mode;
3327 struct net_device *dev = card->dev;
3328 struct qeth_cmd_buffer *iob;
3329 struct qeth_ipa_cmd *cmd;
3330
3331 QETH_DBF_TEXT(TRACE, 4, "setprom");
3332
3333 if (((dev->flags & IFF_PROMISC) &&
3334 (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
3335 (!(dev->flags & IFF_PROMISC) &&
3336 (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
3337 return;
3338 mode = SET_PROMISC_MODE_OFF;
3339 if (dev->flags & IFF_PROMISC)
3340 mode = SET_PROMISC_MODE_ON;
3341 QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
3342
3343 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
3344 sizeof(struct qeth_ipacmd_setadpparms));
3345 cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
3346 cmd->data.setadapterparms.data.mode = mode;
3347 qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
3348 }
3349 EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
3350
3351 int qeth_change_mtu(struct net_device *dev, int new_mtu)
3352 {
3353 struct qeth_card *card;
3354 char dbf_text[15];
3355
3356 card = netdev_priv(dev);
3357
3358 QETH_DBF_TEXT(TRACE, 4, "chgmtu");
3359 sprintf(dbf_text, "%8x", new_mtu);
3360 QETH_DBF_TEXT(TRACE, 4, dbf_text);
3361
3362 if (new_mtu < 64)
3363 return -EINVAL;
3364 if (new_mtu > 65535)
3365 return -EINVAL;
3366 if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
3367 (!qeth_mtu_is_valid(card, new_mtu)))
3368 return -EINVAL;
3369 dev->mtu = new_mtu;
3370 return 0;
3371 }
3372 EXPORT_SYMBOL_GPL(qeth_change_mtu);
3373
3374 struct net_device_stats *qeth_get_stats(struct net_device *dev)
3375 {
3376 struct qeth_card *card;
3377
3378 card = netdev_priv(dev);
3379
3380 QETH_DBF_TEXT(TRACE, 5, "getstat");
3381
3382 return &card->stats;
3383 }
3384 EXPORT_SYMBOL_GPL(qeth_get_stats);
3385
3386 static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
3387 struct qeth_reply *reply, unsigned long data)
3388 {
3389 struct qeth_ipa_cmd *cmd;
3390
3391 QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
3392
3393 cmd = (struct qeth_ipa_cmd *) data;
3394 if (!card->options.layer2 ||
3395 !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
3396 memcpy(card->dev->dev_addr,
3397 &cmd->data.setadapterparms.data.change_addr.addr,
3398 OSA_ADDR_LEN);
3399 card->info.mac_bits |= QETH_LAYER2_MAC_READ;
3400 }
3401 qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
3402 return 0;
3403 }
3404
3405 int qeth_setadpparms_change_macaddr(struct qeth_card *card)
3406 {
3407 int rc;
3408 struct qeth_cmd_buffer *iob;
3409 struct qeth_ipa_cmd *cmd;
3410
3411 QETH_DBF_TEXT(TRACE, 4, "chgmac");
3412
3413 iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
3414 sizeof(struct qeth_ipacmd_setadpparms));
3415 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3416 cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
3417 cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
3418 memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
3419 card->dev->dev_addr, OSA_ADDR_LEN);
3420 rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
3421 NULL);
3422 return rc;
3423 }
3424 EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
3425
3426 void qeth_tx_timeout(struct net_device *dev)
3427 {
3428 struct qeth_card *card;
3429
3430 card = netdev_priv(dev);
3431 card->stats.tx_errors++;
3432 qeth_schedule_recovery(card);
3433 }
3434 EXPORT_SYMBOL_GPL(qeth_tx_timeout);
3435
3436 int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
3437 {
3438 struct qeth_card *card = netdev_priv(dev);
3439 int rc = 0;
3440
3441 switch (regnum) {
3442 case MII_BMCR: /* Basic mode control register */
3443 rc = BMCR_FULLDPLX;
3444 if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
3445 (card->info.link_type != QETH_LINK_TYPE_OSN) &&
3446 (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
3447 rc |= BMCR_SPEED100;
3448 break;
3449 case MII_BMSR: /* Basic mode status register */
3450 rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
3451 BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
3452 BMSR_100BASE4;
3453 break;
3454 case MII_PHYSID1: /* PHYS ID 1 */
3455 rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
3456 dev->dev_addr[2];
3457 rc = (rc >> 5) & 0xFFFF;
3458 break;
3459 case MII_PHYSID2: /* PHYS ID 2 */
3460 rc = (dev->dev_addr[2] << 10) & 0xFFFF;
3461 break;
3462 case MII_ADVERTISE: /* Advertisement control reg */
3463 rc = ADVERTISE_ALL;
3464 break;
3465 case MII_LPA: /* Link partner ability reg */
3466 rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
3467 LPA_100BASE4 | LPA_LPACK;
3468 break;
3469 case MII_EXPANSION: /* Expansion register */
3470 break;
3471 case MII_DCOUNTER: /* disconnect counter */
3472 break;
3473 case MII_FCSCOUNTER: /* false carrier counter */
3474 break;
3475 case MII_NWAYTEST: /* N-way auto-neg test register */
3476 break;
3477 case MII_RERRCOUNTER: /* rx error counter */
3478 rc = card->stats.rx_errors;
3479 break;
3480 case MII_SREVISION: /* silicon revision */
3481 break;
3482 case MII_RESV1: /* reserved 1 */
3483 break;
3484 case MII_LBRERROR: /* loopback, rx, bypass error */
3485 break;
3486 case MII_PHYADDR: /* physical address */
3487 break;
3488 case MII_RESV2: /* reserved 2 */
3489 break;
3490 case MII_TPISTATUS: /* TPI status for 10mbps */
3491 break;
3492 case MII_NCONFIG: /* network interface config */
3493 break;
3494 default:
3495 break;
3496 }
3497 return rc;
3498 }
3499 EXPORT_SYMBOL_GPL(qeth_mdio_read);
3500
3501 static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
3502 struct qeth_cmd_buffer *iob, int len,
3503 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
3504 unsigned long),
3505 void *reply_param)
3506 {
3507 u16 s1, s2;
3508
3509 QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
3510
3511 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
3512 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
3513 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
3514 /* adjust PDU length fields in IPA_PDU_HEADER */
3515 s1 = (u32) IPA_PDU_HEADER_SIZE + len;
3516 s2 = (u32) len;
3517 memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
3518 memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
3519 memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
3520 memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
3521 return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
3522 reply_cb, reply_param);
3523 }
3524
3525 static int qeth_snmp_command_cb(struct qeth_card *card,
3526 struct qeth_reply *reply, unsigned long sdata)
3527 {
3528 struct qeth_ipa_cmd *cmd;
3529 struct qeth_arp_query_info *qinfo;
3530 struct qeth_snmp_cmd *snmp;
3531 unsigned char *data;
3532 __u16 data_len;
3533
3534 QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
3535
3536 cmd = (struct qeth_ipa_cmd *) sdata;
3537 data = (unsigned char *)((char *)cmd - reply->offset);
3538 qinfo = (struct qeth_arp_query_info *) reply->param;
3539 snmp = &cmd->data.setadapterparms.data.snmp;
3540
3541 if (cmd->hdr.return_code) {
3542 QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
3543 return 0;
3544 }
3545 if (cmd->data.setadapterparms.hdr.return_code) {
3546 cmd->hdr.return_code =
3547 cmd->data.setadapterparms.hdr.return_code;
3548 QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
3549 return 0;
3550 }
3551 data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
3552 if (cmd->data.setadapterparms.hdr.seq_no == 1)
3553 data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
3554 else
3555 data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
3556
3557 /* check if there is enough room in userspace */
3558 if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
3559 QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
3560 cmd->hdr.return_code = -ENOMEM;
3561 return 0;
3562 }
3563 QETH_DBF_TEXT_(TRACE, 4, "snore%i",
3564 cmd->data.setadapterparms.hdr.used_total);
3565 QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
3566 cmd->data.setadapterparms.hdr.seq_no);
3567 /*copy entries to user buffer*/
3568 if (cmd->data.setadapterparms.hdr.seq_no == 1) {
3569 memcpy(qinfo->udata + qinfo->udata_offset,
3570 (char *)snmp,
3571 data_len + offsetof(struct qeth_snmp_cmd, data));
3572 qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
3573 } else {
3574 memcpy(qinfo->udata + qinfo->udata_offset,
3575 (char *)&snmp->request, data_len);
3576 }
3577 qinfo->udata_offset += data_len;
3578 /* check if all replies received ... */
3579 QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
3580 cmd->data.setadapterparms.hdr.used_total);
3581 QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
3582 cmd->data.setadapterparms.hdr.seq_no);
3583 if (cmd->data.setadapterparms.hdr.seq_no <
3584 cmd->data.setadapterparms.hdr.used_total)
3585 return 1;
3586 return 0;
3587 }
3588
3589 int qeth_snmp_command(struct qeth_card *card, char __user *udata)
3590 {
3591 struct qeth_cmd_buffer *iob;
3592 struct qeth_ipa_cmd *cmd;
3593 struct qeth_snmp_ureq *ureq;
3594 int req_len;
3595 struct qeth_arp_query_info qinfo = {0, };
3596 int rc = 0;
3597
3598 QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
3599
3600 if (card->info.guestlan)
3601 return -EOPNOTSUPP;
3602
3603 if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
3604 (!card->options.layer2)) {
3605 PRINT_WARN("SNMP Query MIBS not supported "
3606 "on %s!\n", QETH_CARD_IFNAME(card));
3607 return -EOPNOTSUPP;
3608 }
3609 /* skip 4 bytes (data_len struct member) to get req_len */
3610 if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
3611 return -EFAULT;
3612 ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
3613 if (!ureq) {
3614 QETH_DBF_TEXT(TRACE, 2, "snmpnome");
3615 return -ENOMEM;
3616 }
3617 if (copy_from_user(ureq, udata,
3618 req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
3619 kfree(ureq);
3620 return -EFAULT;
3621 }
3622 qinfo.udata_len = ureq->hdr.data_len;
3623 qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
3624 if (!qinfo.udata) {
3625 kfree(ureq);
3626 return -ENOMEM;
3627 }
3628 qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
3629
3630 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
3631 QETH_SNMP_SETADP_CMDLENGTH + req_len);
3632 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3633 memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
3634 rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
3635 qeth_snmp_command_cb, (void *)&qinfo);
3636 if (rc)
3637 PRINT_WARN("SNMP command failed on %s: (0x%x)\n",
3638 QETH_CARD_IFNAME(card), rc);
3639 else {
3640 if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
3641 rc = -EFAULT;
3642 }
3643
3644 kfree(ureq);
3645 kfree(qinfo.udata);
3646 return rc;
3647 }
3648 EXPORT_SYMBOL_GPL(qeth_snmp_command);
3649
3650 static inline int qeth_get_qdio_q_format(struct qeth_card *card)
3651 {
3652 switch (card->info.type) {
3653 case QETH_CARD_TYPE_IQD:
3654 return 2;
3655 default:
3656 return 0;
3657 }
3658 }
3659
3660 static int qeth_qdio_establish(struct qeth_card *card)
3661 {
3662 struct qdio_initialize init_data;
3663 char *qib_param_field;
3664 struct qdio_buffer **in_sbal_ptrs;
3665 struct qdio_buffer **out_sbal_ptrs;
3666 int i, j, k;
3667 int rc = 0;
3668
3669 QETH_DBF_TEXT(SETUP, 2, "qdioest");
3670
3671 qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
3672 GFP_KERNEL);
3673 if (!qib_param_field)
3674 return -ENOMEM;
3675
3676 qeth_create_qib_param_field(card, qib_param_field);
3677 qeth_create_qib_param_field_blkt(card, qib_param_field);
3678
3679 in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
3680 GFP_KERNEL);
3681 if (!in_sbal_ptrs) {
3682 kfree(qib_param_field);
3683 return -ENOMEM;
3684 }
3685 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
3686 in_sbal_ptrs[i] = (struct qdio_buffer *)
3687 virt_to_phys(card->qdio.in_q->bufs[i].buffer);
3688
3689 out_sbal_ptrs =
3690 kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
3691 sizeof(void *), GFP_KERNEL);
3692 if (!out_sbal_ptrs) {
3693 kfree(in_sbal_ptrs);
3694 kfree(qib_param_field);
3695 return -ENOMEM;
3696 }
3697 for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
3698 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
3699 out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
3700 card->qdio.out_qs[i]->bufs[j].buffer);
3701 }
3702
3703 memset(&init_data, 0, sizeof(struct qdio_initialize));
3704 init_data.cdev = CARD_DDEV(card);
3705 init_data.q_format = qeth_get_qdio_q_format(card);
3706 init_data.qib_param_field_format = 0;
3707 init_data.qib_param_field = qib_param_field;
3708 init_data.min_input_threshold = QETH_MIN_INPUT_THRESHOLD;
3709 init_data.max_input_threshold = QETH_MAX_INPUT_THRESHOLD;
3710 init_data.min_output_threshold = QETH_MIN_OUTPUT_THRESHOLD;
3711 init_data.max_output_threshold = QETH_MAX_OUTPUT_THRESHOLD;
3712 init_data.no_input_qs = 1;
3713 init_data.no_output_qs = card->qdio.no_out_queues;
3714 init_data.input_handler = card->discipline.input_handler;
3715 init_data.output_handler = card->discipline.output_handler;
3716 init_data.int_parm = (unsigned long) card;
3717 init_data.flags = QDIO_INBOUND_0COPY_SBALS |
3718 QDIO_OUTBOUND_0COPY_SBALS |
3719 QDIO_USE_OUTBOUND_PCIS;
3720 init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
3721 init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
3722
3723 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
3724 QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
3725 rc = qdio_initialize(&init_data);
3726 if (rc)
3727 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
3728 }
3729 kfree(out_sbal_ptrs);
3730 kfree(in_sbal_ptrs);
3731 kfree(qib_param_field);
3732 return rc;
3733 }
3734
3735 static void qeth_core_free_card(struct qeth_card *card)
3736 {
3737
3738 QETH_DBF_TEXT(SETUP, 2, "freecrd");
3739 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
3740 qeth_clean_channel(&card->read);
3741 qeth_clean_channel(&card->write);
3742 if (card->dev)
3743 free_netdev(card->dev);
3744 kfree(card->ip_tbd_list);
3745 qeth_free_qdio_buffers(card);
3746 kfree(card);
3747 }
3748
3749 static struct ccw_device_id qeth_ids[] = {
3750 {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
3751 {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
3752 {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
3753 {},
3754 };
3755 MODULE_DEVICE_TABLE(ccw, qeth_ids);
3756
3757 static struct ccw_driver qeth_ccw_driver = {
3758 .name = "qeth",
3759 .ids = qeth_ids,
3760 .probe = ccwgroup_probe_ccwdev,
3761 .remove = ccwgroup_remove_ccwdev,
3762 };
3763
3764 static int qeth_core_driver_group(const char *buf, struct device *root_dev,
3765 unsigned long driver_id)
3766 {
3767 return ccwgroup_create_from_string(root_dev, driver_id,
3768 &qeth_ccw_driver, 3, buf);
3769 }
3770
3771 int qeth_core_hardsetup_card(struct qeth_card *card)
3772 {
3773 int retries = 3;
3774 int mpno;
3775 int rc;
3776
3777 QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
3778 atomic_set(&card->force_alloc_skb, 0);
3779 retry:
3780 if (retries < 3) {
3781 PRINT_WARN("Retrying to do IDX activates.\n");
3782 ccw_device_set_offline(CARD_DDEV(card));
3783 ccw_device_set_offline(CARD_WDEV(card));
3784 ccw_device_set_offline(CARD_RDEV(card));
3785 ccw_device_set_online(CARD_RDEV(card));
3786 ccw_device_set_online(CARD_WDEV(card));
3787 ccw_device_set_online(CARD_DDEV(card));
3788 }
3789 rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
3790 if (rc == -ERESTARTSYS) {
3791 QETH_DBF_TEXT(SETUP, 2, "break1");
3792 return rc;
3793 } else if (rc) {
3794 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
3795 if (--retries < 0)
3796 goto out;
3797 else
3798 goto retry;
3799 }
3800
3801 rc = qeth_get_unitaddr(card);
3802 if (rc) {
3803 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
3804 return rc;
3805 }
3806 mpno = qdio_get_ssqd_pct(CARD_DDEV(card));
3807 if (mpno)
3808 mpno = min(mpno - 1, QETH_MAX_PORTNO);
3809 if (card->info.portno > mpno) {
3810 PRINT_ERR("Device %s does not offer port number %d \n.",
3811 CARD_BUS_ID(card), card->info.portno);
3812 rc = -ENODEV;
3813 goto out;
3814 }
3815 qeth_init_tokens(card);
3816 qeth_init_func_level(card);
3817 rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
3818 if (rc == -ERESTARTSYS) {
3819 QETH_DBF_TEXT(SETUP, 2, "break2");
3820 return rc;
3821 } else if (rc) {
3822 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
3823 if (--retries < 0)
3824 goto out;
3825 else
3826 goto retry;
3827 }
3828 rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
3829 if (rc == -ERESTARTSYS) {
3830 QETH_DBF_TEXT(SETUP, 2, "break3");
3831 return rc;
3832 } else if (rc) {
3833 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
3834 if (--retries < 0)
3835 goto out;
3836 else
3837 goto retry;
3838 }
3839 rc = qeth_mpc_initialize(card);
3840 if (rc) {
3841 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
3842 goto out;
3843 }
3844 return 0;
3845 out:
3846 PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
3847 return rc;
3848 }
3849 EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
3850
3851 static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
3852 struct sk_buff **pskb, int offset, int *pfrag, int data_len)
3853 {
3854 struct page *page = virt_to_page(element->addr);
3855 if (*pskb == NULL) {
3856 /* the upper protocol layers assume that there is data in the
3857 * skb itself. Copy a small amount (64 bytes) to make them
3858 * happy. */
3859 *pskb = dev_alloc_skb(64 + ETH_HLEN);
3860 if (!(*pskb))
3861 return -ENOMEM;
3862 skb_reserve(*pskb, ETH_HLEN);
3863 if (data_len <= 64) {
3864 memcpy(skb_put(*pskb, data_len), element->addr + offset,
3865 data_len);
3866 } else {
3867 get_page(page);
3868 memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
3869 skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
3870 data_len - 64);
3871 (*pskb)->data_len += data_len - 64;
3872 (*pskb)->len += data_len - 64;
3873 (*pskb)->truesize += data_len - 64;
3874 (*pfrag)++;
3875 }
3876 } else {
3877 get_page(page);
3878 skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
3879 (*pskb)->data_len += data_len;
3880 (*pskb)->len += data_len;
3881 (*pskb)->truesize += data_len;
3882 (*pfrag)++;
3883 }
3884 return 0;
3885 }
3886
3887 struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
3888 struct qdio_buffer *buffer,
3889 struct qdio_buffer_element **__element, int *__offset,
3890 struct qeth_hdr **hdr)
3891 {
3892 struct qdio_buffer_element *element = *__element;
3893 int offset = *__offset;
3894 struct sk_buff *skb = NULL;
3895 int skb_len;
3896 void *data_ptr;
3897 int data_len;
3898 int headroom = 0;
3899 int use_rx_sg = 0;
3900 int frag = 0;
3901
3902 /* qeth_hdr must not cross element boundaries */
3903 if (element->length < offset + sizeof(struct qeth_hdr)) {
3904 if (qeth_is_last_sbale(element))
3905 return NULL;
3906 element++;
3907 offset = 0;
3908 if (element->length < sizeof(struct qeth_hdr))
3909 return NULL;
3910 }
3911 *hdr = element->addr + offset;
3912
3913 offset += sizeof(struct qeth_hdr);
3914 if (card->options.layer2) {
3915 if (card->info.type == QETH_CARD_TYPE_OSN) {
3916 skb_len = (*hdr)->hdr.osn.pdu_length;
3917 headroom = sizeof(struct qeth_hdr);
3918 } else {
3919 skb_len = (*hdr)->hdr.l2.pkt_length;
3920 }
3921 } else {
3922 skb_len = (*hdr)->hdr.l3.length;
3923 if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
3924 (card->info.link_type == QETH_LINK_TYPE_HSTR))
3925 headroom = TR_HLEN;
3926 else
3927 headroom = ETH_HLEN;
3928 }
3929
3930 if (!skb_len)
3931 return NULL;
3932
3933 if ((skb_len >= card->options.rx_sg_cb) &&
3934 (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
3935 (!atomic_read(&card->force_alloc_skb))) {
3936 use_rx_sg = 1;
3937 } else {
3938 skb = dev_alloc_skb(skb_len + headroom);
3939 if (!skb)
3940 goto no_mem;
3941 if (headroom)
3942 skb_reserve(skb, headroom);
3943 }
3944
3945 data_ptr = element->addr + offset;
3946 while (skb_len) {
3947 data_len = min(skb_len, (int)(element->length - offset));
3948 if (data_len) {
3949 if (use_rx_sg) {
3950 if (qeth_create_skb_frag(element, &skb, offset,
3951 &frag, data_len))
3952 goto no_mem;
3953 } else {
3954 memcpy(skb_put(skb, data_len), data_ptr,
3955 data_len);
3956 }
3957 }
3958 skb_len -= data_len;
3959 if (skb_len) {
3960 if (qeth_is_last_sbale(element)) {
3961 QETH_DBF_TEXT(TRACE, 4, "unexeob");
3962 QETH_DBF_TEXT_(TRACE, 4, "%s",
3963 CARD_BUS_ID(card));
3964 QETH_DBF_TEXT(QERR, 2, "unexeob");
3965 QETH_DBF_TEXT_(QERR, 2, "%s",
3966 CARD_BUS_ID(card));
3967 QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
3968 dev_kfree_skb_any(skb);
3969 card->stats.rx_errors++;
3970 return NULL;
3971 }
3972 element++;
3973 offset = 0;
3974 data_ptr = element->addr;
3975 } else {
3976 offset += data_len;
3977 }
3978 }
3979 *__element = element;
3980 *__offset = offset;
3981 if (use_rx_sg && card->options.performance_stats) {
3982 card->perf_stats.sg_skbs_rx++;
3983 card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
3984 }
3985 return skb;
3986 no_mem:
3987 if (net_ratelimit()) {
3988 PRINT_WARN("No memory for packet received on %s.\n",
3989 QETH_CARD_IFNAME(card));
3990 QETH_DBF_TEXT(TRACE, 2, "noskbmem");
3991 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
3992 }
3993 card->stats.rx_dropped++;
3994 return NULL;
3995 }
3996 EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
3997
3998 static void qeth_unregister_dbf_views(void)
3999 {
4000 int x;
4001 for (x = 0; x < QETH_DBF_INFOS; x++) {
4002 debug_unregister(qeth_dbf[x].id);
4003 qeth_dbf[x].id = NULL;
4004 }
4005 }
4006
4007 void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *text, ...)
4008 {
4009 char dbf_txt_buf[32];
4010
4011 if (level > (qeth_dbf[dbf_nix].id)->level)
4012 return;
4013 snprintf(dbf_txt_buf, sizeof(dbf_txt_buf), text);
4014 debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
4015
4016 }
4017 EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
4018
4019 static int qeth_register_dbf_views(void)
4020 {
4021 int ret;
4022 int x;
4023
4024 for (x = 0; x < QETH_DBF_INFOS; x++) {
4025 /* register the areas */
4026 qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
4027 qeth_dbf[x].pages,
4028 qeth_dbf[x].areas,
4029 qeth_dbf[x].len);
4030 if (qeth_dbf[x].id == NULL) {
4031 qeth_unregister_dbf_views();
4032 return -ENOMEM;
4033 }
4034
4035 /* register a view */
4036 ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
4037 if (ret) {
4038 qeth_unregister_dbf_views();
4039 return ret;
4040 }
4041
4042 /* set a passing level */
4043 debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
4044 }
4045
4046 return 0;
4047 }
4048
4049 int qeth_core_load_discipline(struct qeth_card *card,
4050 enum qeth_discipline_id discipline)
4051 {
4052 int rc = 0;
4053 switch (discipline) {
4054 case QETH_DISCIPLINE_LAYER3:
4055 card->discipline.ccwgdriver = try_then_request_module(
4056 symbol_get(qeth_l3_ccwgroup_driver),
4057 "qeth_l3");
4058 break;
4059 case QETH_DISCIPLINE_LAYER2:
4060 card->discipline.ccwgdriver = try_then_request_module(
4061 symbol_get(qeth_l2_ccwgroup_driver),
4062 "qeth_l2");
4063 break;
4064 }
4065 if (!card->discipline.ccwgdriver) {
4066 PRINT_ERR("Support for discipline %d not present\n",
4067 discipline);
4068 rc = -EINVAL;
4069 }
4070 return rc;
4071 }
4072
4073 void qeth_core_free_discipline(struct qeth_card *card)
4074 {
4075 if (card->options.layer2)
4076 symbol_put(qeth_l2_ccwgroup_driver);
4077 else
4078 symbol_put(qeth_l3_ccwgroup_driver);
4079 card->discipline.ccwgdriver = NULL;
4080 }
4081
4082 static int qeth_core_probe_device(struct ccwgroup_device *gdev)
4083 {
4084 struct qeth_card *card;
4085 struct device *dev;
4086 int rc;
4087 unsigned long flags;
4088
4089 QETH_DBF_TEXT(SETUP, 2, "probedev");
4090
4091 dev = &gdev->dev;
4092 if (!get_device(dev))
4093 return -ENODEV;
4094
4095 QETH_DBF_TEXT_(SETUP, 2, "%s", gdev->dev.bus_id);
4096
4097 card = qeth_alloc_card();
4098 if (!card) {
4099 QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
4100 rc = -ENOMEM;
4101 goto err_dev;
4102 }
4103 card->read.ccwdev = gdev->cdev[0];
4104 card->write.ccwdev = gdev->cdev[1];
4105 card->data.ccwdev = gdev->cdev[2];
4106 dev_set_drvdata(&gdev->dev, card);
4107 card->gdev = gdev;
4108 gdev->cdev[0]->handler = qeth_irq;
4109 gdev->cdev[1]->handler = qeth_irq;
4110 gdev->cdev[2]->handler = qeth_irq;
4111
4112 rc = qeth_determine_card_type(card);
4113 if (rc) {
4114 PRINT_WARN("%s: not a valid card type\n", __func__);
4115 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
4116 goto err_card;
4117 }
4118 rc = qeth_setup_card(card);
4119 if (rc) {
4120 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
4121 goto err_card;
4122 }
4123
4124 if (card->info.type == QETH_CARD_TYPE_OSN) {
4125 rc = qeth_core_create_osn_attributes(dev);
4126 if (rc)
4127 goto err_card;
4128 rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
4129 if (rc) {
4130 qeth_core_remove_osn_attributes(dev);
4131 goto err_card;
4132 }
4133 rc = card->discipline.ccwgdriver->probe(card->gdev);
4134 if (rc) {
4135 qeth_core_free_discipline(card);
4136 qeth_core_remove_osn_attributes(dev);
4137 goto err_card;
4138 }
4139 } else {
4140 rc = qeth_core_create_device_attributes(dev);
4141 if (rc)
4142 goto err_card;
4143 }
4144
4145 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4146 list_add_tail(&card->list, &qeth_core_card_list.list);
4147 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4148 return 0;
4149
4150 err_card:
4151 qeth_core_free_card(card);
4152 err_dev:
4153 put_device(dev);
4154 return rc;
4155 }
4156
4157 static void qeth_core_remove_device(struct ccwgroup_device *gdev)
4158 {
4159 unsigned long flags;
4160 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4161
4162 if (card->discipline.ccwgdriver) {
4163 card->discipline.ccwgdriver->remove(gdev);
4164 qeth_core_free_discipline(card);
4165 }
4166
4167 if (card->info.type == QETH_CARD_TYPE_OSN) {
4168 qeth_core_remove_osn_attributes(&gdev->dev);
4169 } else {
4170 qeth_core_remove_device_attributes(&gdev->dev);
4171 }
4172 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4173 list_del(&card->list);
4174 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4175 qeth_core_free_card(card);
4176 dev_set_drvdata(&gdev->dev, NULL);
4177 put_device(&gdev->dev);
4178 return;
4179 }
4180
4181 static int qeth_core_set_online(struct ccwgroup_device *gdev)
4182 {
4183 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4184 int rc = 0;
4185 int def_discipline;
4186
4187 if (!card->discipline.ccwgdriver) {
4188 if (card->info.type == QETH_CARD_TYPE_IQD)
4189 def_discipline = QETH_DISCIPLINE_LAYER3;
4190 else
4191 def_discipline = QETH_DISCIPLINE_LAYER2;
4192 rc = qeth_core_load_discipline(card, def_discipline);
4193 if (rc)
4194 goto err;
4195 rc = card->discipline.ccwgdriver->probe(card->gdev);
4196 if (rc)
4197 goto err;
4198 }
4199 rc = card->discipline.ccwgdriver->set_online(gdev);
4200 err:
4201 return rc;
4202 }
4203
4204 static int qeth_core_set_offline(struct ccwgroup_device *gdev)
4205 {
4206 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4207 return card->discipline.ccwgdriver->set_offline(gdev);
4208 }
4209
4210 static void qeth_core_shutdown(struct ccwgroup_device *gdev)
4211 {
4212 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4213 if (card->discipline.ccwgdriver &&
4214 card->discipline.ccwgdriver->shutdown)
4215 card->discipline.ccwgdriver->shutdown(gdev);
4216 }
4217
4218 static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
4219 .owner = THIS_MODULE,
4220 .name = "qeth",
4221 .driver_id = 0xD8C5E3C8,
4222 .probe = qeth_core_probe_device,
4223 .remove = qeth_core_remove_device,
4224 .set_online = qeth_core_set_online,
4225 .set_offline = qeth_core_set_offline,
4226 .shutdown = qeth_core_shutdown,
4227 };
4228
4229 static ssize_t
4230 qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
4231 size_t count)
4232 {
4233 int err;
4234 err = qeth_core_driver_group(buf, qeth_core_root_dev,
4235 qeth_core_ccwgroup_driver.driver_id);
4236 if (err)
4237 return err;
4238 else
4239 return count;
4240 }
4241
4242 static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
4243
4244 static struct {
4245 const char str[ETH_GSTRING_LEN];
4246 } qeth_ethtool_stats_keys[] = {
4247 /* 0 */{"rx skbs"},
4248 {"rx buffers"},
4249 {"tx skbs"},
4250 {"tx buffers"},
4251 {"tx skbs no packing"},
4252 {"tx buffers no packing"},
4253 {"tx skbs packing"},
4254 {"tx buffers packing"},
4255 {"tx sg skbs"},
4256 {"tx sg frags"},
4257 /* 10 */{"rx sg skbs"},
4258 {"rx sg frags"},
4259 {"rx sg page allocs"},
4260 {"tx large kbytes"},
4261 {"tx large count"},
4262 {"tx pk state ch n->p"},
4263 {"tx pk state ch p->n"},
4264 {"tx pk watermark low"},
4265 {"tx pk watermark high"},
4266 {"queue 0 buffer usage"},
4267 /* 20 */{"queue 1 buffer usage"},
4268 {"queue 2 buffer usage"},
4269 {"queue 3 buffer usage"},
4270 {"rx handler time"},
4271 {"rx handler count"},
4272 {"rx do_QDIO time"},
4273 {"rx do_QDIO count"},
4274 {"tx handler time"},
4275 {"tx handler count"},
4276 {"tx time"},
4277 /* 30 */{"tx count"},
4278 {"tx do_QDIO time"},
4279 {"tx do_QDIO count"},
4280 };
4281
4282 int qeth_core_get_stats_count(struct net_device *dev)
4283 {
4284 return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
4285 }
4286 EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
4287
4288 void qeth_core_get_ethtool_stats(struct net_device *dev,
4289 struct ethtool_stats *stats, u64 *data)
4290 {
4291 struct qeth_card *card = netdev_priv(dev);
4292 data[0] = card->stats.rx_packets -
4293 card->perf_stats.initial_rx_packets;
4294 data[1] = card->perf_stats.bufs_rec;
4295 data[2] = card->stats.tx_packets -
4296 card->perf_stats.initial_tx_packets;
4297 data[3] = card->perf_stats.bufs_sent;
4298 data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
4299 - card->perf_stats.skbs_sent_pack;
4300 data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
4301 data[6] = card->perf_stats.skbs_sent_pack;
4302 data[7] = card->perf_stats.bufs_sent_pack;
4303 data[8] = card->perf_stats.sg_skbs_sent;
4304 data[9] = card->perf_stats.sg_frags_sent;
4305 data[10] = card->perf_stats.sg_skbs_rx;
4306 data[11] = card->perf_stats.sg_frags_rx;
4307 data[12] = card->perf_stats.sg_alloc_page_rx;
4308 data[13] = (card->perf_stats.large_send_bytes >> 10);
4309 data[14] = card->perf_stats.large_send_cnt;
4310 data[15] = card->perf_stats.sc_dp_p;
4311 data[16] = card->perf_stats.sc_p_dp;
4312 data[17] = QETH_LOW_WATERMARK_PACK;
4313 data[18] = QETH_HIGH_WATERMARK_PACK;
4314 data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
4315 data[20] = (card->qdio.no_out_queues > 1) ?
4316 atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
4317 data[21] = (card->qdio.no_out_queues > 2) ?
4318 atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
4319 data[22] = (card->qdio.no_out_queues > 3) ?
4320 atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
4321 data[23] = card->perf_stats.inbound_time;
4322 data[24] = card->perf_stats.inbound_cnt;
4323 data[25] = card->perf_stats.inbound_do_qdio_time;
4324 data[26] = card->perf_stats.inbound_do_qdio_cnt;
4325 data[27] = card->perf_stats.outbound_handler_time;
4326 data[28] = card->perf_stats.outbound_handler_cnt;
4327 data[29] = card->perf_stats.outbound_time;
4328 data[30] = card->perf_stats.outbound_cnt;
4329 data[31] = card->perf_stats.outbound_do_qdio_time;
4330 data[32] = card->perf_stats.outbound_do_qdio_cnt;
4331 }
4332 EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
4333
4334 void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4335 {
4336 switch (stringset) {
4337 case ETH_SS_STATS:
4338 memcpy(data, &qeth_ethtool_stats_keys,
4339 sizeof(qeth_ethtool_stats_keys));
4340 break;
4341 default:
4342 WARN_ON(1);
4343 break;
4344 }
4345 }
4346 EXPORT_SYMBOL_GPL(qeth_core_get_strings);
4347
4348 void qeth_core_get_drvinfo(struct net_device *dev,
4349 struct ethtool_drvinfo *info)
4350 {
4351 struct qeth_card *card = netdev_priv(dev);
4352 if (card->options.layer2)
4353 strcpy(info->driver, "qeth_l2");
4354 else
4355 strcpy(info->driver, "qeth_l3");
4356
4357 strcpy(info->version, "1.0");
4358 strcpy(info->fw_version, card->info.mcl_level);
4359 sprintf(info->bus_info, "%s/%s/%s",
4360 CARD_RDEV_ID(card),
4361 CARD_WDEV_ID(card),
4362 CARD_DDEV_ID(card));
4363 }
4364 EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
4365
4366 int qeth_core_ethtool_get_settings(struct net_device *netdev,
4367 struct ethtool_cmd *ecmd)
4368 {
4369 struct qeth_card *card = netdev_priv(netdev);
4370 enum qeth_link_types link_type;
4371
4372 if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
4373 link_type = QETH_LINK_TYPE_10GBIT_ETH;
4374 else
4375 link_type = card->info.link_type;
4376
4377 ecmd->transceiver = XCVR_INTERNAL;
4378 ecmd->supported = SUPPORTED_Autoneg;
4379 ecmd->advertising = ADVERTISED_Autoneg;
4380 ecmd->duplex = DUPLEX_FULL;
4381 ecmd->autoneg = AUTONEG_ENABLE;
4382
4383 switch (link_type) {
4384 case QETH_LINK_TYPE_FAST_ETH:
4385 case QETH_LINK_TYPE_LANE_ETH100:
4386 ecmd->supported |= SUPPORTED_10baseT_Half |
4387 SUPPORTED_10baseT_Full |
4388 SUPPORTED_100baseT_Half |
4389 SUPPORTED_100baseT_Full |
4390 SUPPORTED_TP;
4391 ecmd->advertising |= ADVERTISED_10baseT_Half |
4392 ADVERTISED_10baseT_Full |
4393 ADVERTISED_100baseT_Half |
4394 ADVERTISED_100baseT_Full |
4395 ADVERTISED_TP;
4396 ecmd->speed = SPEED_100;
4397 ecmd->port = PORT_TP;
4398 break;
4399
4400 case QETH_LINK_TYPE_GBIT_ETH:
4401 case QETH_LINK_TYPE_LANE_ETH1000:
4402 ecmd->supported |= SUPPORTED_10baseT_Half |
4403 SUPPORTED_10baseT_Full |
4404 SUPPORTED_100baseT_Half |
4405 SUPPORTED_100baseT_Full |
4406 SUPPORTED_1000baseT_Half |
4407 SUPPORTED_1000baseT_Full |
4408 SUPPORTED_FIBRE;
4409 ecmd->advertising |= ADVERTISED_10baseT_Half |
4410 ADVERTISED_10baseT_Full |
4411 ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full |
4413 ADVERTISED_1000baseT_Half |
4414 ADVERTISED_1000baseT_Full |
4415 ADVERTISED_FIBRE;
4416 ecmd->speed = SPEED_1000;
4417 ecmd->port = PORT_FIBRE;
4418 break;
4419
4420 case QETH_LINK_TYPE_10GBIT_ETH:
4421 ecmd->supported |= SUPPORTED_10baseT_Half |
4422 SUPPORTED_10baseT_Full |
4423 SUPPORTED_100baseT_Half |
4424 SUPPORTED_100baseT_Full |
4425 SUPPORTED_1000baseT_Half |
4426 SUPPORTED_1000baseT_Full |
4427 SUPPORTED_10000baseT_Full |
4428 SUPPORTED_FIBRE;
4429 ecmd->advertising |= ADVERTISED_10baseT_Half |
4430 ADVERTISED_10baseT_Full |
4431 ADVERTISED_100baseT_Half |
4432 ADVERTISED_100baseT_Full |
4433 ADVERTISED_1000baseT_Half |
4434 ADVERTISED_1000baseT_Full |
4435 ADVERTISED_10000baseT_Full |
4436 ADVERTISED_FIBRE;
4437 ecmd->speed = SPEED_10000;
4438 ecmd->port = PORT_FIBRE;
4439 break;
4440
4441 default:
4442 ecmd->supported |= SUPPORTED_10baseT_Half |
4443 SUPPORTED_10baseT_Full |
4444 SUPPORTED_TP;
4445 ecmd->advertising |= ADVERTISED_10baseT_Half |
4446 ADVERTISED_10baseT_Full |
4447 ADVERTISED_TP;
4448 ecmd->speed = SPEED_10;
4449 ecmd->port = PORT_TP;
4450 }
4451
4452 return 0;
4453 }
4454 EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
4455
4456 static int __init qeth_core_init(void)
4457 {
4458 int rc;
4459
4460 PRINT_INFO("loading core functions\n");
4461 INIT_LIST_HEAD(&qeth_core_card_list.list);
4462 rwlock_init(&qeth_core_card_list.rwlock);
4463
4464 rc = qeth_register_dbf_views();
4465 if (rc)
4466 goto out_err;
4467 rc = ccw_driver_register(&qeth_ccw_driver);
4468 if (rc)
4469 goto ccw_err;
4470 rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
4471 if (rc)
4472 goto ccwgroup_err;
4473 rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
4474 &driver_attr_group);
4475 if (rc)
4476 goto driver_err;
4477 qeth_core_root_dev = s390_root_dev_register("qeth");
4478 rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
4479 if (rc)
4480 goto register_err;
4481 return 0;
4482
4483 register_err:
4484 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4485 &driver_attr_group);
4486 driver_err:
4487 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4488 ccwgroup_err:
4489 ccw_driver_unregister(&qeth_ccw_driver);
4490 ccw_err:
4491 qeth_unregister_dbf_views();
4492 out_err:
4493 PRINT_ERR("Initialization failed with code %d\n", rc);
4494 return rc;
4495 }
4496
4497 static void __exit qeth_core_exit(void)
4498 {
4499 s390_root_dev_unregister(qeth_core_root_dev);
4500 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4501 &driver_attr_group);
4502 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4503 ccw_driver_unregister(&qeth_ccw_driver);
4504 qeth_unregister_dbf_views();
4505 PRINT_INFO("core functions removed\n");
4506 }
4507
4508 module_init(qeth_core_init);
4509 module_exit(qeth_core_exit);
4510 MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
4511 MODULE_DESCRIPTION("qeth core functions");
4512 MODULE_LICENSE("GPL");
Linux with added FPC-III support