drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #include <video/exynos5433_decon.h>
  21
  22 #include "exynos_drm_drv.h"
  23 #include "exynos_drm_crtc.h"
  24 #include "exynos_drm_fb.h"
  25 #include "exynos_drm_plane.h"
  26 #include "exynos_drm_iommu.h"
  27
  28 #define WINDOWS_NR      3
  29 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  30
  31 #define IFTYPE_I80      (1 << 0)
  32 #define I80_HW_TRG      (1 << 1)
  33 #define IFTYPE_HDMI     (1 << 2)
  34
  35 static const char * const decon_clks_name[] = {
  36         "pclk",
  37         "aclk_decon",
  38         "aclk_smmu_decon0x",
  39         "aclk_xiu_decon0x",
  40         "pclk_smmu_decon0x",
  41         "sclk_decon_vclk",
  42         "sclk_decon_eclk",
  43 };
  44
  45 enum decon_flag_bits {
  46         BIT_CLKS_ENABLED,
  47         BIT_IRQS_ENABLED,
  48         BIT_WIN_UPDATED,
  49         BIT_SUSPENDED,
  50         BIT_REQUEST_UPDATE
  51 };
  52
  53 struct decon_context {
  54         struct device                   *dev;
  55         struct drm_device               *drm_dev;
  56         struct exynos_drm_crtc          *crtc;
  57         struct exynos_drm_plane         planes[WINDOWS_NR];
  58         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  59         void __iomem                    *addr;
  60         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  61         int                             pipe;
  62         unsigned long                   flags;
  63         unsigned long                   out_type;
  64         int                             first_win;
  65 };
  66
  67 static const uint32_t decon_formats[] = {
  68         DRM_FORMAT_XRGB1555,
  69         DRM_FORMAT_RGB565,
  70         DRM_FORMAT_XRGB8888,
  71         DRM_FORMAT_ARGB8888,
  72 };
  73
  74 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  75         DRM_PLANE_TYPE_PRIMARY,
  76         DRM_PLANE_TYPE_OVERLAY,
  77         DRM_PLANE_TYPE_CURSOR,
  78 };
  79
  80 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  81                                   u32 val)
  82 {
  83         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  84         writel(val, ctx->addr + reg);
  85 }
  86
  87 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  88 {
  89         struct decon_context *ctx = crtc->ctx;
  90         u32 val;
  91
  92         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  93                 return -EPERM;
  94
  95         if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
  96                 val = VIDINTCON0_INTEN;
  97                 if (ctx->out_type & IFTYPE_I80)
  98                         val |= VIDINTCON0_FRAMEDONE;
  99                 else
 100                         val |= VIDINTCON0_INTFRMEN;
 101
 102                 writel(val, ctx->addr + DECON_VIDINTCON0);
 103         }
 104
 105         return 0;
 106 }
 107
 108 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 109 {
 110         struct decon_context *ctx = crtc->ctx;
 111
 112         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 113                 return;
 114
 115         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 116                 writel(0, ctx->addr + DECON_VIDINTCON0);
 117 }
 118
 119 static void decon_setup_trigger(struct decon_context *ctx)
 120 {
 121         u32 val = !(ctx->out_type & I80_HW_TRG)
 122                 ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 123                   TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
 124                 : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 125                   TRIGCON_HWTRIGMASK | TRIGCON_HWTRIGEN;
 126         writel(val, ctx->addr + DECON_TRIGCON);
 127 }
 128
 129 static void decon_commit(struct exynos_drm_crtc *crtc)
 130 {
 131         struct decon_context *ctx = crtc->ctx;
 132         struct drm_display_mode *m = &crtc->base.mode;
 133         u32 val;
 134
 135         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 136                 return;
 137
 138         if (ctx->out_type & IFTYPE_HDMI) {
 139                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 140                 m->crtc_hsync_end = m->crtc_htotal - 92;
 141                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 142                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 143         }
 144
 145         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
 146
 147         /* enable clock gate */
 148         val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
 149         writel(val, ctx->addr + DECON_CMU);
 150
 151         if (ctx->out_type & (IFTYPE_I80 | I80_HW_TRG))
 152                 decon_setup_trigger(ctx);
 153
 154         /* lcd on and use command if */
 155         val = VIDOUT_LCD_ON;
 156         if (ctx->out_type & IFTYPE_I80) {
 157                 val |= VIDOUT_COMMAND_IF;
 158         } else {
 159                 val |= VIDOUT_RGB_IF;
 160         }
 161
 162         writel(val, ctx->addr + DECON_VIDOUTCON0);
 163
 164         val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 165                 VIDTCON2_HOZVAL(m->hdisplay - 1);
 166         writel(val, ctx->addr + DECON_VIDTCON2);
 167
 168         if (!(ctx->out_type & IFTYPE_I80)) {
 169                 val = VIDTCON00_VBPD_F(
 170                                 m->crtc_vtotal - m->crtc_vsync_end - 1) |
 171                         VIDTCON00_VFPD_F(
 172                                 m->crtc_vsync_start - m->crtc_vdisplay - 1);
 173                 writel(val, ctx->addr + DECON_VIDTCON00);
 174
 175                 val = VIDTCON01_VSPW_F(
 176                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 177                 writel(val, ctx->addr + DECON_VIDTCON01);
 178
 179                 val = VIDTCON10_HBPD_F(
 180                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 181                         VIDTCON10_HFPD_F(
 182                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 183                 writel(val, ctx->addr + DECON_VIDTCON10);
 184
 185                 val = VIDTCON11_HSPW_F(
 186                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 187                 writel(val, ctx->addr + DECON_VIDTCON11);
 188         }
 189
 190         /* enable output and display signal */
 191         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 192
 193         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 194 }
 195
 196 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 197                                  struct drm_framebuffer *fb)
 198 {
 199         unsigned long val;
 200
 201         val = readl(ctx->addr + DECON_WINCONx(win));
 202         val &= WINCONx_ENWIN_F;
 203
 204         switch (fb->pixel_format) {
 205         case DRM_FORMAT_XRGB1555:
 206                 val |= WINCONx_BPPMODE_16BPP_I1555;
 207                 val |= WINCONx_HAWSWP_F;
 208                 val |= WINCONx_BURSTLEN_16WORD;
 209                 break;
 210         case DRM_FORMAT_RGB565:
 211                 val |= WINCONx_BPPMODE_16BPP_565;
 212                 val |= WINCONx_HAWSWP_F;
 213                 val |= WINCONx_BURSTLEN_16WORD;
 214                 break;
 215         case DRM_FORMAT_XRGB8888:
 216                 val |= WINCONx_BPPMODE_24BPP_888;
 217                 val |= WINCONx_WSWP_F;
 218                 val |= WINCONx_BURSTLEN_16WORD;
 219                 break;
 220         case DRM_FORMAT_ARGB8888:
 221                 val |= WINCONx_BPPMODE_32BPP_A8888;
 222                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 223                 val |= WINCONx_BURSTLEN_16WORD;
 224                 break;
 225         default:
 226                 DRM_ERROR("Proper pixel format is not set\n");
 227                 return;
 228         }
 229
 230         DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
 231
 232         /*
 233          * In case of exynos, setting dma-burst to 16Word causes permanent
 234          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 235          * switching which is based on plane size is not recommended as
 236          * plane size varies a lot towards the end of the screen and rapid
 237          * movement causes unstable DMA which results into iommu crash/tear.
 238          */
 239
 240         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 241                 val &= ~WINCONx_BURSTLEN_MASK;
 242                 val |= WINCONx_BURSTLEN_8WORD;
 243         }
 244
 245         writel(val, ctx->addr + DECON_WINCONx(win));
 246 }
 247
 248 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 249                                         bool protect)
 250 {
 251         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 252                        protect ? ~0 : 0);
 253 }
 254
 255 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 256 {
 257         struct decon_context *ctx = crtc->ctx;
 258         int i;
 259
 260         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 261                 return;
 262
 263         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 264                 decon_shadow_protect_win(ctx, i, true);
 265 }
 266
 267 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 268 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 269 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 270
 271 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 272                                struct exynos_drm_plane *plane)
 273 {
 274         struct exynos_drm_plane_state *state =
 275                                 to_exynos_plane_state(plane->base.state);
 276         struct decon_context *ctx = crtc->ctx;
 277         struct drm_framebuffer *fb = state->base.fb;
 278         unsigned int win = plane->index;
 279         unsigned int bpp = fb->bits_per_pixel >> 3;
 280         unsigned int pitch = fb->pitches[0];
 281         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 282         u32 val;
 283
 284         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 285                 return;
 286
 287         val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 288         writel(val, ctx->addr + DECON_VIDOSDxA(win));
 289
 290         val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 291                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 292         writel(val, ctx->addr + DECON_VIDOSDxB(win));
 293
 294         val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
 295                 VIDOSD_Wx_ALPHA_B_F(0xff);
 296         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 297
 298         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 299                 VIDOSD_Wx_ALPHA_B_F(0x0);
 300         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 301
 302         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 303
 304         val = dma_addr + pitch * state->src.h;
 305         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 306
 307         if (!(ctx->out_type & IFTYPE_HDMI))
 308                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 309                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 310         else
 311                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 312                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 313         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 314
 315         decon_win_set_pixfmt(ctx, win, fb);
 316
 317         /* window enable */
 318         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 319         set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
 320 }
 321
 322 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 323                                 struct exynos_drm_plane *plane)
 324 {
 325         struct decon_context *ctx = crtc->ctx;
 326         unsigned int win = plane->index;
 327
 328         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 329                 return;
 330
 331         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 332         set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
 333 }
 334
 335 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 336 {
 337         struct decon_context *ctx = crtc->ctx;
 338         int i;
 339
 340         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 341                 return;
 342
 343         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 344                 decon_shadow_protect_win(ctx, i, false);
 345
 346         if (test_and_clear_bit(BIT_REQUEST_UPDATE, &ctx->flags))
 347                 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 348
 349         if (ctx->out_type & IFTYPE_I80)
 350                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 351 }
 352
 353 static void decon_swreset(struct decon_context *ctx)
 354 {
 355         unsigned int tries;
 356
 357         writel(0, ctx->addr + DECON_VIDCON0);
 358         for (tries = 2000; tries; --tries) {
 359                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 360                         break;
 361                 udelay(10);
 362         }
 363
 364         WARN(tries == 0, "failed to disable DECON\n");
 365
 366         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 367         for (tries = 2000; tries; --tries) {
 368                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 369                         break;
 370                 udelay(10);
 371         }
 372
 373         WARN(tries == 0, "failed to software reset DECON\n");
 374
 375         if (!(ctx->out_type & IFTYPE_HDMI))
 376                 return;
 377
 378         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 379         decon_set_bits(ctx, DECON_CMU,
 380                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 381         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 382         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 383                ctx->addr + DECON_CRCCTRL);
 384 }
 385
 386 static void decon_enable(struct exynos_drm_crtc *crtc)
 387 {
 388         struct decon_context *ctx = crtc->ctx;
 389
 390         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 391                 return;
 392
 393         pm_runtime_get_sync(ctx->dev);
 394
 395         exynos_drm_pipe_clk_enable(crtc, true);
 396
 397         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 398
 399         decon_swreset(ctx);
 400
 401         /* if vblank was enabled status, enable it again. */
 402         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 403                 decon_enable_vblank(ctx->crtc);
 404
 405         decon_commit(ctx->crtc);
 406 }
 407
 408 static void decon_disable(struct exynos_drm_crtc *crtc)
 409 {
 410         struct decon_context *ctx = crtc->ctx;
 411         int i;
 412
 413         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 414                 return;
 415
 416         /*
 417          * We need to make sure that all windows are disabled before we
 418          * suspend that connector. Otherwise we might try to scan from
 419          * a destroyed buffer later.
 420          */
 421         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 422                 decon_disable_plane(crtc, &ctx->planes[i]);
 423
 424         decon_swreset(ctx);
 425
 426         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 427
 428         exynos_drm_pipe_clk_enable(crtc, false);
 429
 430         pm_runtime_put_sync(ctx->dev);
 431
 432         set_bit(BIT_SUSPENDED, &ctx->flags);
 433 }
 434
 435 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 436 {
 437         struct decon_context *ctx = crtc->ctx;
 438
 439         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 440             (ctx->out_type & I80_HW_TRG))
 441                 return;
 442
 443         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 444                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 445 }
 446
 447 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 448 {
 449         struct decon_context *ctx = crtc->ctx;
 450         int win, i, ret;
 451
 452         DRM_DEBUG_KMS("%s\n", __FILE__);
 453
 454         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 455                 ret = clk_prepare_enable(ctx->clks[i]);
 456                 if (ret < 0)
 457                         goto err;
 458         }
 459
 460         for (win = 0; win < WINDOWS_NR; win++) {
 461                 decon_shadow_protect_win(ctx, win, true);
 462                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 463                 decon_shadow_protect_win(ctx, win, false);
 464         }
 465
 466         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 467
 468         /* TODO: wait for possible vsync */
 469         msleep(50);
 470
 471 err:
 472         while (--i >= 0)
 473                 clk_disable_unprepare(ctx->clks[i]);
 474 }
 475
 476 static struct exynos_drm_crtc_ops decon_crtc_ops = {
 477         .enable                 = decon_enable,
 478         .disable                = decon_disable,
 479         .enable_vblank          = decon_enable_vblank,
 480         .disable_vblank         = decon_disable_vblank,
 481         .atomic_begin           = decon_atomic_begin,
 482         .update_plane           = decon_update_plane,
 483         .disable_plane          = decon_disable_plane,
 484         .atomic_flush           = decon_atomic_flush,
 485         .te_handler             = decon_te_irq_handler,
 486 };
 487
 488 static int decon_bind(struct device *dev, struct device *master, void *data)
 489 {
 490         struct decon_context *ctx = dev_get_drvdata(dev);
 491         struct drm_device *drm_dev = data;
 492         struct exynos_drm_private *priv = drm_dev->dev_private;
 493         struct exynos_drm_plane *exynos_plane;
 494         enum exynos_drm_output_type out_type;
 495         unsigned int win;
 496         int ret;
 497
 498         ctx->drm_dev = drm_dev;
 499         ctx->pipe = priv->pipe++;
 500
 501         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 502                 int tmp = (win == ctx->first_win) ? 0 : win;
 503
 504                 ctx->configs[win].pixel_formats = decon_formats;
 505                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 506                 ctx->configs[win].zpos = win;
 507                 ctx->configs[win].type = decon_win_types[tmp];
 508
 509                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 510                                         1 << ctx->pipe, &ctx->configs[win]);
 511                 if (ret)
 512                         return ret;
 513         }
 514
 515         exynos_plane = &ctx->planes[ctx->first_win];
 516         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 517                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 518         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 519                                         ctx->pipe, out_type,
 520                                         &decon_crtc_ops, ctx);
 521         if (IS_ERR(ctx->crtc)) {
 522                 ret = PTR_ERR(ctx->crtc);
 523                 goto err;
 524         }
 525
 526         decon_clear_channels(ctx->crtc);
 527
 528         ret = drm_iommu_attach_device(drm_dev, dev);
 529         if (ret)
 530                 goto err;
 531
 532         return ret;
 533 err:
 534         priv->pipe--;
 535         return ret;
 536 }
 537
 538 static void decon_unbind(struct device *dev, struct device *master, void *data)
 539 {
 540         struct decon_context *ctx = dev_get_drvdata(dev);
 541
 542         decon_disable(ctx->crtc);
 543
 544         /* detach this sub driver from iommu mapping if supported. */
 545         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 546 }
 547
 548 static const struct component_ops decon_component_ops = {
 549         .bind   = decon_bind,
 550         .unbind = decon_unbind,
 551 };
 552
 553 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 554 {
 555         struct decon_context *ctx = dev_id;
 556         u32 val;
 557
 558         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 559                 goto out;
 560
 561         val = readl(ctx->addr + DECON_VIDINTCON1);
 562         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 563
 564         if (val) {
 565                 writel(val, ctx->addr + DECON_VIDINTCON1);
 566                 drm_crtc_handle_vblank(&ctx->crtc->base);
 567         }
 568
 569 out:
 570         return IRQ_HANDLED;
 571 }
 572
 573 #ifdef CONFIG_PM
 574 static int exynos5433_decon_suspend(struct device *dev)
 575 {
 576         struct decon_context *ctx = dev_get_drvdata(dev);
 577         int i = ARRAY_SIZE(decon_clks_name);
 578
 579         while (--i >= 0)
 580                 clk_disable_unprepare(ctx->clks[i]);
 581
 582         return 0;
 583 }
 584
 585 static int exynos5433_decon_resume(struct device *dev)
 586 {
 587         struct decon_context *ctx = dev_get_drvdata(dev);
 588         int i, ret;
 589
 590         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 591                 ret = clk_prepare_enable(ctx->clks[i]);
 592                 if (ret < 0)
 593                         goto err;
 594         }
 595
 596         return 0;
 597
 598 err:
 599         while (--i >= 0)
 600                 clk_disable_unprepare(ctx->clks[i]);
 601
 602         return ret;
 603 }
 604 #endif
 605
 606 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 607         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 608                            NULL)
 609 };
 610
 611 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 612         {
 613                 .compatible = "samsung,exynos5433-decon",
 614                 .data = (void *)I80_HW_TRG
 615         },
 616         {
 617                 .compatible = "samsung,exynos5433-decon-tv",
 618                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 619         },
 620         {},
 621 };
 622 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 623
 624 static int exynos5433_decon_probe(struct platform_device *pdev)
 625 {
 626         struct device *dev = &pdev->dev;
 627         struct decon_context *ctx;
 628         struct resource *res;
 629         int ret;
 630         int i;
 631
 632         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 633         if (!ctx)
 634                 return -ENOMEM;
 635
 636         __set_bit(BIT_SUSPENDED, &ctx->flags);
 637         ctx->dev = dev;
 638         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 639
 640         if (ctx->out_type & IFTYPE_HDMI) {
 641                 ctx->first_win = 1;
 642         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 643                 ctx->out_type |= IFTYPE_I80;
 644         }
 645
 646         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 647                 struct clk *clk;
 648
 649                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 650                 if (IS_ERR(clk))
 651                         return PTR_ERR(clk);
 652
 653                 ctx->clks[i] = clk;
 654         }
 655
 656         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 657         if (!res) {
 658                 dev_err(dev, "cannot find IO resource\n");
 659                 return -ENXIO;
 660         }
 661
 662         ctx->addr = devm_ioremap_resource(dev, res);
 663         if (IS_ERR(ctx->addr)) {
 664                 dev_err(dev, "ioremap failed\n");
 665                 return PTR_ERR(ctx->addr);
 666         }
 667
 668         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 669                         (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
 670         if (!res) {
 671                 dev_err(dev, "cannot find IRQ resource\n");
 672                 return -ENXIO;
 673         }
 674
 675         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 676                                "drm_decon", ctx);
 677         if (ret < 0) {
 678                 dev_err(dev, "lcd_sys irq request failed\n");
 679                 return ret;
 680         }
 681
 682         platform_set_drvdata(pdev, ctx);
 683
 684         pm_runtime_enable(dev);
 685
 686         ret = component_add(dev, &decon_component_ops);
 687         if (ret)
 688                 goto err_disable_pm_runtime;
 689
 690         return 0;
 691
 692 err_disable_pm_runtime:
 693         pm_runtime_disable(dev);
 694
 695         return ret;
 696 }
 697
 698 static int exynos5433_decon_remove(struct platform_device *pdev)
 699 {
 700         pm_runtime_disable(&pdev->dev);
 701
 702         component_del(&pdev->dev, &decon_component_ops);
 703
 704         return 0;
 705 }
 706
 707 struct platform_driver exynos5433_decon_driver = {
 708         .probe          = exynos5433_decon_probe,
 709         .remove         = exynos5433_decon_remove,
 710         .driver         = {
 711                 .name   = "exynos5433-decon",
 712                 .pm     = &exynos5433_decon_pm_ops,
 713                 .of_match_table = exynos5433_decon_driver_dt_match,
 714         },
 715 };