arch/arm/plat-mxc/include/mach/board-mx31ads.h

   1 /*
   2  * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
  12 #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
  13
  14 #include <mach/hardware.h>
  15
  16 /* Base address of PBC controller */
  17 #define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
  18 /* Offsets for the PBC Controller register */
  19
  20 /* PBC Board status register offset */
  21 #define PBC_BSTAT               0x000002
  22
  23 /* PBC Board control register 1 set address */
  24 #define PBC_BCTRL1_SET          0x000004
  25
  26 /* PBC Board control register 1 clear address */
  27 #define PBC_BCTRL1_CLEAR        0x000006
  28
  29 /* PBC Board control register 2 set address */
  30 #define PBC_BCTRL2_SET          0x000008
  31
  32 /* PBC Board control register 2 clear address */
  33 #define PBC_BCTRL2_CLEAR        0x00000A
  34
  35 /* PBC Board control register 3 set address */
  36 #define PBC_BCTRL3_SET          0x00000C
  37
  38 /* PBC Board control register 3 clear address */
  39 #define PBC_BCTRL3_CLEAR        0x00000E
  40
  41 /* PBC Board control register 4 set address */
  42 #define PBC_BCTRL4_SET          0x000010
  43
  44 /* PBC Board control register 4 clear address */
  45 #define PBC_BCTRL4_CLEAR        0x000012
  46
  47 /* PBC Board status register 1 */
  48 #define PBC_BSTAT1              0x000014
  49
  50 /* PBC Board interrupt status register */
  51 #define PBC_INTSTATUS           0x000016
  52
  53 /* PBC Board interrupt current status register */
  54 #define PBC_INTCURR_STATUS      0x000018
  55
  56 /* PBC Interrupt mask register set address */
  57 #define PBC_INTMASK_SET         0x00001A
  58
  59 /* PBC Interrupt mask register clear address */
  60 #define PBC_INTMASK_CLEAR       0x00001C
  61
  62 /* External UART A */
  63 #define PBC_SC16C652_UARTA      0x010000
  64
  65 /* External UART B */
  66 #define PBC_SC16C652_UARTB      0x010010
  67
  68 /* Ethernet Controller IO base address */
  69 #define PBC_CS8900A_IOBASE      0x020000
  70
  71 /* Ethernet Controller Memory base address */
  72 #define PBC_CS8900A_MEMBASE     0x021000
  73
  74 /* Ethernet Controller DMA base address */
  75 #define PBC_CS8900A_DMABASE     0x022000
  76
  77 /* External chip select 0 */
  78 #define PBC_XCS0                0x040000
  79
  80 /* LCD Display enable */
  81 #define PBC_LCD_EN_B            0x060000
  82
  83 /* Code test debug enable */
  84 #define PBC_CODE_B              0x070000
  85
  86 /* PSRAM memory select */
  87 #define PBC_PSRAM_B             0x5000000
  88
  89 #define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
  90 #define PBC_INTCURR_STATUS_REG  (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
  91 #define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
  92 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
  93 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
  94
  95 #define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
  96 #define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
  97
  98 #define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 0)
  99 #define EXPIO_INT_PB_IRQ        (MXC_EXP_IO_BASE + 1)
 100 #define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
 101 #define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
 102 #define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
 103 #define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
 104 #define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
 105 #define EXPIO_INT_RES7          (MXC_EXP_IO_BASE + 7)
 106 #define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
 107 #define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
 108 #define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
 109 #define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
 110 #define EXPIO_INT_SYNTH_IRQ     (MXC_EXP_IO_BASE + 12)
 111 #define EXPIO_INT_CE_INT1       (MXC_EXP_IO_BASE + 13)
 112 #define EXPIO_INT_CE_INT2       (MXC_EXP_IO_BASE + 14)
 113 #define EXPIO_INT_RES15         (MXC_EXP_IO_BASE + 15)
 114
 115 #define MXC_MAX_EXP_IO_LINES    16
 116
 117 /* mandatory for CONFIG_DEBUG_LL */
 118
 119 #define MXC_LL_UART_PADDR       UART1_BASE_ADDR
 120 #define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 121
 122 #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */