arch/arm/plat-mxc/include/mach/mx27.h

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This contains i.MX27-specific hardware definitions. For those
   6  * hardware pieces that are common between i.MX21 and i.MX27, have a
   7  * look at mx2x.h.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version 2
  12  * of the License, or (at your option) any later version.
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  21  * MA  02110-1301, USA.
  22  */
  23
  24 #ifndef __ASM_ARCH_MXC_MX27_H__
  25 #define __ASM_ARCH_MXC_MX27_H__
  26
  27 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
  28 #error "Do not include directly."
  29 #endif
  30
  31 /* IRAM */
  32 #define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
  33
  34 #define MSHC_BASE_ADDR          (AIPI_BASE_ADDR + 0x18000)
  35 #define GPT5_BASE_ADDR          (AIPI_BASE_ADDR + 0x19000)
  36 #define GPT4_BASE_ADDR          (AIPI_BASE_ADDR + 0x1A000)
  37 #define UART5_BASE_ADDR         (AIPI_BASE_ADDR + 0x1B000)
  38 #define UART6_BASE_ADDR         (AIPI_BASE_ADDR + 0x1C000)
  39 #define I2C2_BASE_ADDR          (AIPI_BASE_ADDR + 0x1D000)
  40 #define SDHC3_BASE_ADDR         (AIPI_BASE_ADDR + 0x1E000)
  41 #define GPT6_BASE_ADDR          (AIPI_BASE_ADDR + 0x1F000)
  42 #define VPU_BASE_ADDR           (AIPI_BASE_ADDR + 0x23000)
  43 #define OTG_BASE_ADDR           USBOTG_BASE_ADDR
  44 #define SAHARA_BASE_ADDR        (AIPI_BASE_ADDR + 0x25000)
  45 #define IIM_BASE_ADDR           (AIPI_BASE_ADDR + 0x28000)
  46 #define RTIC_BASE_ADDR          (AIPI_BASE_ADDR + 0x2A000)
  47 #define FEC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2B000)
  48 #define SCC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2C000)
  49 #define ETB_BASE_ADDR           (AIPI_BASE_ADDR + 0x3B000)
  50 #define ETB_RAM_BASE_ADDR       (AIPI_BASE_ADDR + 0x3C000)
  51
  52 /* ROM patch */
  53 #define ROMP_BASE_ADDR          0x10041000
  54
  55 #define ATA_BASE_ADDR           (SAHB1_BASE_ADDR + 0x1000)
  56
  57 /* Memory regions and CS */
  58 #define SDRAM_BASE_ADDR         0xA0000000
  59 #define CSD1_BASE_ADDR          0xB0000000
  60
  61 #define CS0_BASE_ADDR           0xC0000000
  62 #define CS1_BASE_ADDR           0xC8000000
  63 #define CS2_BASE_ADDR           0xD0000000
  64 #define CS3_BASE_ADDR           0xD2000000
  65 #define CS4_BASE_ADDR           0xD4000000
  66 #define CS5_BASE_ADDR           0xD6000000
  67 #define PCMCIA_MEM_BASE_ADDR    0xDC000000
  68
  69 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */
  70 #define X_MEMC_BASE_ADDR        0xD8000000
  71 #define X_MEMC_BASE_ADDR_VIRT   0xF4200000
  72 #define X_MEMC_SIZE             SZ_1M
  73
  74 #define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
  75 #define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
  76 #define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
  77 #define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
  78 #define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x4000)
  79
  80 /* fixed interrupt numbers */
  81 #define MXC_INT_CCM             63
  82 #define MXC_INT_IIM             62
  83 #define MXC_INT_SAHARA          59
  84 #define MXC_INT_SCC_SCM         58
  85 #define MXC_INT_SCC_SMN         57
  86 #define MXC_INT_USB3            56
  87 #define MXC_INT_USB2            55
  88 #define MXC_INT_USB1            54
  89 #define MXC_INT_VPU             53
  90 #define MXC_INT_FEC             50
  91 #define MXC_INT_UART5           49
  92 #define MXC_INT_UART6           48
  93 #define MXC_INT_ATA             30
  94 #define MXC_INT_SDHC3           9
  95 #define MXC_INT_SDHC            7
  96 #define MXC_INT_RTIC            5
  97 #define MXC_INT_GPT4            4
  98 #define MXC_INT_GPT5            3
  99 #define MXC_INT_GPT6            2
 100 #define MXC_INT_I2C2            1
 101
 102 /* fixed DMA request numbers */
 103 #define DMA_REQ_NFC             37
 104 #define DMA_REQ_SDHC3           36
 105 #define DMA_REQ_UART6_RX        35
 106 #define DMA_REQ_UART6_TX        34
 107 #define DMA_REQ_UART5_RX        33
 108 #define DMA_REQ_UART5_TX        32
 109 #define DMA_REQ_ATA_RCV         29
 110 #define DMA_REQ_ATA_TX          28
 111 #define DMA_REQ_MSHC            4
 112
 113 /* silicon revisions specific to i.MX27 */
 114 #define CHIP_REV_1_0            0x00
 115 #define CHIP_REV_2_0            0x01
 116
 117 #ifndef __ASSEMBLY__
 118 extern int mx27_revision(void);
 119 #endif
 120
 121 /* Mandatory defines used globally */
 122
 123 /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
 124 #define ARCH_NR_GPIOS           (192 + 16)
 125
 126 #endif /* __ASM_ARCH_MXC_MX27_H__ */