arch/arm/plat-mxc/include/mach/mx31.h

   1 /*
   2  * IRAM
   3  */
   4 #define MX31_IRAM_BASE_ADDR             0x1FFC0000      /* internal ram */
   5 #define MX31_IRAM_SIZE                  SZ_16K
   6
   7 #define OTG_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00088000)
   8 #define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
   9 #define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
  10 #define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
  11
  12 #define MMC_SDHC1_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00004000)
  13 #define MMC_SDHC2_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00008000)
  14 #define SIM1_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00018000)
  15 #define IIM_BASE_ADDR           (SPBA0_BASE_ADDR + 0x0001C000)
  16
  17 #define CSPI3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
  18 #define FIRI_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0008C000)
  19 #define SCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AE000)
  20 #define SMN_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AF000)
  21 #define MPEG4_ENC_BASE_ADDR     (AIPS2_BASE_ADDR + 0x000C8000)
  22
  23 #define MX31_NFC_BASE_ADDR      (X_MEMC_BASE_ADDR + 0x0000)
  24
  25 #define MXC_INT_MPEG4_ENCODER   5
  26 #define MXC_INT_FIRI            7
  27 #define MX31_INT_MMC_SDHC2      8
  28 #define MXC_INT_MMC_SDHC1       9
  29 #define MX31_INT_SSI2           11
  30 #define MX31_INT_SSI1           12
  31 #define MXC_INT_MBX             16
  32 #define MXC_INT_CSPI3           17
  33 #define MXC_INT_SIM2            20
  34 #define MXC_INT_SIM1            21
  35 #define MXC_INT_CCM_DVFS        31
  36 #define MXC_INT_USB1            35
  37 #define MXC_INT_USB2            36
  38 #define MXC_INT_USB3            37
  39 #define MXC_INT_USB4            38
  40 #define MXC_INT_MSHC2           40
  41 #define MXC_INT_UART4           46
  42 #define MXC_INT_UART5           47
  43 #define MXC_INT_CCM             53
  44 #define MXC_INT_PCMCIA          54
  45