arch/arm/plat-mxc/include/mach/mx3x.h

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef __ASM_ARCH_MXC_MX31_H__
  12 #define __ASM_ARCH_MXC_MX31_H__
  13
  14 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
  15 #error "Do not include directly."
  16 #endif
  17
  18 /*
  19  * MX31 memory map:
  20  *
  21  * Virt         Phys            Size    What
  22  * ---------------------------------------------------------------------------
  23  * FC000000     43F00000        1M      AIPS 1
  24  * FC100000     50000000        1M      SPBA
  25  * FC200000     53F00000        1M      AIPS 2
  26  * FC500000     60000000        128M    ROMPATCH
  27  * FC400000     68000000        128M    AVIC
  28  *              70000000        256M    IPU (MAX M2)
  29  *              80000000        256M    CSD0 SDRAM/DDR
  30  *              90000000        256M    CSD1 SDRAM/DDR
  31  *              A0000000        128M    CS0 Flash
  32  *              A8000000        128M    CS1 Flash
  33  *              B0000000        32M     CS2
  34  *              B2000000        32M     CS3
  35  * F4000000     B4000000        32M     CS4
  36  *              B6000000        32M     CS5
  37  * FC320000     B8000000        64K     NAND, SDRAM, WEIM, M3IF, EMI controllers
  38  *              C0000000        64M     PCMCIA/CF
  39  */
  40
  41 #define CS0_BASE_ADDR           0xA0000000
  42 #define CS1_BASE_ADDR           0xA8000000
  43 #define CS2_BASE_ADDR           0xB0000000
  44 #define CS3_BASE_ADDR           0xB2000000
  45
  46 #define CS4_BASE_ADDR           0xB4000000
  47 #define CS4_BASE_ADDR_VIRT      0xF4000000
  48 #define CS4_SIZE                SZ_32M
  49
  50 #define CS5_BASE_ADDR           0xB6000000
  51 #define CS5_BASE_ADDR_VIRT      0xF6000000
  52 #define CS5_SIZE                SZ_32M
  53
  54 #define PCMCIA_MEM_BASE_ADDR    0xBC000000
  55
  56 /*
  57  * L2CC
  58  */
  59 #define L2CC_BASE_ADDR          0x30000000
  60 #define L2CC_SIZE               SZ_1M
  61
  62 /*
  63  * AIPS 1
  64  */
  65 #define AIPS1_BASE_ADDR         0x43F00000
  66 #define AIPS1_BASE_ADDR_VIRT    0xFC000000
  67 #define AIPS1_SIZE              SZ_1M
  68
  69 #define MAX_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00004000)
  70 #define EVTMON_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00008000)
  71 #define CLKCTL_BASE_ADDR        (AIPS1_BASE_ADDR + 0x0000C000)
  72 #define ETB_SLOT4_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00010000)
  73 #define ETB_SLOT5_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00014000)
  74 #define ECT_CTIO_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00018000)
  75 #define I2C_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00080000)
  76 #define I2C3_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00084000)
  77 #define UART1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00090000)
  78 #define UART2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00094000)
  79 #define I2C2_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00098000)
  80 #define OWIRE_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0009C000)
  81 #define SSI1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A0000)
  82 #define CSPI1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A4000)
  83 #define KPP_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000A8000)
  84 #define IOMUXC_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000AC000)
  85 #define ECT_IP1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000B8000)
  86 #define ECT_IP2_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000BC000)
  87
  88 /*
  89  * SPBA global module enabled #0
  90  */
  91 #define SPBA0_BASE_ADDR         0x50000000
  92 #define SPBA0_BASE_ADDR_VIRT    0xFC100000
  93 #define SPBA0_SIZE              SZ_1M
  94
  95 #define UART3_BASE_ADDR         (SPBA0_BASE_ADDR + 0x0000C000)
  96 #define CSPI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00010000)
  97 #define SSI2_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00014000)
  98 #define ATA_DMA_BASE_ADDR       (SPBA0_BASE_ADDR + 0x00020000)
  99 #define MSHC1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
 100 #define SPBA_CTRL_BASE_ADDR     (SPBA0_BASE_ADDR + 0x0003C000)
 101
 102 /*
 103  * AIPS 2
 104  */
 105 #define AIPS2_BASE_ADDR         0x53F00000
 106 #define AIPS2_BASE_ADDR_VIRT    0xFC200000
 107 #define AIPS2_SIZE              SZ_1M
 108 #define CCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x00080000)
 109 #define GPT1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00090000)
 110 #define EPIT1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00094000)
 111 #define EPIT2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00098000)
 112 #define GPIO3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A4000)
 113 #define SCC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AC000)
 114 #define RNGA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B0000)
 115 #define IPU_CTRL_BASE_ADDR      (AIPS2_BASE_ADDR + 0x000C0000)
 116 #define AUDMUX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000C4000)
 117 #define GPIO1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000CC000)
 118 #define GPIO2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D0000)
 119 #define SDMA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D4000)
 120 #define RTC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000D8000)
 121 #define WDOG_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DC000)
 122 #define PWM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E0000)
 123 #define RTIC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000EC000)
 124
 125 /*
 126  * ROMP and AVIC
 127  */
 128 #define ROMP_BASE_ADDR          0x60000000
 129 #define ROMP_BASE_ADDR_VIRT     0xFC500000
 130 #define ROMP_SIZE               SZ_1M
 131
 132 #define AVIC_BASE_ADDR          0x68000000
 133 #define AVIC_BASE_ADDR_VIRT     0xFC400000
 134 #define AVIC_SIZE               SZ_1M
 135
 136 /*
 137  * NAND, SDRAM, WEIM, M3IF, EMI controllers
 138  */
 139 #define X_MEMC_BASE_ADDR        0xB8000000
 140 #define X_MEMC_BASE_ADDR_VIRT   0xFC320000
 141 #define X_MEMC_SIZE             SZ_64K
 142
 143 #define ESDCTL_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
 144 #define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
 145 #define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
 146 #define EMI_CTL_BASE_ADDR       (X_MEMC_BASE_ADDR + 0x4000)
 147 #define PCMCIA_CTL_BASE_ADDR    EMI_CTL_BASE_ADDR
 148
 149 /*
 150  * Memory regions and CS
 151  */
 152 #define IPU_MEM_BASE_ADDR       0x70000000
 153 #define CSD0_BASE_ADDR          0x80000000
 154 #define CSD1_BASE_ADDR          0x90000000
 155
 156 /*!
 157  * This macro defines the physical to virtual address mapping for all the
 158  * peripheral modules. It is used by passing in the physical address as x
 159  * and returning the virtual address. If the physical address is not mapped,
 160  * it returns 0xDEADBEEF
 161  */
 162 #define IO_ADDRESS(x)   \
 163         (void __force __iomem *) \
 164         (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
 165         ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
 166         ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
 167         ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
 168         ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
 169         ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
 170         ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
 171         0xDEADBEEF)
 172
 173 /*
 174  * define the address mapping macros: in physical address order
 175  */
 176 #define L2CC_IO_ADDRESS(x)  \
 177         (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
 178
 179 #define AIPS1_IO_ADDRESS(x)  \
 180         (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
 181
 182 #define SPBA0_IO_ADDRESS(x)  \
 183         (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
 184
 185 #define AIPS2_IO_ADDRESS(x)  \
 186         (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
 187
 188 #define ROMP_IO_ADDRESS(x)  \
 189         (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
 190
 191 #define AVIC_IO_ADDRESS(x)  \
 192         (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
 193
 194 #define CS4_IO_ADDRESS(x)  \
 195         (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
 196
 197 #define CS5_IO_ADDRESS(x)  \
 198         (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
 199
 200 #define X_MEMC_IO_ADDRESS(x)  \
 201         (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
 202
 203 #define PCMCIA_IO_ADDRESS(x) \
 204         (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
 205
 206 /*
 207  * Interrupt numbers
 208  */
 209 #define MXC_INT_I2C3            3
 210 #define MXC_INT_I2C2            4
 211 #define MXC_INT_RTIC            6
 212 #define MXC_INT_I2C             10
 213 #define MXC_INT_CSPI2           13
 214 #define MXC_INT_CSPI1           14
 215 #define MXC_INT_ATA             15
 216 #define MXC_INT_UART3           18
 217 #define MXC_INT_IIM             19
 218 #define MXC_INT_RNGA            22
 219 #define MXC_INT_EVTMON          23
 220 #define MXC_INT_KPP             24
 221 #define MXC_INT_RTC             25
 222 #define MXC_INT_PWM             26
 223 #define MXC_INT_EPIT2           27
 224 #define MXC_INT_EPIT1           28
 225 #define MXC_INT_GPT             29
 226 #define MXC_INT_POWER_FAIL      30
 227 #define MXC_INT_UART2           32
 228 #define MXC_INT_NANDFC          33
 229 #define MXC_INT_SDMA            34
 230 #define MXC_INT_MSHC1           39
 231 #define MXC_INT_IPU_ERR         41
 232 #define MXC_INT_IPU_SYN         42
 233 #define MXC_INT_UART1           45
 234 #define MXC_INT_ECT             48
 235 #define MXC_INT_SCC_SCM         49
 236 #define MXC_INT_SCC_SMN         50
 237 #define MXC_INT_GPIO2           51
 238 #define MXC_INT_GPIO1           52
 239 #define MXC_INT_WDOG            55
 240 #define MXC_INT_GPIO3           56
 241 #define MXC_INT_EXT_POWER       58
 242 #define MXC_INT_EXT_TEMPER      59
 243 #define MXC_INT_EXT_SENSOR60    60
 244 #define MXC_INT_EXT_SENSOR61    61
 245 #define MXC_INT_EXT_WDOG        62
 246 #define MXC_INT_EXT_TV          63
 247
 248 #define PROD_SIGNATURE          0x1     /* For MX31 */
 249
 250 /* silicon revisions specific to i.MX31 */
 251 #define CHIP_REV_1_0            0x10
 252 #define CHIP_REV_1_1            0x11
 253 #define CHIP_REV_1_2            0x12
 254 #define CHIP_REV_1_3            0x13
 255 #define CHIP_REV_2_0            0x20
 256 #define CHIP_REV_2_1            0x21
 257 #define CHIP_REV_2_2            0x22
 258 #define CHIP_REV_2_3            0x23
 259 #define CHIP_REV_3_0            0x30
 260 #define CHIP_REV_3_1            0x31
 261 #define CHIP_REV_3_2            0x32
 262
 263 #define SYSTEM_REV_MIN          CHIP_REV_1_0
 264 #define SYSTEM_REV_NUM          3
 265
 266 /* gpio and gpio based interrupt handling */
 267 #define GPIO_DR                 0x00
 268 #define GPIO_GDIR               0x04
 269 #define GPIO_PSR                0x08
 270 #define GPIO_ICR1               0x0C
 271 #define GPIO_ICR2               0x10
 272 #define GPIO_IMR                0x14
 273 #define GPIO_ISR                0x18
 274 #define GPIO_INT_LOW_LEV        0x0
 275 #define GPIO_INT_HIGH_LEV       0x1
 276 #define GPIO_INT_RISE_EDGE      0x2
 277 #define GPIO_INT_FALL_EDGE      0x3
 278 #define GPIO_INT_NONE           0x4
 279
 280 /* Mandatory defines used globally */
 281
 282 /* this CPU supports up to 96 GPIOs */
 283 #define ARCH_NR_GPIOS           96
 284
 285 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 286
 287 extern unsigned int system_rev;
 288
 289 static inline int mx31_revision(void)
 290 {
 291         return system_rev;
 292 }
 293 #endif
 294
 295 #endif /*  __ASM_ARCH_MXC_MX31_H__ */
 296