arch/arm/mach-lh7a40x/lcd-panel.h

   1 /* lcd-panel.h
   2      $Id$
   3
   4    written by Marc Singer
   5    18 Jul 2005
   6
   7    Copyright (C) 2005 Marc Singer
   8
   9    -----------
  10    DESCRIPTION
  11    -----------
  12
  13    Only one panel may be defined at a time.
  14
  15    The pixel clock is calculated to be no greater than the target.
  16
  17    Each timing value is accompanied by a specification comment.
  18
  19      UNITS/MIN/TYP/MAX
  20
  21    Most of the units will be in clocks.
  22
  23    USE_RGB555
  24
  25      Define this macro to configure the AMBA LCD controller to use an
  26      RGB555 encoding for the pels instead of the normal RGB565.
  27
  28    LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11
  29
  30      These boards are best approximated by 555 for all panels.  Some
  31      can use an extra low-order bit of blue in bit 16 of the color
  32      value, but we don't have a way to communicate this non-linear
  33      mapping to the kernel.
  34
  35 */
  36
  37 #if !defined (__LCD_PANEL_H__)
  38 #    define   __LCD_PANEL_H__
  39
  40 #if defined (MACH_LPD79520)\
  41  || defined (MACH_LPD79524)\
  42  || defined (MACH_LPD7A400)\
  43  || defined (MACH_LPD7A404)
  44 # define USE_RGB555
  45 #endif
  46
  47 struct clcd_panel_extra {
  48         unsigned int hrmode;
  49         unsigned int clsen;
  50         unsigned int spsen;
  51         unsigned int pcdel;
  52         unsigned int revdel;
  53         unsigned int lpdel;
  54         unsigned int spldel;
  55         unsigned int pc2del;
  56 };
  57
  58 #define NS_TO_CLOCK(ns,c)       ((((ns)*((c)/1000) + (1000000 - 1))/1000000))
  59 #define CLOCK_TO_DIV(e,c)       (((c) + (e) - 1)/(e))
  60
  61 #if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
  62
  63         /* Logic Product Development LCD 3.5" QVGA HRTFT -10 */
  64         /* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */
  65
  66 #define PIX_CLOCK_TARGET        (6800000)
  67 #define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
  68 #define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
  69
  70 static struct clcd_panel lcd_panel = {
  71         .mode   = {
  72                 .name           = "3.5in QVGA (LQ035Q7DB02)",
  73                 .xres           = 240,
  74                 .yres           = 320,
  75                 .pixclock       = PIX_CLOCK,
  76                 .left_margin    = 16,
  77                 .right_margin   = 21,
  78                 .upper_margin   = 8,                    // line/8/8/8
  79                 .lower_margin   = 5,
  80                 .hsync_len      = 61,
  81                 .vsync_len      = NS_TO_CLOCK (60, PIX_CLOCK),
  82                 .vmode          = FB_VMODE_NONINTERLACED,
  83         },
  84         .width          = -1,
  85         .height         = -1,
  86         .tim2           = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2),
  87         .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
  88         .bpp            = 16,
  89 };
  90
  91 #define HAS_LCD_PANEL_EXTRA
  92
  93 static struct clcd_panel_extra lcd_panel_extra = {
  94         .hrmode = 1,
  95         .clsen = 1,
  96         .spsen = 1,
  97         .pcdel = 8,
  98         .revdel = 7,
  99         .lpdel = 13,
 100         .spldel = 77,
 101         .pc2del = 208,
 102 };
 103
 104 #endif
 105
 106 #if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02
 107
 108         /* Logic Product Development LCD 5.7" QVGA -10 */
 109         /* Sharp PN LQ057Q3DC02 */
 110         /* QVGA mode, V/Q=LOW */
 111
 112 /* From Sharp on 2006.1.3.  I believe some of the values are incorrect
 113  * based on the datasheet.
 114
 115     Timing0     TIMING1         TIMING2         CONTROL
 116     0x140A0C4C  0x080504EF      0x013F380D      0x00000829
 117     HBP= 20     VBP=  8         BCD=  0
 118     HFP= 10     VFP=  5         CPL=319
 119     HSW= 12     VSW=  1         IOE=  0
 120     PPL= 19     LPP=239         IPC=  1
 121                                 IHS=  1
 122                                 IVS=  1
 123                                 ACB=  0
 124                                 CSEL= 0
 125                                 PCD= 13
 126
 127  */
 128
 129 /* The full horizontal cycle (Th) is clock/360/400/450. */
 130 /* The full vertical   cycle (Tv) is line/251/262/280. */
 131
 132 #define PIX_CLOCK_TARGET        (6300000) /* -/6.3/7 MHz */
 133 #define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
 134 #define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
 135
 136 static struct clcd_panel lcd_panel = {
 137         .mode   = {
 138                 .name           = "5.7in QVGA (LQ057Q3DC02)",
 139                 .xres           = 320,
 140                 .yres           = 240,
 141                 .pixclock       = PIX_CLOCK,
 142                 .left_margin    = 11,
 143                 .right_margin   = 400-11-320-2,
 144                 .upper_margin   = 7,                    // line/7/7/7
 145                 .lower_margin   = 262-7-240-2,
 146                 .hsync_len      = 2,                    // clk/2/96/200
 147                 .vsync_len      = 2,                    // line/2/-/34
 148                 .vmode          = FB_VMODE_NONINTERLACED,
 149         },
 150         .width          = -1,
 151         .height         = -1,
 152         .tim2           = TIM2_IHS | TIM2_IVS
 153                         | (PIX_CLOCK_DIVIDER - 2),
 154         .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
 155         .bpp            = 16,
 156 };
 157
 158 #endif
 159
 160 #if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343
 161
 162         /* Logic Product Development LCD 6.4" VGA -10 */
 163         /* Sharp PN LQ64D343 */
 164
 165 /* The full horizontal cycle (Th) is clock/750/800/900. */
 166 /* The full vertical   cycle (Tv) is line/515/525/560. */
 167
 168 #define PIX_CLOCK_TARGET        (28330000)
 169 #define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
 170 #define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
 171
 172 static struct clcd_panel lcd_panel = {
 173         .mode   = {
 174                 .name           = "6.4in QVGA (LQ64D343)",
 175                 .xres           = 640,
 176                 .yres           = 480,
 177                 .pixclock       = PIX_CLOCK,
 178                 .left_margin    = 32,
 179                 .right_margin   = 800-32-640-96,
 180                 .upper_margin   = 32,                   // line/34/34/34
 181                 .lower_margin   = 540-32-480-2,
 182                 .hsync_len      = 96,                   // clk/2/96/200
 183                 .vsync_len      = 2,                    // line/2/-/34
 184                 .vmode          = FB_VMODE_NONINTERLACED,
 185         },
 186         .width          = -1,
 187         .height         = -1,
 188         .tim2           = TIM2_IHS | TIM2_IVS
 189                         | (PIX_CLOCK_DIVIDER - 2),
 190         .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
 191         .bpp            = 16,
 192 };
 193
 194 #endif
 195
 196 #if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368
 197
 198         /* Logic Product Development LCD 10.4" VGA -10 */
 199         /* Sharp PN LQ10D368 */
 200
 201 #define PIX_CLOCK_TARGET        (28330000)
 202 #define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
 203 #define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
 204
 205 static struct clcd_panel lcd_panel = {
 206         .mode   = {
 207                 .name           = "10.4in VGA (LQ10D368)",
 208                 .xres           = 640,
 209                 .yres           = 480,
 210                 .pixclock       = PIX_CLOCK,
 211                 .left_margin    = 21,
 212                 .right_margin   = 15,
 213                 .upper_margin   = 34,
 214                 .lower_margin   = 5,
 215                 .hsync_len      = 96,
 216                 .vsync_len      = 16,
 217                 .vmode          = FB_VMODE_NONINTERLACED,
 218         },
 219         .width          = -1,
 220         .height         = -1,
 221         .tim2           = TIM2_IHS | TIM2_IVS
 222                         | (PIX_CLOCK_DIVIDER - 2),
 223         .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
 224         .bpp            = 16,
 225 };
 226
 227 #endif
 228
 229 #if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41
 230
 231         /* Logic Product Development LCD 12.1" SVGA -10 */
 232         /* Sharp PN LQ121S1DG41, was LQ121S1DG31 */
 233
 234 /* Note that with a 99993900 Hz HCLK, it is not possible to hit the
 235  * target clock frequency range of 35MHz to 42MHz. */
 236
 237 /* If the target pixel clock is substantially lower than the panel
 238  * spec, this is done to prevent the LCD display from glitching when
 239  * the CPU is under load.  A pixel clock higher than 25MHz
 240  * (empirically determined) will compete with the CPU for bus cycles
 241  * for the Ethernet chip.  However, even a pixel clock of 10MHz
 242  * competes with Compact Flash interface during some operations
 243  * (fdisk, e2fsck).  And, at that speed the display may have a visible
 244  * flicker. */
 245
 246 /* The full horizontal cycle (Th) is clock/832/1056/1395. */
 247
 248 #define PIX_CLOCK_TARGET        (20000000)
 249 #define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
 250 #define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
 251
 252 static struct clcd_panel lcd_panel = {
 253         .mode   = {
 254                 .name           = "12.1in SVGA (LQ121S1DG41)",
 255                 .xres           = 800,
 256                 .yres           = 600,
 257                 .pixclock       = PIX_CLOCK,
 258                 .left_margin    = 89,           // ns/5/-/(1/PIX_CLOCK)-10
 259                 .right_margin   = 1056-800-89-128,
 260                 .upper_margin   = 23,           // line/23/23/23
 261                 .lower_margin   = 44,
 262                 .hsync_len      = 128,          // clk/2/128/200
 263                 .vsync_len      = 4,            // line/2/4/6
 264                 .vmode          = FB_VMODE_NONINTERLACED,
 265         },
 266         .width          = -1,
 267         .height         = -1,
 268         .tim2           = TIM2_IHS | TIM2_IVS
 269                         | (PIX_CLOCK_DIVIDER - 2),
 270         .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
 271         .bpp            = 16,
 272 };
 273
 274 #endif
 275
 276 #if defined CONFIG_FB_ARMCLCD_HITACHI
 277
 278         /* Hitachi*/
 279         /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
 280
 281 #define PIX_CLOCK_TARGET        (49000000)
 282 #define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
 283 #define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
 284
 285 static struct clcd_panel lcd_panel = {
 286         .mode   = {
 287                 .name           = "Hitachi 800x480",
 288                 .xres           = 800,
 289                 .yres           = 480,
 290                 .pixclock       = PIX_CLOCK,
 291                 .left_margin    = 88,
 292                 .right_margin   = 40,
 293                 .upper_margin   = 32,
 294                 .lower_margin   = 11,
 295                 .hsync_len      = 128,
 296                 .vsync_len      = 2,
 297                 .vmode          = FB_VMODE_NONINTERLACED,
 298         },
 299         .width          = -1,
 300         .height         = -1,
 301         .tim2           = TIM2_IPC | TIM2_IHS | TIM2_IVS
 302                         | (PIX_CLOCK_DIVIDER - 2),
 303         .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
 304         .bpp            = 16,
 305 };
 306
 307 #endif
 308
 309
 310 #if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE
 311
 312         /* AU Optotronics  A070VW01 7.0 Wide Screen color Display*/
 313         /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
 314
 315 #define PIX_CLOCK_TARGET        (10000000)
 316 #define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
 317 #define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
 318
 319 static struct clcd_panel lcd_panel = {
 320         .mode   = {
 321                 .name           = "7.0in Wide (A070VW01)",
 322                 .xres           = 480,
 323                 .yres           = 234,
 324                 .pixclock       = PIX_CLOCK,
 325                 .left_margin    = 30,
 326                 .right_margin   = 25,
 327                 .upper_margin   = 14,
 328                 .lower_margin   = 12,
 329                 .hsync_len      = 100,
 330                 .vsync_len      = 1,
 331                 .vmode          = FB_VMODE_NONINTERLACED,
 332         },
 333         .width          = -1,
 334         .height         = -1,
 335         .tim2           = TIM2_IPC | TIM2_IHS | TIM2_IVS
 336                         | (PIX_CLOCK_DIVIDER - 2),
 337         .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
 338         .bpp            = 16,
 339 };
 340
 341 #endif
 342
 343 #undef NS_TO_CLOCK
 344 #undef CLOCK_TO_DIV
 345
 346 #endif  /* __LCD_PANEL_H__ */