drivers/mtd/spi-nor/mtk-quadspi.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Bayi Cheng <bayi.cheng@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/device.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/ioport.h>
  22 #include <linux/math64.h>
  23 #include <linux/module.h>
  24 #include <linux/mutex.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/slab.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/partitions.h>
  31 #include <linux/mtd/spi-nor.h>
  32
  33 #define MTK_NOR_CMD_REG                 0x00
  34 #define MTK_NOR_CNT_REG                 0x04
  35 #define MTK_NOR_RDSR_REG                0x08
  36 #define MTK_NOR_RDATA_REG               0x0c
  37 #define MTK_NOR_RADR0_REG               0x10
  38 #define MTK_NOR_RADR1_REG               0x14
  39 #define MTK_NOR_RADR2_REG               0x18
  40 #define MTK_NOR_WDATA_REG               0x1c
  41 #define MTK_NOR_PRGDATA0_REG            0x20
  42 #define MTK_NOR_PRGDATA1_REG            0x24
  43 #define MTK_NOR_PRGDATA2_REG            0x28
  44 #define MTK_NOR_PRGDATA3_REG            0x2c
  45 #define MTK_NOR_PRGDATA4_REG            0x30
  46 #define MTK_NOR_PRGDATA5_REG            0x34
  47 #define MTK_NOR_SHREG0_REG              0x38
  48 #define MTK_NOR_SHREG1_REG              0x3c
  49 #define MTK_NOR_SHREG2_REG              0x40
  50 #define MTK_NOR_SHREG3_REG              0x44
  51 #define MTK_NOR_SHREG4_REG              0x48
  52 #define MTK_NOR_SHREG5_REG              0x4c
  53 #define MTK_NOR_SHREG6_REG              0x50
  54 #define MTK_NOR_SHREG7_REG              0x54
  55 #define MTK_NOR_SHREG8_REG              0x58
  56 #define MTK_NOR_SHREG9_REG              0x5c
  57 #define MTK_NOR_CFG1_REG                0x60
  58 #define MTK_NOR_CFG2_REG                0x64
  59 #define MTK_NOR_CFG3_REG                0x68
  60 #define MTK_NOR_STATUS0_REG             0x70
  61 #define MTK_NOR_STATUS1_REG             0x74
  62 #define MTK_NOR_STATUS2_REG             0x78
  63 #define MTK_NOR_STATUS3_REG             0x7c
  64 #define MTK_NOR_FLHCFG_REG              0x84
  65 #define MTK_NOR_TIME_REG                0x94
  66 #define MTK_NOR_PP_DATA_REG             0x98
  67 #define MTK_NOR_PREBUF_STUS_REG         0x9c
  68 #define MTK_NOR_DELSEL0_REG             0xa0
  69 #define MTK_NOR_DELSEL1_REG             0xa4
  70 #define MTK_NOR_INTRSTUS_REG            0xa8
  71 #define MTK_NOR_INTREN_REG              0xac
  72 #define MTK_NOR_CHKSUM_CTL_REG          0xb8
  73 #define MTK_NOR_CHKSUM_REG              0xbc
  74 #define MTK_NOR_CMD2_REG                0xc0
  75 #define MTK_NOR_WRPROT_REG              0xc4
  76 #define MTK_NOR_RADR3_REG               0xc8
  77 #define MTK_NOR_DUAL_REG                0xcc
  78 #define MTK_NOR_DELSEL2_REG             0xd0
  79 #define MTK_NOR_DELSEL3_REG             0xd4
  80 #define MTK_NOR_DELSEL4_REG             0xd8
  81
  82 /* commands for mtk nor controller */
  83 #define MTK_NOR_READ_CMD                0x0
  84 #define MTK_NOR_RDSR_CMD                0x2
  85 #define MTK_NOR_PRG_CMD                 0x4
  86 #define MTK_NOR_WR_CMD                  0x10
  87 #define MTK_NOR_PIO_WR_CMD              0x90
  88 #define MTK_NOR_WRSR_CMD                0x20
  89 #define MTK_NOR_PIO_READ_CMD            0x81
  90 #define MTK_NOR_WR_BUF_ENABLE           0x1
  91 #define MTK_NOR_WR_BUF_DISABLE          0x0
  92 #define MTK_NOR_ENABLE_SF_CMD           0x30
  93 #define MTK_NOR_DUAD_ADDR_EN            0x8
  94 #define MTK_NOR_QUAD_READ_EN            0x4
  95 #define MTK_NOR_DUAL_ADDR_EN            0x2
  96 #define MTK_NOR_DUAL_READ_EN            0x1
  97 #define MTK_NOR_DUAL_DISABLE            0x0
  98 #define MTK_NOR_FAST_READ               0x1
  99
 100 #define SFLASH_WRBUF_SIZE               128
 101
 102 /* Can shift up to 48 bits (6 bytes) of TX/RX */
 103 #define MTK_NOR_MAX_RX_TX_SHIFT         6
 104 /* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
 105 #define MTK_NOR_MAX_SHIFT               7
 106 /* nor controller 4-byte address mode enable bit */
 107 #define MTK_NOR_4B_ADDR_EN              BIT(4)
 108
 109 /* Helpers for accessing the program data / shift data registers */
 110 #define MTK_NOR_PRG_REG(n)              (MTK_NOR_PRGDATA0_REG + 4 * (n))
 111 #define MTK_NOR_SHREG(n)                (MTK_NOR_SHREG0_REG + 4 * (n))
 112
 113 struct mt8173_nor {
 114         struct spi_nor nor;
 115         struct device *dev;
 116         void __iomem *base;     /* nor flash base address */
 117         struct clk *spi_clk;
 118         struct clk *nor_clk;
 119 };
 120
 121 static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor)
 122 {
 123         struct spi_nor *nor = &mt8173_nor->nor;
 124
 125         switch (nor->read_proto) {
 126         case SNOR_PROTO_1_1_1:
 127                 writeb(nor->read_opcode, mt8173_nor->base +
 128                        MTK_NOR_PRGDATA3_REG);
 129                 writeb(MTK_NOR_FAST_READ, mt8173_nor->base +
 130                        MTK_NOR_CFG1_REG);
 131                 break;
 132         case SNOR_PROTO_1_1_2:
 133                 writeb(nor->read_opcode, mt8173_nor->base +
 134                        MTK_NOR_PRGDATA3_REG);
 135                 writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base +
 136                        MTK_NOR_DUAL_REG);
 137                 break;
 138         case SNOR_PROTO_1_1_4:
 139                 writeb(nor->read_opcode, mt8173_nor->base +
 140                        MTK_NOR_PRGDATA4_REG);
 141                 writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base +
 142                        MTK_NOR_DUAL_REG);
 143                 break;
 144         default:
 145                 writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base +
 146                        MTK_NOR_DUAL_REG);
 147                 break;
 148         }
 149 }
 150
 151 static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval)
 152 {
 153         int reg;
 154         u8 val = cmdval & 0x1f;
 155
 156         writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG);
 157         return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg,
 158                                   !(reg & val), 100, 10000);
 159 }
 160
 161 static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op,
 162                                u8 *tx, int txlen, u8 *rx, int rxlen)
 163 {
 164         int len = 1 + txlen + rxlen;
 165         int i, ret, idx;
 166
 167         if (len > MTK_NOR_MAX_SHIFT)
 168                 return -EINVAL;
 169
 170         writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG);
 171
 172         /* start at PRGDATA5, go down to PRGDATA0 */
 173         idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;
 174
 175         /* opcode */
 176         writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
 177         idx--;
 178
 179         /* program TX data */
 180         for (i = 0; i < txlen; i++, idx--)
 181                 writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx));
 182
 183         /* clear out rest of TX registers */
 184         while (idx >= 0) {
 185                 writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
 186                 idx--;
 187         }
 188
 189         ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD);
 190         if (ret)
 191                 return ret;
 192
 193         /* restart at first RX byte */
 194         idx = rxlen - 1;
 195
 196         /* read out RX data */
 197         for (i = 0; i < rxlen; i++, idx--)
 198                 rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx));
 199
 200         return 0;
 201 }
 202
 203 /* Do a WRSR (Write Status Register) command */
 204 static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr)
 205 {
 206         writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG);
 207         writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG);
 208         return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD);
 209 }
 210
 211 static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor)
 212 {
 213         u8 reg;
 214
 215         /* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
 216          * 0: pre-fetch buffer use for read
 217          * 1: pre-fetch buffer use for page program
 218          */
 219         writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
 220         return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
 221                                   0x01 == (reg & 0x01), 100, 10000);
 222 }
 223
 224 static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor)
 225 {
 226         u8 reg;
 227
 228         writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
 229         return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
 230                                   MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
 231                                   10000);
 232 }
 233
 234 static void mt8173_nor_set_addr_width(struct mt8173_nor *mt8173_nor)
 235 {
 236         u8 val;
 237         struct spi_nor *nor = &mt8173_nor->nor;
 238
 239         val = readb(mt8173_nor->base + MTK_NOR_DUAL_REG);
 240
 241         switch (nor->addr_width) {
 242         case 3:
 243                 val &= ~MTK_NOR_4B_ADDR_EN;
 244                 break;
 245         case 4:
 246                 val |= MTK_NOR_4B_ADDR_EN;
 247                 break;
 248         default:
 249                 dev_warn(mt8173_nor->dev, "Unexpected address width %u.\n",
 250                          nor->addr_width);
 251                 break;
 252         }
 253
 254         writeb(val, mt8173_nor->base + MTK_NOR_DUAL_REG);
 255 }
 256
 257 static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr)
 258 {
 259         int i;
 260
 261         mt8173_nor_set_addr_width(mt8173_nor);
 262
 263         for (i = 0; i < 3; i++) {
 264                 writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4);
 265                 addr >>= 8;
 266         }
 267         /* Last register is non-contiguous */
 268         writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG);
 269 }
 270
 271 static ssize_t mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length,
 272                                u_char *buffer)
 273 {
 274         int i, ret;
 275         int addr = (int)from;
 276         u8 *buf = (u8 *)buffer;
 277         struct mt8173_nor *mt8173_nor = nor->priv;
 278
 279         /* set mode for fast read mode ,dual mode or quad mode */
 280         mt8173_nor_set_read_mode(mt8173_nor);
 281         mt8173_nor_set_addr(mt8173_nor, addr);
 282
 283         for (i = 0; i < length; i++) {
 284                 ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD);
 285                 if (ret < 0)
 286                         return ret;
 287                 buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG);
 288         }
 289         return length;
 290 }
 291
 292 static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor,
 293                                         int addr, int length, u8 *data)
 294 {
 295         int i, ret;
 296
 297         mt8173_nor_set_addr(mt8173_nor, addr);
 298
 299         for (i = 0; i < length; i++) {
 300                 writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG);
 301                 ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD);
 302                 if (ret < 0)
 303                         return ret;
 304         }
 305         return 0;
 306 }
 307
 308 static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr,
 309                                    const u8 *buf)
 310 {
 311         int i, bufidx, data;
 312
 313         mt8173_nor_set_addr(mt8173_nor, addr);
 314
 315         bufidx = 0;
 316         for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
 317                 data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 |
 318                        buf[bufidx + 1]<<8 | buf[bufidx];
 319                 bufidx += 4;
 320                 writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG);
 321         }
 322         return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD);
 323 }
 324
 325 static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len,
 326                                 const u_char *buf)
 327 {
 328         int ret;
 329         struct mt8173_nor *mt8173_nor = nor->priv;
 330         size_t i;
 331
 332         ret = mt8173_nor_write_buffer_enable(mt8173_nor);
 333         if (ret < 0) {
 334                 dev_warn(mt8173_nor->dev, "write buffer enable failed!\n");
 335                 return ret;
 336         }
 337
 338         for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
 339                 ret = mt8173_nor_write_buffer(mt8173_nor, to, buf);
 340                 if (ret < 0) {
 341                         dev_err(mt8173_nor->dev, "write buffer failed!\n");
 342                         return ret;
 343                 }
 344                 to += SFLASH_WRBUF_SIZE;
 345                 buf += SFLASH_WRBUF_SIZE;
 346         }
 347         ret = mt8173_nor_write_buffer_disable(mt8173_nor);
 348         if (ret < 0) {
 349                 dev_warn(mt8173_nor->dev, "write buffer disable failed!\n");
 350                 return ret;
 351         }
 352
 353         if (i < len) {
 354                 ret = mt8173_nor_write_single_byte(mt8173_nor, to,
 355                                                    (int)(len - i), (u8 *)buf);
 356                 if (ret < 0) {
 357                         dev_err(mt8173_nor->dev, "write single byte failed!\n");
 358                         return ret;
 359                 }
 360         }
 361
 362         return len;
 363 }
 364
 365 static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 366 {
 367         int ret;
 368         struct mt8173_nor *mt8173_nor = nor->priv;
 369
 370         switch (opcode) {
 371         case SPINOR_OP_RDSR:
 372                 ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD);
 373                 if (ret < 0)
 374                         return ret;
 375                 if (len == 1)
 376                         *buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG);
 377                 else
 378                         dev_err(mt8173_nor->dev, "len should be 1 for read status!\n");
 379                 break;
 380         default:
 381                 ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len);
 382                 break;
 383         }
 384         return ret;
 385 }
 386
 387 static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
 388                                 int len)
 389 {
 390         int ret;
 391         struct mt8173_nor *mt8173_nor = nor->priv;
 392
 393         switch (opcode) {
 394         case SPINOR_OP_WRSR:
 395                 /* We only handle 1 byte */
 396                 ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
 397                 break;
 398         default:
 399                 ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
 400                 if (ret)
 401                         dev_warn(mt8173_nor->dev, "write reg failure!\n");
 402                 break;
 403         }
 404         return ret;
 405 }
 406
 407 static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
 408                         struct device_node *flash_node)
 409 {
 410         const struct spi_nor_hwcaps hwcaps = {
 411                 .mask = SNOR_HWCAPS_READ_FAST |
 412                         SNOR_HWCAPS_READ_1_1_2 |
 413                         SNOR_HWCAPS_PP,
 414         };
 415         int ret;
 416         struct spi_nor *nor;
 417
 418         /* initialize controller to accept commands */
 419         writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG);
 420
 421         nor = &mt8173_nor->nor;
 422         nor->dev = mt8173_nor->dev;
 423         nor->priv = mt8173_nor;
 424         spi_nor_set_flash_node(nor, flash_node);
 425
 426         /* fill the hooks to spi nor */
 427         nor->read = mt8173_nor_read;
 428         nor->read_reg = mt8173_nor_read_reg;
 429         nor->write = mt8173_nor_write;
 430         nor->write_reg = mt8173_nor_write_reg;
 431         nor->mtd.name = "mtk_nor";
 432         /* initialized with NULL */
 433         ret = spi_nor_scan(nor, NULL, &hwcaps);
 434         if (ret)
 435                 return ret;
 436
 437         return mtd_device_register(&nor->mtd, NULL, 0);
 438 }
 439
 440 static int mtk_nor_drv_probe(struct platform_device *pdev)
 441 {
 442         struct device_node *flash_np;
 443         struct resource *res;
 444         int ret;
 445         struct mt8173_nor *mt8173_nor;
 446
 447         if (!pdev->dev.of_node) {
 448                 dev_err(&pdev->dev, "No DT found\n");
 449                 return -EINVAL;
 450         }
 451
 452         mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL);
 453         if (!mt8173_nor)
 454                 return -ENOMEM;
 455         platform_set_drvdata(pdev, mt8173_nor);
 456
 457         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 458         mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res);
 459         if (IS_ERR(mt8173_nor->base))
 460                 return PTR_ERR(mt8173_nor->base);
 461
 462         mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
 463         if (IS_ERR(mt8173_nor->spi_clk))
 464                 return PTR_ERR(mt8173_nor->spi_clk);
 465
 466         mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
 467         if (IS_ERR(mt8173_nor->nor_clk))
 468                 return PTR_ERR(mt8173_nor->nor_clk);
 469
 470         mt8173_nor->dev = &pdev->dev;
 471         ret = clk_prepare_enable(mt8173_nor->spi_clk);
 472         if (ret)
 473                 return ret;
 474
 475         ret = clk_prepare_enable(mt8173_nor->nor_clk);
 476         if (ret) {
 477                 clk_disable_unprepare(mt8173_nor->spi_clk);
 478                 return ret;
 479         }
 480         /* only support one attached flash */
 481         flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
 482         if (!flash_np) {
 483                 dev_err(&pdev->dev, "no SPI flash device to configure\n");
 484                 ret = -ENODEV;
 485                 goto nor_free;
 486         }
 487         ret = mtk_nor_init(mt8173_nor, flash_np);
 488
 489 nor_free:
 490         if (ret) {
 491                 clk_disable_unprepare(mt8173_nor->spi_clk);
 492                 clk_disable_unprepare(mt8173_nor->nor_clk);
 493         }
 494         return ret;
 495 }
 496
 497 static int mtk_nor_drv_remove(struct platform_device *pdev)
 498 {
 499         struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev);
 500
 501         clk_disable_unprepare(mt8173_nor->spi_clk);
 502         clk_disable_unprepare(mt8173_nor->nor_clk);
 503         return 0;
 504 }
 505
 506 static const struct of_device_id mtk_nor_of_ids[] = {
 507         { .compatible = "mediatek,mt8173-nor"},
 508         { /* sentinel */ }
 509 };
 510 MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);
 511
 512 static struct platform_driver mtk_nor_driver = {
 513         .probe = mtk_nor_drv_probe,
 514         .remove = mtk_nor_drv_remove,
 515         .driver = {
 516                 .name = "mtk-nor",
 517                 .of_match_table = mtk_nor_of_ids,
 518         },
 519 };
 520
 521 module_platform_driver(mtk_nor_driver);
 522 MODULE_LICENSE("GPL v2");
 523 MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");