drivers/irqchip/irq-lpc32xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
   4  */
   5
   6 #define pr_fmt(fmt) "%s: " fmt, __func__
   7
   8 #include <linux/io.h>
   9 #include <linux/irqchip.h>
  10 #include <linux/irqchip/chained_irq.h>
  11 #include <linux/of_address.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/slab.h>
  15 #include <asm/exception.h>
  16
  17 #define LPC32XX_INTC_MASK               0x00
  18 #define LPC32XX_INTC_RAW                0x04
  19 #define LPC32XX_INTC_STAT               0x08
  20 #define LPC32XX_INTC_POL                0x0C
  21 #define LPC32XX_INTC_TYPE               0x10
  22 #define LPC32XX_INTC_FIQ                0x14
  23
  24 #define NR_LPC32XX_IC_IRQS              32
  25
  26 struct lpc32xx_irq_chip {
  27         void __iomem *base;
  28         struct irq_domain *domain;
  29         struct irq_chip chip;
  30 };
  31
  32 static struct lpc32xx_irq_chip *lpc32xx_mic_irqc;
  33
  34 static inline u32 lpc32xx_ic_read(struct lpc32xx_irq_chip *ic, u32 reg)
  35 {
  36         return readl_relaxed(ic->base + reg);
  37 }
  38
  39 static inline void lpc32xx_ic_write(struct lpc32xx_irq_chip *ic,
  40                                     u32 reg, u32 val)
  41 {
  42         writel_relaxed(val, ic->base + reg);
  43 }
  44
  45 static void lpc32xx_irq_mask(struct irq_data *d)
  46 {
  47         struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
  48         u32 val, mask = BIT(d->hwirq);
  49
  50         val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) & ~mask;
  51         lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
  52 }
  53
  54 static void lpc32xx_irq_unmask(struct irq_data *d)
  55 {
  56         struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
  57         u32 val, mask = BIT(d->hwirq);
  58
  59         val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) | mask;
  60         lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
  61 }
  62
  63 static void lpc32xx_irq_ack(struct irq_data *d)
  64 {
  65         struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
  66         u32 mask = BIT(d->hwirq);
  67
  68         lpc32xx_ic_write(ic, LPC32XX_INTC_RAW, mask);
  69 }
  70
  71 static int lpc32xx_irq_set_type(struct irq_data *d, unsigned int type)
  72 {
  73         struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
  74         u32 val, mask = BIT(d->hwirq);
  75         bool high, edge;
  76
  77         switch (type) {
  78         case IRQ_TYPE_EDGE_RISING:
  79                 edge = true;
  80                 high = true;
  81                 break;
  82         case IRQ_TYPE_EDGE_FALLING:
  83                 edge = true;
  84                 high = false;
  85                 break;
  86         case IRQ_TYPE_LEVEL_HIGH:
  87                 edge = false;
  88                 high = true;
  89                 break;
  90         case IRQ_TYPE_LEVEL_LOW:
  91                 edge = false;
  92                 high = false;
  93                 break;
  94         default:
  95                 pr_info("unsupported irq type %d\n", type);
  96                 return -EINVAL;
  97         }
  98
  99         irqd_set_trigger_type(d, type);
 100
 101         val = lpc32xx_ic_read(ic, LPC32XX_INTC_POL);
 102         if (high)
 103                 val |= mask;
 104         else
 105                 val &= ~mask;
 106         lpc32xx_ic_write(ic, LPC32XX_INTC_POL, val);
 107
 108         val = lpc32xx_ic_read(ic, LPC32XX_INTC_TYPE);
 109         if (edge) {
 110                 val |= mask;
 111                 irq_set_handler_locked(d, handle_edge_irq);
 112         } else {
 113                 val &= ~mask;
 114                 irq_set_handler_locked(d, handle_level_irq);
 115         }
 116         lpc32xx_ic_write(ic, LPC32XX_INTC_TYPE, val);
 117
 118         return 0;
 119 }
 120
 121 static void __exception_irq_entry lpc32xx_handle_irq(struct pt_regs *regs)
 122 {
 123         struct lpc32xx_irq_chip *ic = lpc32xx_mic_irqc;
 124         u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
 125
 126         while (hwirq) {
 127                 irq = __ffs(hwirq);
 128                 hwirq &= ~BIT(irq);
 129                 handle_domain_irq(lpc32xx_mic_irqc->domain, irq, regs);
 130         }
 131 }
 132
 133 static void lpc32xx_sic_handler(struct irq_desc *desc)
 134 {
 135         struct lpc32xx_irq_chip *ic = irq_desc_get_handler_data(desc);
 136         struct irq_chip *chip = irq_desc_get_chip(desc);
 137         u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
 138
 139         chained_irq_enter(chip, desc);
 140
 141         while (hwirq) {
 142                 irq = __ffs(hwirq);
 143                 hwirq &= ~BIT(irq);
 144                 generic_handle_irq(irq_find_mapping(ic->domain, irq));
 145         }
 146
 147         chained_irq_exit(chip, desc);
 148 }
 149
 150 static int lpc32xx_irq_domain_map(struct irq_domain *id, unsigned int virq,
 151                                   irq_hw_number_t hw)
 152 {
 153         struct lpc32xx_irq_chip *ic = id->host_data;
 154
 155         irq_set_chip_data(virq, ic);
 156         irq_set_chip_and_handler(virq, &ic->chip, handle_level_irq);
 157         irq_set_status_flags(virq, IRQ_LEVEL);
 158         irq_set_noprobe(virq);
 159
 160         return 0;
 161 }
 162
 163 static void lpc32xx_irq_domain_unmap(struct irq_domain *id, unsigned int virq)
 164 {
 165         irq_set_chip_and_handler(virq, NULL, NULL);
 166 }
 167
 168 static const struct irq_domain_ops lpc32xx_irq_domain_ops = {
 169         .map    = lpc32xx_irq_domain_map,
 170         .unmap  = lpc32xx_irq_domain_unmap,
 171         .xlate  = irq_domain_xlate_twocell,
 172 };
 173
 174 static int __init lpc32xx_of_ic_init(struct device_node *node,
 175                                      struct device_node *parent)
 176 {
 177         struct lpc32xx_irq_chip *irqc;
 178         bool is_mic = of_device_is_compatible(node, "nxp,lpc3220-mic");
 179         const __be32 *reg = of_get_property(node, "reg", NULL);
 180         u32 parent_irq, i, addr = reg ? be32_to_cpu(*reg) : 0;
 181
 182         irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
 183         if (!irqc)
 184                 return -ENOMEM;
 185
 186         irqc->base = of_iomap(node, 0);
 187         if (!irqc->base) {
 188                 pr_err("%pOF: unable to map registers\n", node);
 189                 kfree(irqc);
 190                 return -EINVAL;
 191         }
 192
 193         irqc->chip.irq_ack = lpc32xx_irq_ack;
 194         irqc->chip.irq_mask = lpc32xx_irq_mask;
 195         irqc->chip.irq_unmask = lpc32xx_irq_unmask;
 196         irqc->chip.irq_set_type = lpc32xx_irq_set_type;
 197         if (is_mic)
 198                 irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.mic", addr);
 199         else
 200                 irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.sic", addr);
 201
 202         irqc->domain = irq_domain_add_linear(node, NR_LPC32XX_IC_IRQS,
 203                                              &lpc32xx_irq_domain_ops, irqc);
 204         if (!irqc->domain) {
 205                 pr_err("unable to add irq domain\n");
 206                 iounmap(irqc->base);
 207                 kfree(irqc->chip.name);
 208                 kfree(irqc);
 209                 return -ENODEV;
 210         }
 211
 212         if (is_mic) {
 213                 lpc32xx_mic_irqc = irqc;
 214                 set_handle_irq(lpc32xx_handle_irq);
 215         } else {
 216                 for (i = 0; i < of_irq_count(node); i++) {
 217                         parent_irq = irq_of_parse_and_map(node, i);
 218                         if (parent_irq)
 219                                 irq_set_chained_handler_and_data(parent_irq,
 220                                                  lpc32xx_sic_handler, irqc);
 221                 }
 222         }
 223
 224         lpc32xx_ic_write(irqc, LPC32XX_INTC_MASK, 0x00);
 225         lpc32xx_ic_write(irqc, LPC32XX_INTC_POL,  0x00);
 226         lpc32xx_ic_write(irqc, LPC32XX_INTC_TYPE, 0x00);
 227
 228         return 0;
 229 }
 230
 231 IRQCHIP_DECLARE(nxp_lpc32xx_mic, "nxp,lpc3220-mic", lpc32xx_of_ic_init);
 232 IRQCHIP_DECLARE(nxp_lpc32xx_sic, "nxp,lpc3220-sic", lpc32xx_of_ic_init);