1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define FEC_MAX_MULTICAST_ADDRS 64
7 /* Interrupt events/masks.
9 #define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */
10 #define FEC_ENET_BABR 0x40000000U /* Babbling receiver */
11 #define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */
12 #define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */
13 #define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
14 #define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */
15 #define FEC_ENET_RXF 0x02000000U /* Full frame received */
16 #define FEC_ENET_RXB 0x01000000U /* A buffer was received */
17 #define FEC_ENET_MII 0x00800000U /* MII interrupt */
18 #define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */
20 #define FEC_ECNTRL_PINMUX 0x00000004
21 #define FEC_ECNTRL_ETHER_EN 0x00000002
22 #define FEC_ECNTRL_RESET 0x00000001
24 /* RMII mode enabled only when MII_MODE bit is set too. */
25 #define FEC_RCNTRL_RMII_MODE (0x00000100 | \
26 FEC_RCNTRL_MII_MODE | FEC_RCNTRL_FCE)
27 #define FEC_RCNTRL_FCE 0x00000020
28 #define FEC_RCNTRL_BC_REJ 0x00000010
29 #define FEC_RCNTRL_PROM 0x00000008
30 #define FEC_RCNTRL_MII_MODE 0x00000004
31 #define FEC_RCNTRL_DRT 0x00000002
32 #define FEC_RCNTRL_LOOP 0x00000001
34 #define FEC_TCNTRL_FDEN 0x00000004
35 #define FEC_TCNTRL_HBC 0x00000002
36 #define FEC_TCNTRL_GTS 0x00000001
39 * Delay to wait for FEC reset command to complete (in us)
41 #define FEC_RESET_DELAY 50