drivers/net/wireless/ath/ath10k/pci.h

   1 /* SPDX-License-Identifier: ISC */
   2 /*
   3  * Copyright (c) 2005-2011 Atheros Communications Inc.
   4  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
   5  */
   6
   7 #ifndef _PCI_H_
   8 #define _PCI_H_
   9
  10 #include <linux/interrupt.h>
  11 #include <linux/mutex.h>
  12
  13 #include "hw.h"
  14 #include "ce.h"
  15 #include "ahb.h"
  16
  17 /*
  18  * maximum number of bytes that can be
  19  * handled atomically by DiagRead/DiagWrite
  20  */
  21 #define DIAG_TRANSFER_LIMIT 2048
  22
  23 struct bmi_xfer {
  24         bool tx_done;
  25         bool rx_done;
  26         bool wait_for_resp;
  27         u32 resp_len;
  28 };
  29
  30 /*
  31  * PCI-specific Target state
  32  *
  33  * NOTE: Structure is shared between Host software and Target firmware!
  34  *
  35  * Much of this may be of interest to the Host so
  36  * HOST_INTEREST->hi_interconnect_state points here
  37  * (and all members are 32-bit quantities in order to
  38  * facilitate Host access). In particular, Host software is
  39  * required to initialize pipe_cfg_addr and svc_to_pipe_map.
  40  */
  41 struct pcie_state {
  42         /* Pipe configuration Target address */
  43         /* NB: ce_pipe_config[CE_COUNT] */
  44         u32 pipe_cfg_addr;
  45
  46         /* Service to pipe map Target address */
  47         /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
  48         u32 svc_to_pipe_map;
  49
  50         /* number of MSI interrupts requested */
  51         u32 msi_requested;
  52
  53         /* number of MSI interrupts granted */
  54         u32 msi_granted;
  55
  56         /* Message Signalled Interrupt address */
  57         u32 msi_addr;
  58
  59         /* Base data */
  60         u32 msi_data;
  61
  62         /*
  63          * Data for firmware interrupt;
  64          * MSI data for other interrupts are
  65          * in various SoC registers
  66          */
  67         u32 msi_fw_intr_data;
  68
  69         /* PCIE_PWR_METHOD_* */
  70         u32 power_mgmt_method;
  71
  72         /* PCIE_CONFIG_FLAG_* */
  73         u32 config_flags;
  74 };
  75
  76 /* PCIE_CONFIG_FLAG definitions */
  77 #define PCIE_CONFIG_FLAG_ENABLE_L1  0x0000001
  78
  79 /* Per-pipe state. */
  80 struct ath10k_pci_pipe {
  81         /* Handle of underlying Copy Engine */
  82         struct ath10k_ce_pipe *ce_hdl;
  83
  84         /* Our pipe number; facilitiates use of pipe_info ptrs. */
  85         u8 pipe_num;
  86
  87         /* Convenience back pointer to hif_ce_state. */
  88         struct ath10k *hif_ce_state;
  89
  90         size_t buf_sz;
  91
  92         /* protects compl_free and num_send_allowed */
  93         spinlock_t pipe_lock;
  94 };
  95
  96 struct ath10k_pci_supp_chip {
  97         u32 dev_id;
  98         u32 rev_id;
  99 };
 100
 101 enum ath10k_pci_irq_mode {
 102         ATH10K_PCI_IRQ_AUTO = 0,
 103         ATH10K_PCI_IRQ_LEGACY = 1,
 104         ATH10K_PCI_IRQ_MSI = 2,
 105 };
 106
 107 struct ath10k_pci {
 108         struct pci_dev *pdev;
 109         struct device *dev;
 110         struct ath10k *ar;
 111         void __iomem *mem;
 112         size_t mem_len;
 113
 114         /* Operating interrupt mode */
 115         enum ath10k_pci_irq_mode oper_irq_mode;
 116
 117         struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
 118
 119         /* Copy Engine used for Diagnostic Accesses */
 120         struct ath10k_ce_pipe *ce_diag;
 121         /* For protecting ce_diag */
 122         struct mutex ce_diag_mutex;
 123
 124         struct work_struct dump_work;
 125
 126         struct ath10k_ce ce;
 127         struct timer_list rx_post_retry;
 128
 129         /* Due to HW quirks it is recommended to disable ASPM during device
 130          * bootup. To do that the original PCI-E Link Control is stored before
 131          * device bootup is executed and re-programmed later.
 132          */
 133         u16 link_ctl;
 134
 135         /* Protects ps_awake and ps_wake_refcount */
 136         spinlock_t ps_lock;
 137
 138         /* The device has a special powersave-oriented register. When device is
 139          * considered asleep it drains less power and driver is forbidden from
 140          * accessing most MMIO registers. If host were to access them without
 141          * waking up the device might scribble over host memory or return
 142          * 0xdeadbeef readouts.
 143          */
 144         unsigned long ps_wake_refcount;
 145
 146         /* Waking up takes some time (up to 2ms in some cases) so it can be bad
 147          * for latency. To mitigate this the device isn't immediately allowed
 148          * to sleep after all references are undone - instead there's a grace
 149          * period after which the powersave register is updated unless some
 150          * activity to/from device happened in the meantime.
 151          *
 152          * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
 153          */
 154         struct timer_list ps_timer;
 155
 156         /* MMIO registers are used to communicate with the device. With
 157          * intensive traffic accessing powersave register would be a bit
 158          * wasteful overhead and would needlessly stall CPU. It is far more
 159          * efficient to rely on a variable in RAM and update it only upon
 160          * powersave register state changes.
 161          */
 162         bool ps_awake;
 163
 164         /* pci power save, disable for QCA988X and QCA99X0.
 165          * Writing 'false' to this variable avoids frequent locking
 166          * on MMIO read/write.
 167          */
 168         bool pci_ps;
 169
 170         /* Chip specific pci reset routine used to do a safe reset */
 171         int (*pci_soft_reset)(struct ath10k *ar);
 172
 173         /* Chip specific pci full reset function */
 174         int (*pci_hard_reset)(struct ath10k *ar);
 175
 176         /* chip specific methods for converting target CPU virtual address
 177          * space to CE address space
 178          */
 179         u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
 180
 181         /* Keep this entry in the last, memory for struct ath10k_ahb is
 182          * allocated (ahb support enabled case) in the continuation of
 183          * this struct.
 184          */
 185         struct ath10k_ahb ahb[0];
 186 };
 187
 188 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
 189 {
 190         return (struct ath10k_pci *)ar->drv_priv;
 191 }
 192
 193 #define ATH10K_PCI_RX_POST_RETRY_MS 50
 194 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
 195 #define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
 196 #define PCIE_WAKE_LATE_US 10000 /* 10ms */
 197
 198 #define BAR_NUM 0
 199
 200 #define CDC_WAR_MAGIC_STR   0xceef0000
 201 #define CDC_WAR_DATA_CE     4
 202
 203 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
 204 #define DIAG_ACCESS_CE_TIMEOUT_US 10000 /* 10 ms */
 205 #define DIAG_ACCESS_CE_WAIT_US  50
 206
 207 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
 208 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
 209 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
 210
 211 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
 212 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
 213 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
 214
 215 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
 216                          struct ath10k_hif_sg_item *items, int n_items);
 217 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
 218                              size_t buf_len);
 219 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
 220                               const void *data, int nbytes);
 221 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
 222                                     void *resp, u32 *resp_len);
 223 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
 224                                        u8 *ul_pipe, u8 *dl_pipe);
 225 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
 226                                      u8 *dl_pipe);
 227 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
 228                                         int force);
 229 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
 230 void ath10k_pci_hif_power_down(struct ath10k *ar);
 231 int ath10k_pci_alloc_pipes(struct ath10k *ar);
 232 void ath10k_pci_free_pipes(struct ath10k *ar);
 233 void ath10k_pci_free_pipes(struct ath10k *ar);
 234 void ath10k_pci_rx_replenish_retry(struct timer_list *t);
 235 void ath10k_pci_ce_deinit(struct ath10k *ar);
 236 void ath10k_pci_init_napi(struct ath10k *ar);
 237 int ath10k_pci_init_pipes(struct ath10k *ar);
 238 int ath10k_pci_init_config(struct ath10k *ar);
 239 void ath10k_pci_rx_post(struct ath10k *ar);
 240 void ath10k_pci_flush(struct ath10k *ar);
 241 void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
 242 bool ath10k_pci_irq_pending(struct ath10k *ar);
 243 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
 244 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
 245 int ath10k_pci_wait_for_target_init(struct ath10k *ar);
 246 int ath10k_pci_setup_resource(struct ath10k *ar);
 247 void ath10k_pci_release_resource(struct ath10k *ar);
 248
 249 /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
 250  * frequently. To avoid this put SoC to sleep after a very conservative grace
 251  * period. Adjust with great care.
 252  */
 253 #define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
 254
 255 #endif /* _PCI_H_ */