2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 /*********************************\
24 * Protocol Control Unit Functions *
25 \*********************************/
27 #include <asm/unaligned.h>
34 * DOC: Protocol Control Unit (PCU) functions
36 * Protocol control unit is responsible to maintain various protocol
37 * properties before a frame is send and after a frame is received to/from
38 * baseband. To be more specific, PCU handles:
40 * - Buffering of RX and TX frames (after QCU/DCUs)
42 * - Encrypting and decrypting (using the built-in engine)
44 * - Generating ACKs, RTS/CTS frames
50 * - Updating beacon data (with TSF etc)
52 * - Generating virtual CCA
54 * - RX/Multicast filtering
58 * - Various statistics
60 * -Different operating modes: AP, STA, IBSS
62 * Note: Most of these functions can be tweaked/bypassed so you can do
63 * them on sw above for debugging or research. For more infos check out PCU
70 * AR5212+ can use higher rates for ack transmission
71 * based on current tx rate instead of the base rate.
72 * It does this to better utilize channel usage.
73 * There is a mapping between G rates (that cover both
74 * CCK and OFDM) and ack rates that we use when setting
75 * rate -> duration table. This mapping is hw-based so
76 * don't change anything.
78 * To enable this functionality we must set
79 * ah->ah_ack_bitrate_high to true else base rate is
80 * used (1Mb for CCK, 6Mb for OFDM).
82 static const unsigned int ack_rates_high
[] =
95 /* 54Mb -> 24Mb */ 8 };
102 * ath5k_hw_get_frame_duration() - Get tx time of a frame
103 * @ah: The &struct ath5k_hw
104 * @len: Frame's length in bytes
105 * @rate: The @struct ieee80211_rate
106 * @shortpre: Indicate short preample
108 * Calculate tx duration of a frame given it's rate and length
109 * It extends ieee80211_generic_frame_duration for non standard
113 ath5k_hw_get_frame_duration(struct ath5k_hw
*ah
, enum nl80211_band band
,
114 int len
, struct ieee80211_rate
*rate
, bool shortpre
)
116 int sifs
, preamble
, plcp_bits
, sym_time
;
117 int bitrate
, bits
, symbols
, symbol_bits
;
121 if (!ah
->ah_bwmode
) {
122 __le16 raw_dur
= ieee80211_generic_frame_duration(ah
->hw
,
123 NULL
, band
, len
, rate
);
125 /* subtract difference between long and short preamble */
126 dur
= le16_to_cpu(raw_dur
);
133 bitrate
= rate
->bitrate
;
134 preamble
= AR5K_INIT_OFDM_PREAMPLE_TIME
;
135 plcp_bits
= AR5K_INIT_OFDM_PLCP_BITS
;
136 sym_time
= AR5K_INIT_OFDM_SYMBOL_TIME
;
138 switch (ah
->ah_bwmode
) {
139 case AR5K_BWMODE_40MHZ
:
140 sifs
= AR5K_INIT_SIFS_TURBO
;
141 preamble
= AR5K_INIT_OFDM_PREAMBLE_TIME_MIN
;
143 case AR5K_BWMODE_10MHZ
:
144 sifs
= AR5K_INIT_SIFS_HALF_RATE
;
147 bitrate
= DIV_ROUND_UP(bitrate
, 2);
149 case AR5K_BWMODE_5MHZ
:
150 sifs
= AR5K_INIT_SIFS_QUARTER_RATE
;
153 bitrate
= DIV_ROUND_UP(bitrate
, 4);
156 sifs
= AR5K_INIT_SIFS_DEFAULT_BG
;
160 bits
= plcp_bits
+ (len
<< 3);
161 /* Bit rate is in 100Kbits */
162 symbol_bits
= bitrate
* sym_time
;
163 symbols
= DIV_ROUND_UP(bits
* 10, symbol_bits
);
165 dur
= sifs
+ preamble
+ (sym_time
* symbols
);
171 * ath5k_hw_get_default_slottime() - Get the default slot time for current mode
172 * @ah: The &struct ath5k_hw
175 ath5k_hw_get_default_slottime(struct ath5k_hw
*ah
)
177 struct ieee80211_channel
*channel
= ah
->ah_current_channel
;
178 unsigned int slot_time
;
180 switch (ah
->ah_bwmode
) {
181 case AR5K_BWMODE_40MHZ
:
182 slot_time
= AR5K_INIT_SLOT_TIME_TURBO
;
184 case AR5K_BWMODE_10MHZ
:
185 slot_time
= AR5K_INIT_SLOT_TIME_HALF_RATE
;
187 case AR5K_BWMODE_5MHZ
:
188 slot_time
= AR5K_INIT_SLOT_TIME_QUARTER_RATE
;
190 case AR5K_BWMODE_DEFAULT
:
192 slot_time
= AR5K_INIT_SLOT_TIME_DEFAULT
;
193 if ((channel
->hw_value
== AR5K_MODE_11B
) && !ah
->ah_short_slot
)
194 slot_time
= AR5K_INIT_SLOT_TIME_B
;
202 * ath5k_hw_get_default_sifs() - Get the default SIFS for current mode
203 * @ah: The &struct ath5k_hw
206 ath5k_hw_get_default_sifs(struct ath5k_hw
*ah
)
208 struct ieee80211_channel
*channel
= ah
->ah_current_channel
;
211 switch (ah
->ah_bwmode
) {
212 case AR5K_BWMODE_40MHZ
:
213 sifs
= AR5K_INIT_SIFS_TURBO
;
215 case AR5K_BWMODE_10MHZ
:
216 sifs
= AR5K_INIT_SIFS_HALF_RATE
;
218 case AR5K_BWMODE_5MHZ
:
219 sifs
= AR5K_INIT_SIFS_QUARTER_RATE
;
221 case AR5K_BWMODE_DEFAULT
:
223 sifs
= AR5K_INIT_SIFS_DEFAULT_BG
;
224 if (channel
->band
== NL80211_BAND_5GHZ
)
225 sifs
= AR5K_INIT_SIFS_DEFAULT_A
;
233 * ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics)
234 * @ah: The &struct ath5k_hw
236 * Reads MIB counters from PCU and updates sw statistics. Is called after a
237 * MIB interrupt, because one of these counters might have reached their maximum
238 * and triggered the MIB interrupt, to let us read and clear the counter.
240 * NOTE: Is called in interrupt context!
243 ath5k_hw_update_mib_counters(struct ath5k_hw
*ah
)
245 struct ath5k_statistics
*stats
= &ah
->stats
;
248 stats
->ack_fail
+= ath5k_hw_reg_read(ah
, AR5K_ACK_FAIL
);
249 stats
->rts_fail
+= ath5k_hw_reg_read(ah
, AR5K_RTS_FAIL
);
250 stats
->rts_ok
+= ath5k_hw_reg_read(ah
, AR5K_RTS_OK
);
251 stats
->fcs_error
+= ath5k_hw_reg_read(ah
, AR5K_FCS_FAIL
);
252 stats
->beacons
+= ath5k_hw_reg_read(ah
, AR5K_BEACON_CNT
);
261 * ath5k_hw_write_rate_duration() - Fill rate code to duration table
262 * @ah: The &struct ath5k_hw
264 * Write the rate code to duration table upon hw reset. This is a helper for
265 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on
266 * the hardware, based on current mode, for each rate. The rates which are
267 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
268 * different rate code so we write their value twice (one for long preamble
269 * and one for short).
271 * Note: Band doesn't matter here, if we set the values for OFDM it works
272 * on both a and g modes. So all we have to do is set values for all g rates
273 * that include all OFDM and CCK rates.
277 ath5k_hw_write_rate_duration(struct ath5k_hw
*ah
)
279 struct ieee80211_rate
*rate
;
281 /* 802.11g covers both OFDM and CCK */
282 u8 band
= NL80211_BAND_2GHZ
;
284 /* Write rate duration table */
285 for (i
= 0; i
< ah
->sbands
[band
].n_bitrates
; i
++) {
289 if (ah
->ah_ack_bitrate_high
)
290 rate
= &ah
->sbands
[band
].bitrates
[ack_rates_high
[i
]];
293 rate
= &ah
->sbands
[band
].bitrates
[0];
296 rate
= &ah
->sbands
[band
].bitrates
[4];
298 /* Set ACK timeout */
299 reg
= AR5K_RATE_DUR(rate
->hw_value
);
301 /* An ACK frame consists of 10 bytes. If you add the FCS,
302 * which ieee80211_generic_frame_duration() adds,
303 * its 14 bytes. Note we use the control rate and not the
304 * actual rate for this rate. See mac80211 tx.c
305 * ieee80211_duration() for a brief description of
306 * what rate we should choose to TX ACKs. */
307 tx_time
= ath5k_hw_get_frame_duration(ah
, band
, 10,
310 ath5k_hw_reg_write(ah
, tx_time
, reg
);
312 if (!(rate
->flags
& IEEE80211_RATE_SHORT_PREAMBLE
))
315 tx_time
= ath5k_hw_get_frame_duration(ah
, band
, 10, rate
, true);
316 ath5k_hw_reg_write(ah
, tx_time
,
317 reg
+ (AR5K_SET_SHORT_PREAMBLE
<< 2));
322 * ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU
323 * @ah: The &struct ath5k_hw
324 * @timeout: Timeout in usec
327 ath5k_hw_set_ack_timeout(struct ath5k_hw
*ah
, unsigned int timeout
)
329 if (ath5k_hw_clocktoh(ah
, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK
))
333 AR5K_REG_WRITE_BITS(ah
, AR5K_TIME_OUT
, AR5K_TIME_OUT_ACK
,
334 ath5k_hw_htoclock(ah
, timeout
));
340 * ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU
341 * @ah: The &struct ath5k_hw
342 * @timeout: Timeout in usec
345 ath5k_hw_set_cts_timeout(struct ath5k_hw
*ah
, unsigned int timeout
)
347 if (ath5k_hw_clocktoh(ah
, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS
))
351 AR5K_REG_WRITE_BITS(ah
, AR5K_TIME_OUT
, AR5K_TIME_OUT_CTS
,
352 ath5k_hw_htoclock(ah
, timeout
));
358 /*******************\
359 * RX filter Control *
360 \*******************/
363 * ath5k_hw_set_lladdr() - Set station id
364 * @ah: The &struct ath5k_hw
365 * @mac: The card's mac address (array of octets)
367 * Set station id on hw using the provided mac address
370 ath5k_hw_set_lladdr(struct ath5k_hw
*ah
, const u8
*mac
)
372 struct ath_common
*common
= ath5k_hw_common(ah
);
376 /* Set new station ID */
377 memcpy(common
->macaddr
, mac
, ETH_ALEN
);
379 pcu_reg
= ath5k_hw_reg_read(ah
, AR5K_STA_ID1
) & 0xffff0000;
381 low_id
= get_unaligned_le32(mac
);
382 high_id
= get_unaligned_le16(mac
+ 4);
384 ath5k_hw_reg_write(ah
, low_id
, AR5K_STA_ID0
);
385 ath5k_hw_reg_write(ah
, pcu_reg
| high_id
, AR5K_STA_ID1
);
391 * ath5k_hw_set_bssid() - Set current BSSID on hw
392 * @ah: The &struct ath5k_hw
394 * Sets the current BSSID and BSSID mask we have from the
395 * common struct into the hardware
398 ath5k_hw_set_bssid(struct ath5k_hw
*ah
)
400 struct ath_common
*common
= ath5k_hw_common(ah
);
404 * Set BSSID mask on 5212
406 if (ah
->ah_version
== AR5K_AR5212
)
407 ath_hw_setbssidmask(common
);
412 ath5k_hw_reg_write(ah
,
413 get_unaligned_le32(common
->curbssid
),
415 ath5k_hw_reg_write(ah
,
416 get_unaligned_le16(common
->curbssid
+ 4) |
417 ((common
->curaid
& 0x3fff) << AR5K_BSS_ID1_AID_S
),
420 if (common
->curaid
== 0) {
421 ath5k_hw_disable_pspoll(ah
);
425 AR5K_REG_WRITE_BITS(ah
, AR5K_BEACON
, AR5K_BEACON_TIM
,
426 tim_offset
? tim_offset
+ 4 : 0);
428 ath5k_hw_enable_pspoll(ah
, NULL
, 0);
432 * ath5k_hw_set_bssid_mask() - Filter out bssids we listen
433 * @ah: The &struct ath5k_hw
434 * @mask: The BSSID mask to set (array of octets)
436 * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
437 * which bits of the interface's MAC address should be looked at when trying
438 * to decide which packets to ACK. In station mode and AP mode with a single
439 * BSS every bit matters since we lock to only one BSS. In AP mode with
440 * multiple BSSes (virtual interfaces) not every bit matters because hw must
441 * accept frames for all BSSes and so we tweak some bits of our mac address
442 * in order to have multiple BSSes.
444 * For more information check out ../hw.c of the common ath module.
447 ath5k_hw_set_bssid_mask(struct ath5k_hw
*ah
, const u8
*mask
)
449 struct ath_common
*common
= ath5k_hw_common(ah
);
451 /* Cache bssid mask so that we can restore it
453 memcpy(common
->bssidmask
, mask
, ETH_ALEN
);
454 if (ah
->ah_version
== AR5K_AR5212
)
455 ath_hw_setbssidmask(common
);
459 * ath5k_hw_set_mcast_filter() - Set multicast filter
460 * @ah: The &struct ath5k_hw
461 * @filter0: Lower 32bits of muticast filter
462 * @filter1: Higher 16bits of multicast filter
465 ath5k_hw_set_mcast_filter(struct ath5k_hw
*ah
, u32 filter0
, u32 filter1
)
467 ath5k_hw_reg_write(ah
, filter0
, AR5K_MCAST_FILTER0
);
468 ath5k_hw_reg_write(ah
, filter1
, AR5K_MCAST_FILTER1
);
472 * ath5k_hw_get_rx_filter() - Get current rx filter
473 * @ah: The &struct ath5k_hw
475 * Returns the RX filter by reading rx filter and
476 * phy error filter registers. RX filter is used
477 * to set the allowed frame types that PCU will accept
478 * and pass to the driver. For a list of frame types
482 ath5k_hw_get_rx_filter(struct ath5k_hw
*ah
)
484 u32 data
, filter
= 0;
486 filter
= ath5k_hw_reg_read(ah
, AR5K_RX_FILTER
);
488 /*Radar detection for 5212*/
489 if (ah
->ah_version
== AR5K_AR5212
) {
490 data
= ath5k_hw_reg_read(ah
, AR5K_PHY_ERR_FIL
);
492 if (data
& AR5K_PHY_ERR_FIL_RADAR
)
493 filter
|= AR5K_RX_FILTER_RADARERR
;
494 if (data
& (AR5K_PHY_ERR_FIL_OFDM
| AR5K_PHY_ERR_FIL_CCK
))
495 filter
|= AR5K_RX_FILTER_PHYERR
;
502 * ath5k_hw_set_rx_filter() - Set rx filter
503 * @ah: The &struct ath5k_hw
504 * @filter: RX filter mask (see reg.h)
506 * Sets RX filter register and also handles PHY error filter
507 * register on 5212 and newer chips so that we have proper PHY
511 ath5k_hw_set_rx_filter(struct ath5k_hw
*ah
, u32 filter
)
515 /* Set PHY error filter register on 5212*/
516 if (ah
->ah_version
== AR5K_AR5212
) {
517 if (filter
& AR5K_RX_FILTER_RADARERR
)
518 data
|= AR5K_PHY_ERR_FIL_RADAR
;
519 if (filter
& AR5K_RX_FILTER_PHYERR
)
520 data
|= AR5K_PHY_ERR_FIL_OFDM
| AR5K_PHY_ERR_FIL_CCK
;
524 * The AR5210 uses promiscuous mode to detect radar activity
526 if (ah
->ah_version
== AR5K_AR5210
&&
527 (filter
& AR5K_RX_FILTER_RADARERR
)) {
528 filter
&= ~AR5K_RX_FILTER_RADARERR
;
529 filter
|= AR5K_RX_FILTER_PROM
;
532 /*Zero length DMA (phy error reporting) */
534 AR5K_REG_ENABLE_BITS(ah
, AR5K_RXCFG
, AR5K_RXCFG_ZLFDMA
);
536 AR5K_REG_DISABLE_BITS(ah
, AR5K_RXCFG
, AR5K_RXCFG_ZLFDMA
);
538 /*Write RX Filter register*/
539 ath5k_hw_reg_write(ah
, filter
& 0xff, AR5K_RX_FILTER
);
541 /*Write PHY error filter register on 5212*/
542 if (ah
->ah_version
== AR5K_AR5212
)
543 ath5k_hw_reg_write(ah
, data
, AR5K_PHY_ERR_FIL
);
552 #define ATH5K_MAX_TSF_READ 10
555 * ath5k_hw_get_tsf64() - Get the full 64bit TSF
556 * @ah: The &struct ath5k_hw
558 * Returns the current TSF
561 ath5k_hw_get_tsf64(struct ath5k_hw
*ah
)
563 u32 tsf_lower
, tsf_upper1
, tsf_upper2
;
567 /* This code is time critical - we don't want to be interrupted here */
568 local_irq_save(flags
);
571 * While reading TSF upper and then lower part, the clock is still
572 * counting (or jumping in case of IBSS merge) so we might get
573 * inconsistent values. To avoid this, we read the upper part again
574 * and check it has not been changed. We make the hypothesis that a
575 * maximum of 3 changes can happens in a row (we use 10 as a safe
578 * Impact on performance is pretty small, since in most cases, only
579 * 3 register reads are needed.
582 tsf_upper1
= ath5k_hw_reg_read(ah
, AR5K_TSF_U32
);
583 for (i
= 0; i
< ATH5K_MAX_TSF_READ
; i
++) {
584 tsf_lower
= ath5k_hw_reg_read(ah
, AR5K_TSF_L32
);
585 tsf_upper2
= ath5k_hw_reg_read(ah
, AR5K_TSF_U32
);
586 if (tsf_upper2
== tsf_upper1
)
588 tsf_upper1
= tsf_upper2
;
591 local_irq_restore(flags
);
593 WARN_ON(i
== ATH5K_MAX_TSF_READ
);
595 return ((u64
)tsf_upper1
<< 32) | tsf_lower
;
598 #undef ATH5K_MAX_TSF_READ
601 * ath5k_hw_set_tsf64() - Set a new 64bit TSF
602 * @ah: The &struct ath5k_hw
603 * @tsf64: The new 64bit TSF
608 ath5k_hw_set_tsf64(struct ath5k_hw
*ah
, u64 tsf64
)
610 ath5k_hw_reg_write(ah
, tsf64
& 0xffffffff, AR5K_TSF_L32
);
611 ath5k_hw_reg_write(ah
, (tsf64
>> 32) & 0xffffffff, AR5K_TSF_U32
);
615 * ath5k_hw_reset_tsf() - Force a TSF reset
616 * @ah: The &struct ath5k_hw
618 * Forces a TSF reset on PCU
621 ath5k_hw_reset_tsf(struct ath5k_hw
*ah
)
625 val
= ath5k_hw_reg_read(ah
, AR5K_BEACON
) | AR5K_BEACON_RESET_TSF
;
628 * Each write to the RESET_TSF bit toggles a hardware internal
629 * signal to reset TSF, but if left high it will cause a TSF reset
630 * on the next chip reset as well. Thus we always write the value
631 * twice to clear the signal.
633 ath5k_hw_reg_write(ah
, val
, AR5K_BEACON
);
634 ath5k_hw_reg_write(ah
, val
, AR5K_BEACON
);
638 * ath5k_hw_init_beacon_timers() - Initialize beacon timers
639 * @ah: The &struct ath5k_hw
640 * @next_beacon: Next TBTT
641 * @interval: Current beacon interval
643 * This function is used to initialize beacon timers based on current
644 * operation mode and settings.
647 ath5k_hw_init_beacon_timers(struct ath5k_hw
*ah
, u32 next_beacon
, u32 interval
)
649 u32 timer1
, timer2
, timer3
;
652 * Set the additional timers by mode
654 switch (ah
->opmode
) {
655 case NL80211_IFTYPE_MONITOR
:
656 case NL80211_IFTYPE_STATION
:
657 /* In STA mode timer1 is used as next wakeup
658 * timer and timer2 as next CFP duration start
659 * timer. Both in 1/8TUs. */
660 /* TODO: PCF handling */
661 if (ah
->ah_version
== AR5K_AR5210
) {
668 /* Mark associated AP as PCF incapable for now */
669 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
, AR5K_STA_ID1_PCF
);
671 case NL80211_IFTYPE_ADHOC
:
672 AR5K_REG_ENABLE_BITS(ah
, AR5K_TXCFG
, AR5K_TXCFG_ADHOC_BCN_ATIM
);
675 /* On non-STA modes timer1 is used as next DMA
676 * beacon alert (DBA) timer and timer2 as next
677 * software beacon alert. Both in 1/8TUs. */
678 timer1
= (next_beacon
- AR5K_TUNE_DMA_BEACON_RESP
) << 3;
679 timer2
= (next_beacon
- AR5K_TUNE_SW_BEACON_RESP
) << 3;
683 /* Timer3 marks the end of our ATIM window
684 * a zero length window is not allowed because
685 * we 'll get no beacons */
686 timer3
= next_beacon
+ 1;
689 * Set the beacon register and enable all timers.
691 /* When in AP or Mesh Point mode zero timer0 to start TSF */
692 if (ah
->opmode
== NL80211_IFTYPE_AP
||
693 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
)
694 ath5k_hw_reg_write(ah
, 0, AR5K_TIMER0
);
696 ath5k_hw_reg_write(ah
, next_beacon
, AR5K_TIMER0
);
697 ath5k_hw_reg_write(ah
, timer1
, AR5K_TIMER1
);
698 ath5k_hw_reg_write(ah
, timer2
, AR5K_TIMER2
);
699 ath5k_hw_reg_write(ah
, timer3
, AR5K_TIMER3
);
701 /* Force a TSF reset if requested and enable beacons */
702 if (interval
& AR5K_BEACON_RESET_TSF
)
703 ath5k_hw_reset_tsf(ah
);
705 ath5k_hw_reg_write(ah
, interval
& (AR5K_BEACON_PERIOD
|
709 /* Flush any pending BMISS interrupts on ISR by
710 * performing a clear-on-write operation on PISR
711 * register for the BMISS bit (writing a bit on
712 * ISR toggles a reset for that bit and leaves
713 * the remaining bits intact) */
714 if (ah
->ah_version
== AR5K_AR5210
)
715 ath5k_hw_reg_write(ah
, AR5K_ISR_BMISS
, AR5K_ISR
);
717 ath5k_hw_reg_write(ah
, AR5K_ISR_BMISS
, AR5K_PISR
);
719 /* TODO: Set enhanced sleep registers on AR5212
720 * based on vif->bss_conf params, until then
721 * disable power save reporting.*/
722 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
, AR5K_STA_ID1_PWR_SV
);
727 * ath5k_check_timer_win() - Check if timer B is timer A + window
728 * @a: timer a (before b)
729 * @b: timer b (after a)
730 * @window: difference between a and b
731 * @intval: timers are increased by this interval
733 * This helper function checks if timer B is timer A + window and covers
734 * cases where timer A or B might have already been updated or wrapped
735 * around (Timers are 16 bit).
737 * Returns true if O.K.
740 ath5k_check_timer_win(int a
, int b
, int window
, int intval
)
743 * 1.) usually B should be A + window
744 * 2.) A already updated, B not updated yet
745 * 3.) A already updated and has wrapped around
746 * 4.) B has wrapped around
748 if ((b
- a
== window
) || /* 1.) */
749 (a
- b
== intval
- window
) || /* 2.) */
750 ((a
| 0x10000) - b
== intval
- window
) || /* 3.) */
751 ((b
| 0x10000) - a
== window
)) /* 4.) */
752 return true; /* O.K. */
757 * ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct
758 * @ah: The &struct ath5k_hw
759 * @intval: beacon interval
761 * This is a workaround for IBSS mode
763 * The need for this function arises from the fact that we have 4 separate
764 * HW timer registers (TIMER0 - TIMER3), which are closely related to the
765 * next beacon target time (NBTT), and that the HW updates these timers
766 * separately based on the current TSF value. The hardware increments each
767 * timer by the beacon interval, when the local TSF converted to TU is equal
768 * to the value stored in the timer.
770 * The reception of a beacon with the same BSSID can update the local HW TSF
771 * at any time - this is something we can't avoid. If the TSF jumps to a
772 * time which is later than the time stored in a timer, this timer will not
773 * be updated until the TSF in TU wraps around at 16 bit (the size of the
774 * timers) and reaches the time which is stored in the timer.
776 * The problem is that these timers are closely related to TIMER0 (NBTT) and
777 * that they define a time "window". When the TSF jumps between two timers
778 * (e.g. ATIM and NBTT), the one in the past will be left behind (not
779 * updated), while the one in the future will be updated every beacon
780 * interval. This causes the window to get larger, until the TSF wraps
781 * around as described above and the timer which was left behind gets
782 * updated again. But - because the beacon interval is usually not an exact
783 * divisor of the size of the timers (16 bit), an unwanted "window" between
784 * these timers has developed!
786 * This is especially important with the ATIM window, because during
787 * the ATIM window only ATIM frames and no data frames are allowed to be
788 * sent, which creates transmission pauses after each beacon. This symptom
789 * has been described as "ramping ping" because ping times increase linearly
790 * for some time and then drop down again. A wrong window on the DMA beacon
791 * timer has the same effect, so we check for these two conditions.
793 * Returns true if O.K.
796 ath5k_hw_check_beacon_timers(struct ath5k_hw
*ah
, int intval
)
798 unsigned int nbtt
, atim
, dma
;
800 nbtt
= ath5k_hw_reg_read(ah
, AR5K_TIMER0
);
801 atim
= ath5k_hw_reg_read(ah
, AR5K_TIMER3
);
802 dma
= ath5k_hw_reg_read(ah
, AR5K_TIMER1
) >> 3;
804 /* NOTE: SWBA is different. Having a wrong window there does not
805 * stop us from sending data and this condition is caught by
806 * other means (SWBA interrupt) */
808 if (ath5k_check_timer_win(nbtt
, atim
, 1, intval
) &&
809 ath5k_check_timer_win(dma
, nbtt
, AR5K_TUNE_DMA_BEACON_RESP
,
811 return true; /* O.K. */
816 * ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class
817 * @ah: The &struct ath5k_hw
818 * @coverage_class: IEEE 802.11 coverage class number
820 * Sets IFS intervals and ACK/CTS timeouts for given coverage class.
823 ath5k_hw_set_coverage_class(struct ath5k_hw
*ah
, u8 coverage_class
)
825 /* As defined by IEEE 802.11-2007 17.3.8.6 */
826 int slot_time
= ath5k_hw_get_default_slottime(ah
) + 3 * coverage_class
;
827 int ack_timeout
= ath5k_hw_get_default_sifs(ah
) + slot_time
;
828 int cts_timeout
= ack_timeout
;
830 ath5k_hw_set_ifs_intervals(ah
, slot_time
);
831 ath5k_hw_set_ack_timeout(ah
, ack_timeout
);
832 ath5k_hw_set_cts_timeout(ah
, cts_timeout
);
834 ah
->ah_coverage_class
= coverage_class
;
837 /***************************\
838 * Init/Start/Stop functions *
839 \***************************/
842 * ath5k_hw_start_rx_pcu() - Start RX engine
843 * @ah: The &struct ath5k_hw
845 * Starts RX engine on PCU so that hw can process RXed frames
848 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
851 ath5k_hw_start_rx_pcu(struct ath5k_hw
*ah
)
853 AR5K_REG_DISABLE_BITS(ah
, AR5K_DIAG_SW
, AR5K_DIAG_SW_DIS_RX
);
857 * at5k_hw_stop_rx_pcu() - Stop RX engine
858 * @ah: The &struct ath5k_hw
860 * Stops RX engine on PCU
863 ath5k_hw_stop_rx_pcu(struct ath5k_hw
*ah
)
865 AR5K_REG_ENABLE_BITS(ah
, AR5K_DIAG_SW
, AR5K_DIAG_SW_DIS_RX
);
869 * ath5k_hw_set_opmode() - Set PCU operating mode
870 * @ah: The &struct ath5k_hw
871 * @op_mode: One of enum nl80211_iftype
873 * Configure PCU for the various operating modes (AP/STA etc)
876 ath5k_hw_set_opmode(struct ath5k_hw
*ah
, enum nl80211_iftype op_mode
)
878 struct ath_common
*common
= ath5k_hw_common(ah
);
879 u32 pcu_reg
, beacon_reg
, low_id
, high_id
;
881 ATH5K_DBG(ah
, ATH5K_DEBUG_MODE
, "mode %d\n", op_mode
);
883 /* Preserve rest settings */
884 pcu_reg
= ath5k_hw_reg_read(ah
, AR5K_STA_ID1
) & 0xffff0000;
885 pcu_reg
&= ~(AR5K_STA_ID1_ADHOC
| AR5K_STA_ID1_AP
886 | AR5K_STA_ID1_KEYSRCH_MODE
887 | (ah
->ah_version
== AR5K_AR5210
?
888 (AR5K_STA_ID1_PWR_SV
| AR5K_STA_ID1_NO_PSPOLL
) : 0));
893 case NL80211_IFTYPE_ADHOC
:
894 pcu_reg
|= AR5K_STA_ID1_ADHOC
| AR5K_STA_ID1_KEYSRCH_MODE
;
895 beacon_reg
|= AR5K_BCR_ADHOC
;
896 if (ah
->ah_version
== AR5K_AR5210
)
897 pcu_reg
|= AR5K_STA_ID1_NO_PSPOLL
;
899 AR5K_REG_ENABLE_BITS(ah
, AR5K_CFG
, AR5K_CFG_IBSS
);
902 case NL80211_IFTYPE_AP
:
903 case NL80211_IFTYPE_MESH_POINT
:
904 pcu_reg
|= AR5K_STA_ID1_AP
| AR5K_STA_ID1_KEYSRCH_MODE
;
905 beacon_reg
|= AR5K_BCR_AP
;
906 if (ah
->ah_version
== AR5K_AR5210
)
907 pcu_reg
|= AR5K_STA_ID1_NO_PSPOLL
;
909 AR5K_REG_DISABLE_BITS(ah
, AR5K_CFG
, AR5K_CFG_IBSS
);
912 case NL80211_IFTYPE_STATION
:
913 pcu_reg
|= AR5K_STA_ID1_KEYSRCH_MODE
914 | (ah
->ah_version
== AR5K_AR5210
?
915 AR5K_STA_ID1_PWR_SV
: 0);
917 case NL80211_IFTYPE_MONITOR
:
918 pcu_reg
|= AR5K_STA_ID1_KEYSRCH_MODE
919 | (ah
->ah_version
== AR5K_AR5210
?
920 AR5K_STA_ID1_NO_PSPOLL
: 0);
930 low_id
= get_unaligned_le32(common
->macaddr
);
931 high_id
= get_unaligned_le16(common
->macaddr
+ 4);
932 ath5k_hw_reg_write(ah
, low_id
, AR5K_STA_ID0
);
933 ath5k_hw_reg_write(ah
, pcu_reg
| high_id
, AR5K_STA_ID1
);
936 * Set Beacon Control Register on 5210
938 if (ah
->ah_version
== AR5K_AR5210
)
939 ath5k_hw_reg_write(ah
, beacon_reg
, AR5K_BCR
);
945 * ath5k_hw_pcu_init() - Initialize PCU
946 * @ah: The &struct ath5k_hw
947 * @op_mode: One of enum nl80211_iftype
948 * @mode: One of enum ath5k_driver_mode
950 * This function is used to initialize PCU by setting current
951 * operation mode and various other settings.
954 ath5k_hw_pcu_init(struct ath5k_hw
*ah
, enum nl80211_iftype op_mode
)
956 /* Set bssid and bssid mask */
957 ath5k_hw_set_bssid(ah
);
960 ath5k_hw_set_opmode(ah
, op_mode
);
962 /* Write rate duration table only on AR5212 and if
963 * virtual interface has already been brought up
964 * XXX: rethink this after new mode changes to
965 * mac80211 are integrated */
966 if (ah
->ah_version
== AR5K_AR5212
&&
968 ath5k_hw_write_rate_duration(ah
);
970 /* Set RSSI/BRSSI thresholds
972 * Note: If we decide to set this value
973 * dynamically, have in mind that when AR5K_RSSI_THR
974 * register is read it might return 0x40 if we haven't
975 * wrote anything to it plus BMISS RSSI threshold is zeroed.
976 * So doing a save/restore procedure here isn't the right
977 * choice. Instead store it on ath5k_hw */
978 ath5k_hw_reg_write(ah
, (AR5K_TUNE_RSSI_THRES
|
979 AR5K_TUNE_BMISS_THRES
<<
980 AR5K_RSSI_THR_BMISS_S
),
983 /* MIC QoS support */
984 if (ah
->ah_mac_srev
>= AR5K_SREV_AR2413
) {
985 ath5k_hw_reg_write(ah
, 0x000100aa, AR5K_MIC_QOS_CTL
);
986 ath5k_hw_reg_write(ah
, 0x00003210, AR5K_MIC_QOS_SEL
);
989 /* QoS NOACK Policy */
990 if (ah
->ah_version
== AR5K_AR5212
) {
991 ath5k_hw_reg_write(ah
,
992 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES
) |
993 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET
) |
994 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET
),
998 /* Restore slot time and ACK timeouts */
999 if (ah
->ah_coverage_class
> 0)
1000 ath5k_hw_set_coverage_class(ah
, ah
->ah_coverage_class
);
1002 /* Set ACK bitrate mode (see ack_rates_high) */
1003 if (ah
->ah_version
== AR5K_AR5212
) {
1004 u32 val
= AR5K_STA_ID1_BASE_RATE_11B
| AR5K_STA_ID1_ACKCTS_6MB
;
1005 if (ah
->ah_ack_bitrate_high
)
1006 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
, val
);
1008 AR5K_REG_ENABLE_BITS(ah
, AR5K_STA_ID1
, val
);