gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / reg_wow.h
blob453054078cc4785c770ea29a16c92cc5881d38bc
1 /*
2 * Copyright (c) 2015 Qualcomm Atheros Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef REG_WOW_H
18 #define REG_WOW_H
20 #define AR_WOW_PATTERN 0x825C
21 #define AR_WOW_COUNT 0x8260
22 #define AR_WOW_BCN_EN 0x8270
23 #define AR_WOW_BCN_TIMO 0x8274
24 #define AR_WOW_KEEP_ALIVE_TIMO 0x8278
25 #define AR_WOW_KEEP_ALIVE 0x827c
26 #define AR_WOW_KEEP_ALIVE_DELAY 0x8288
27 #define AR_WOW_PATTERN_MATCH 0x828c
30 * AR_WOW_LENGTH1
31 * bit 31:24 pattern 0 length
32 * bit 23:16 pattern 1 length
33 * bit 15:8 pattern 2 length
34 * bit 7:0 pattern 3 length
36 * AR_WOW_LENGTH2
37 * bit 31:24 pattern 4 length
38 * bit 23:16 pattern 5 length
39 * bit 15:8 pattern 6 length
40 * bit 7:0 pattern 7 length
42 * AR_WOW_LENGTH3
43 * bit 31:24 pattern 8 length
44 * bit 23:16 pattern 9 length
45 * bit 15:8 pattern 10 length
46 * bit 7:0 pattern 11 length
48 * AR_WOW_LENGTH4
49 * bit 31:24 pattern 12 length
50 * bit 23:16 pattern 13 length
51 * bit 15:8 pattern 14 length
52 * bit 7:0 pattern 15 length
54 #define AR_WOW_LENGTH1 0x8360
55 #define AR_WOW_LENGTH2 0X8364
56 #define AR_WOW_LENGTH3 0X8380
57 #define AR_WOW_LENGTH4 0X8384
59 #define AR_WOW_PATTERN_MATCH_LT_256B 0x8368
60 #define AR_MAC_PCU_WOW4 0x8370
62 #define AR_SW_WOW_CONTROL 0x20018
63 #define AR_SW_WOW_ENABLE 0x1
64 #define AR_SWITCH_TO_REFCLK 0x2
65 #define AR_RESET_CONTROL 0x4
66 #define AR_RESET_VALUE_MASK 0x8
67 #define AR_HW_WOW_DISABLE 0x10
68 #define AR_CLR_MAC_INTERRUPT 0x20
69 #define AR_CLR_KA_INTERRUPT 0x40
71 #define AR_WOW_BACK_OFF_SHIFT(x) ((x & 0xf) << 27) /* in usecs */
72 #define AR_WOW_MAC_INTR_EN 0x00040000
73 #define AR_WOW_MAGIC_EN 0x00010000
74 #define AR_WOW_PATTERN_EN(x) (x & 0xff)
75 #define AR_WOW_PAT_FOUND_SHIFT 8
76 #define AR_WOW_PATTERN_FOUND(x) (x & (0xff << AR_WOW_PAT_FOUND_SHIFT))
77 #define AR_WOW_PATTERN_FOUND_MASK ((0xff) << AR_WOW_PAT_FOUND_SHIFT)
78 #define AR_WOW_MAGIC_PAT_FOUND 0x00020000
79 #define AR_WOW_MAC_INTR 0x00080000
80 #define AR_WOW_KEEP_ALIVE_FAIL 0x00100000
81 #define AR_WOW_BEACON_FAIL 0x00200000
83 #define AR_WOW_STATUS(x) (x & (AR_WOW_PATTERN_FOUND_MASK | \
84 AR_WOW_MAGIC_PAT_FOUND | \
85 AR_WOW_KEEP_ALIVE_FAIL | \
86 AR_WOW_BEACON_FAIL))
87 #define AR_WOW_CLEAR_EVENTS(x) (x & ~(AR_WOW_PATTERN_EN(0xff) | \
88 AR_WOW_MAGIC_EN | \
89 AR_WOW_MAC_INTR_EN | \
90 AR_WOW_BEACON_FAIL | \
91 AR_WOW_KEEP_ALIVE_FAIL))
93 #define AR_WOW2_PATTERN_EN(x) ((x & 0xff) << 0)
94 #define AR_WOW2_PATTERN_FOUND_SHIFT 8
95 #define AR_WOW2_PATTERN_FOUND(x) (x & (0xff << AR_WOW2_PATTERN_FOUND_SHIFT))
96 #define AR_WOW2_PATTERN_FOUND_MASK ((0xff) << AR_WOW2_PATTERN_FOUND_SHIFT)
98 #define AR_WOW_STATUS2(x) (x & AR_WOW2_PATTERN_FOUND_MASK)
99 #define AR_WOW_CLEAR_EVENTS2(x) (x & ~(AR_WOW2_PATTERN_EN(0xff)))
101 #define AR_WOW_AIFS_CNT(x) (x & 0xff)
102 #define AR_WOW_SLOT_CNT(x) ((x & 0xff) << 8)
103 #define AR_WOW_KEEP_ALIVE_CNT(x) ((x & 0xff) << 16)
105 #define AR_WOW_BEACON_FAIL_EN 0x00000001
106 #define AR_WOW_BEACON_TIMO 0x40000000
107 #define AR_WOW_KEEP_ALIVE_NEVER 0xffffffff
108 #define AR_WOW_KEEP_ALIVE_AUTO_DIS 0x00000001
109 #define AR_WOW_KEEP_ALIVE_FAIL_DIS 0x00000002
110 #define AR_WOW_KEEP_ALIVE_DELAY_VALUE 0x000003e8 /* 1 msec */
111 #define AR_WOW_BMISSTHRESHOLD 0x20
112 #define AR_WOW_PAT_END_OF_PKT(x) (x & 0xf)
113 #define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8)
114 #define AR_WOW_PAT_BACKOFF 0x00000004
115 #define AR_WOW_CNT_AIFS_CNT 0x00000022
116 #define AR_WOW_CNT_SLOT_CNT 0x00000009
117 #define AR_WOW_CNT_KA_CNT 0x00000008
119 #define AR_WOW_TRANSMIT_BUFFER 0xe000
120 #define AR_WOW_TXBUF(i) (AR_WOW_TRANSMIT_BUFFER + ((i) << 2))
121 #define AR_WOW_KA_DESC_WORD2 0xe000
122 #define AR_WOW_TB_PATTERN(i) (0xe100 + (i << 8))
123 #define AR_WOW_TB_MASK(i) (0xec00 + (i << 5))
124 #define AR_WOW_PATTERN_SUPPORTED_LEGACY 0xff
125 #define AR_WOW_PATTERN_SUPPORTED 0xffff
126 #define AR_WOW_LENGTH_MAX 0xff
127 #define AR_WOW_LEN1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3)
128 #define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN1_SHIFT(_i))
129 #define AR_WOW_LEN2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3)
130 #define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN2_SHIFT(_i))
131 #define AR_WOW_LEN3_SHIFT(_i) ((0xb - ((_i) & 0xb)) << 0x3)
132 #define AR_WOW_LENGTH3_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN3_SHIFT(_i))
133 #define AR_WOW_LEN4_SHIFT(_i) ((0xf - ((_i) & 0xf)) << 0x3)
134 #define AR_WOW_LENGTH4_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN4_SHIFT(_i))
136 #endif /* REG_WOW_H */