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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / xmit.c
blobe60d4737fc6e4e42bc49c9486b6ea90263d43838
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37
38 static u16 bits_per_symbol[][2] = {
39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 };
49
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq,
54 struct ieee80211_sta *sta);
55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
56 struct ath_txq *txq, struct list_head *bf_q,
57 struct ieee80211_sta *sta,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
63 int txok);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 struct ath_buf *bf);
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_txq *txq,
68 struct ath_atx_tid *tid,
69 struct sk_buff *skb);
70 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
71 struct ath_tx_control *txctl);
72
73 enum {
74 MCS_HT20,
75 MCS_HT20_SGI,
76 MCS_HT40,
77 MCS_HT40_SGI,
78 };
79
80 /*********************/
81 /* Aggregation logic */
82 /*********************/
83
84 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
85 {
86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
87 struct ieee80211_sta *sta = info->status.status_driver_data[0];
88
89 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
90 IEEE80211_TX_STATUS_EOSP)) {
91 ieee80211_tx_status(hw, skb);
92 return;
93 }
94
95 if (sta)
96 ieee80211_tx_status_noskb(hw, sta, info);
97
98 dev_kfree_skb(skb);
99 }
100
101 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
102 __releases(&txq->axq_lock)
103 {
104 struct ieee80211_hw *hw = sc->hw;
105 struct sk_buff_head q;
106 struct sk_buff *skb;
107
108 __skb_queue_head_init(&q);
109 skb_queue_splice_init(&txq->complete_q, &q);
110 spin_unlock_bh(&txq->axq_lock);
111
112 while ((skb = __skb_dequeue(&q)))
113 ath_tx_status(hw, skb);
114 }
115
116 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
117 {
118 struct ieee80211_txq *queue =
119 container_of((void *)tid, struct ieee80211_txq, drv_priv);
120
121 ieee80211_schedule_txq(sc->hw, queue);
122 }
123
124 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
125 {
126 struct ath_softc *sc = hw->priv;
127 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
128 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
129 struct ath_txq *txq = tid->txq;
130
131 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
132 queue->sta ? queue->sta->addr : queue->vif->addr,
133 tid->tidno);
134
135 ath_txq_lock(sc, txq);
136 ath_txq_schedule(sc, txq);
137 ath_txq_unlock(sc, txq);
138 }
139
140 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
141 {
142 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
143 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
144 sizeof(tx_info->rate_driver_data));
145 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
146 }
147
148 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
149 {
150 if (!tid->an->sta)
151 return;
152
153 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
154 seqno << IEEE80211_SEQ_SEQ_SHIFT);
155 }
156
157 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
158 struct ath_buf *bf)
159 {
160 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
161 ARRAY_SIZE(bf->rates));
162 }
163
164 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
165 struct sk_buff *skb)
166 {
167 struct ath_frame_info *fi = get_frame_info(skb);
168 int q = fi->txq;
169
170 if (q < 0)
171 return;
172
173 txq = sc->tx.txq_map[q];
174 if (WARN_ON(--txq->pending_frames < 0))
175 txq->pending_frames = 0;
176
177 }
178
179 static struct ath_atx_tid *
180 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
181 {
182 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
183 return ATH_AN_2_TID(an, tidno);
184 }
185
186 static int
187 ath_tid_pull(struct ath_atx_tid *tid, struct sk_buff **skbuf)
188 {
189 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
190 struct ath_softc *sc = tid->an->sc;
191 struct ieee80211_hw *hw = sc->hw;
192 struct ath_tx_control txctl = {
193 .txq = tid->txq,
194 .sta = tid->an->sta,
195 };
196 struct sk_buff *skb;
197 struct ath_frame_info *fi;
198 int q, ret;
199
200 skb = ieee80211_tx_dequeue(hw, txq);
201 if (!skb)
202 return -ENOENT;
203
204 ret = ath_tx_prepare(hw, skb, &txctl);
205 if (ret) {
206 ieee80211_free_txskb(hw, skb);
207 return ret;
208 }
209
210 q = skb_get_queue_mapping(skb);
211 if (tid->txq == sc->tx.txq_map[q]) {
212 fi = get_frame_info(skb);
213 fi->txq = q;
214 ++tid->txq->pending_frames;
215 }
216
217 *skbuf = skb;
218 return 0;
219 }
220
221 static int ath_tid_dequeue(struct ath_atx_tid *tid,
222 struct sk_buff **skb)
223 {
224 int ret = 0;
225 *skb = __skb_dequeue(&tid->retry_q);
226 if (!*skb)
227 ret = ath_tid_pull(tid, skb);
228
229 return ret;
230 }
231
232 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
233 {
234 struct ath_txq *txq = tid->txq;
235 struct sk_buff *skb;
236 struct ath_buf *bf;
237 struct list_head bf_head;
238 struct ath_tx_status ts;
239 struct ath_frame_info *fi;
240 bool sendbar = false;
241
242 INIT_LIST_HEAD(&bf_head);
243
244 memset(&ts, 0, sizeof(ts));
245
246 while ((skb = __skb_dequeue(&tid->retry_q))) {
247 fi = get_frame_info(skb);
248 bf = fi->bf;
249 if (!bf) {
250 ath_txq_skb_done(sc, txq, skb);
251 ieee80211_free_txskb(sc->hw, skb);
252 continue;
253 }
254
255 if (fi->baw_tracked) {
256 ath_tx_update_baw(sc, tid, bf);
257 sendbar = true;
258 }
259
260 list_add_tail(&bf->list, &bf_head);
261 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
262 }
263
264 if (sendbar) {
265 ath_txq_unlock(sc, txq);
266 ath_send_bar(tid, tid->seq_start);
267 ath_txq_lock(sc, txq);
268 }
269 }
270
271 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
272 struct ath_buf *bf)
273 {
274 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
275 u16 seqno = bf->bf_state.seqno;
276 int index, cindex;
277
278 if (!fi->baw_tracked)
279 return;
280
281 index = ATH_BA_INDEX(tid->seq_start, seqno);
282 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
283
284 __clear_bit(cindex, tid->tx_buf);
285
286 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
287 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
288 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
289 if (tid->bar_index >= 0)
290 tid->bar_index--;
291 }
292 }
293
294 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
295 struct ath_buf *bf)
296 {
297 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
298 u16 seqno = bf->bf_state.seqno;
299 int index, cindex;
300
301 if (fi->baw_tracked)
302 return;
303
304 index = ATH_BA_INDEX(tid->seq_start, seqno);
305 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
306 __set_bit(cindex, tid->tx_buf);
307 fi->baw_tracked = 1;
308
309 if (index >= ((tid->baw_tail - tid->baw_head) &
310 (ATH_TID_MAX_BUFS - 1))) {
311 tid->baw_tail = cindex;
312 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
313 }
314 }
315
316 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
317 struct ath_atx_tid *tid)
318
319 {
320 struct sk_buff *skb;
321 struct ath_buf *bf;
322 struct list_head bf_head;
323 struct ath_tx_status ts;
324 struct ath_frame_info *fi;
325 int ret;
326
327 memset(&ts, 0, sizeof(ts));
328 INIT_LIST_HEAD(&bf_head);
329
330 while ((ret = ath_tid_dequeue(tid, &skb)) == 0) {
331 fi = get_frame_info(skb);
332 bf = fi->bf;
333
334 if (!bf) {
335 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
336 continue;
337 }
338
339 list_add_tail(&bf->list, &bf_head);
340 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
341 }
342 }
343
344 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
345 struct sk_buff *skb, int count)
346 {
347 struct ath_frame_info *fi = get_frame_info(skb);
348 struct ath_buf *bf = fi->bf;
349 struct ieee80211_hdr *hdr;
350 int prev = fi->retries;
351
352 TX_STAT_INC(sc, txq->axq_qnum, a_retries);
353 fi->retries += count;
354
355 if (prev > 0)
356 return;
357
358 hdr = (struct ieee80211_hdr *)skb->data;
359 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
360 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
361 sizeof(*hdr), DMA_TO_DEVICE);
362 }
363
364 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
365 {
366 struct ath_buf *bf = NULL;
367
368 spin_lock_bh(&sc->tx.txbuflock);
369
370 if (unlikely(list_empty(&sc->tx.txbuf))) {
371 spin_unlock_bh(&sc->tx.txbuflock);
372 return NULL;
373 }
374
375 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
376 list_del(&bf->list);
377
378 spin_unlock_bh(&sc->tx.txbuflock);
379
380 return bf;
381 }
382
383 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
384 {
385 spin_lock_bh(&sc->tx.txbuflock);
386 list_add_tail(&bf->list, &sc->tx.txbuf);
387 spin_unlock_bh(&sc->tx.txbuflock);
388 }
389
390 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
391 {
392 struct ath_buf *tbf;
393
394 tbf = ath_tx_get_buffer(sc);
395 if (WARN_ON(!tbf))
396 return NULL;
397
398 ATH_TXBUF_RESET(tbf);
399
400 tbf->bf_mpdu = bf->bf_mpdu;
401 tbf->bf_buf_addr = bf->bf_buf_addr;
402 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
403 tbf->bf_state = bf->bf_state;
404 tbf->bf_state.stale = false;
405
406 return tbf;
407 }
408
409 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
410 struct ath_tx_status *ts, int txok,
411 int *nframes, int *nbad)
412 {
413 u16 seq_st = 0;
414 u32 ba[WME_BA_BMP_SIZE >> 5];
415 int ba_index;
416 int isaggr = 0;
417
418 *nbad = 0;
419 *nframes = 0;
420
421 isaggr = bf_isaggr(bf);
422 if (isaggr) {
423 seq_st = ts->ts_seqnum;
424 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
425 }
426
427 while (bf) {
428 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
429
430 (*nframes)++;
431 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
432 (*nbad)++;
433
434 bf = bf->bf_next;
435 }
436 }
437
438
439 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
440 struct ath_buf *bf, struct list_head *bf_q,
441 struct ieee80211_sta *sta,
442 struct ath_atx_tid *tid,
443 struct ath_tx_status *ts, int txok)
444 {
445 struct ath_node *an = NULL;
446 struct sk_buff *skb;
447 struct ieee80211_tx_info *tx_info;
448 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
449 struct list_head bf_head;
450 struct sk_buff_head bf_pending;
451 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
452 u32 ba[WME_BA_BMP_SIZE >> 5];
453 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
454 bool rc_update = true, isba;
455 struct ieee80211_tx_rate rates[4];
456 struct ath_frame_info *fi;
457 int nframes;
458 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
459 int i, retries;
460 int bar_index = -1;
461
462 skb = bf->bf_mpdu;
463 tx_info = IEEE80211_SKB_CB(skb);
464
465 memcpy(rates, bf->rates, sizeof(rates));
466
467 retries = ts->ts_longretry + 1;
468 for (i = 0; i < ts->ts_rateindex; i++)
469 retries += rates[i].count;
470
471 if (!sta) {
472 INIT_LIST_HEAD(&bf_head);
473 while (bf) {
474 bf_next = bf->bf_next;
475
476 if (!bf->bf_state.stale || bf_next != NULL)
477 list_move_tail(&bf->list, &bf_head);
478
479 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
480
481 bf = bf_next;
482 }
483 return;
484 }
485
486 an = (struct ath_node *)sta->drv_priv;
487 seq_first = tid->seq_start;
488 isba = ts->ts_flags & ATH9K_TX_BA;
489
490 /*
491 * The hardware occasionally sends a tx status for the wrong TID.
492 * In this case, the BA status cannot be considered valid and all
493 * subframes need to be retransmitted
494 *
495 * Only BlockAcks have a TID and therefore normal Acks cannot be
496 * checked
497 */
498 if (isba && tid->tidno != ts->tid)
499 txok = false;
500
501 isaggr = bf_isaggr(bf);
502 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
503
504 if (isaggr && txok) {
505 if (ts->ts_flags & ATH9K_TX_BA) {
506 seq_st = ts->ts_seqnum;
507 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
508 } else {
509 /*
510 * AR5416 can become deaf/mute when BA
511 * issue happens. Chip needs to be reset.
512 * But AP code may have sychronization issues
513 * when perform internal reset in this routine.
514 * Only enable reset in STA mode for now.
515 */
516 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
517 needreset = 1;
518 }
519 }
520
521 __skb_queue_head_init(&bf_pending);
522
523 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
524 while (bf) {
525 u16 seqno = bf->bf_state.seqno;
526
527 txfail = txpending = sendbar = 0;
528 bf_next = bf->bf_next;
529
530 skb = bf->bf_mpdu;
531 tx_info = IEEE80211_SKB_CB(skb);
532 fi = get_frame_info(skb);
533
534 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
535 !tid->active) {
536 /*
537 * Outside of the current BlockAck window,
538 * maybe part of a previous session
539 */
540 txfail = 1;
541 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
542 /* transmit completion, subframe is
543 * acked by block ack */
544 acked_cnt++;
545 } else if (!isaggr && txok) {
546 /* transmit completion */
547 acked_cnt++;
548 } else if (flush) {
549 txpending = 1;
550 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
551 if (txok || !an->sleeping)
552 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
553 retries);
554
555 txpending = 1;
556 } else {
557 txfail = 1;
558 txfail_cnt++;
559 bar_index = max_t(int, bar_index,
560 ATH_BA_INDEX(seq_first, seqno));
561 }
562
563 /*
564 * Make sure the last desc is reclaimed if it
565 * not a holding desc.
566 */
567 INIT_LIST_HEAD(&bf_head);
568 if (bf_next != NULL || !bf_last->bf_state.stale)
569 list_move_tail(&bf->list, &bf_head);
570
571 if (!txpending) {
572 /*
573 * complete the acked-ones/xretried ones; update
574 * block-ack window
575 */
576 ath_tx_update_baw(sc, tid, bf);
577
578 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
579 memcpy(tx_info->control.rates, rates, sizeof(rates));
580 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
581 rc_update = false;
582 if (bf == bf->bf_lastbf)
583 ath_dynack_sample_tx_ts(sc->sc_ah,
584 bf->bf_mpdu,
585 ts, sta);
586 }
587
588 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
589 !txfail);
590 } else {
591 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
592 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
593 ieee80211_sta_eosp(sta);
594 }
595 /* retry the un-acked ones */
596 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
597 struct ath_buf *tbf;
598
599 tbf = ath_clone_txbuf(sc, bf_last);
600 /*
601 * Update tx baw and complete the
602 * frame with failed status if we
603 * run out of tx buf.
604 */
605 if (!tbf) {
606 ath_tx_update_baw(sc, tid, bf);
607
608 ath_tx_complete_buf(sc, bf, txq,
609 &bf_head, NULL, ts,
610 0);
611 bar_index = max_t(int, bar_index,
612 ATH_BA_INDEX(seq_first, seqno));
613 break;
614 }
615
616 fi->bf = tbf;
617 }
618
619 /*
620 * Put this buffer to the temporary pending
621 * queue to retain ordering
622 */
623 __skb_queue_tail(&bf_pending, skb);
624 }
625
626 bf = bf_next;
627 }
628
629 /* prepend un-acked frames to the beginning of the pending frame queue */
630 if (!skb_queue_empty(&bf_pending)) {
631 if (an->sleeping)
632 ieee80211_sta_set_buffered(sta, tid->tidno, true);
633
634 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
635 if (!an->sleeping) {
636 ath_tx_queue_tid(sc, tid);
637 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
638 tid->clear_ps_filter = true;
639 }
640 }
641
642 if (bar_index >= 0) {
643 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
644
645 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
646 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
647
648 ath_txq_unlock(sc, txq);
649 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
650 ath_txq_lock(sc, txq);
651 }
652
653 if (needreset)
654 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
655 }
656
657 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
658 {
659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
660 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
661 }
662
663 static void ath_tx_count_airtime(struct ath_softc *sc,
664 struct ieee80211_sta *sta,
665 struct ath_buf *bf,
666 struct ath_tx_status *ts,
667 u8 tid)
668 {
669 u32 airtime = 0;
670 int i;
671
672 airtime += ts->duration * (ts->ts_longretry + 1);
673 for(i = 0; i < ts->ts_rateindex; i++) {
674 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
675 airtime += rate_dur * bf->rates[i].count;
676 }
677
678 ieee80211_sta_register_airtime(sta, tid, airtime, 0);
679 }
680
681 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
682 struct ath_tx_status *ts, struct ath_buf *bf,
683 struct list_head *bf_head)
684 {
685 struct ieee80211_hw *hw = sc->hw;
686 struct ieee80211_tx_info *info;
687 struct ieee80211_sta *sta;
688 struct ieee80211_hdr *hdr;
689 struct ath_atx_tid *tid = NULL;
690 bool txok, flush;
691
692 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
693 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
694 txq->axq_tx_inprogress = false;
695
696 txq->axq_depth--;
697 if (bf_is_ampdu_not_probing(bf))
698 txq->axq_ampdu_depth--;
699
700 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
701 ts->ts_rateindex);
702
703 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
704 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
705 if (sta) {
706 struct ath_node *an = (struct ath_node *)sta->drv_priv;
707 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
708 ath_tx_count_airtime(sc, sta, bf, ts, tid->tidno);
709 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
710 tid->clear_ps_filter = true;
711 }
712
713 if (!bf_isampdu(bf)) {
714 if (!flush) {
715 info = IEEE80211_SKB_CB(bf->bf_mpdu);
716 memcpy(info->control.rates, bf->rates,
717 sizeof(info->control.rates));
718 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
719 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
720 sta);
721 }
722 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
723 } else
724 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
725
726 if (!flush)
727 ath_txq_schedule(sc, txq);
728 }
729
730 static bool ath_lookup_legacy(struct ath_buf *bf)
731 {
732 struct sk_buff *skb;
733 struct ieee80211_tx_info *tx_info;
734 struct ieee80211_tx_rate *rates;
735 int i;
736
737 skb = bf->bf_mpdu;
738 tx_info = IEEE80211_SKB_CB(skb);
739 rates = tx_info->control.rates;
740
741 for (i = 0; i < 4; i++) {
742 if (!rates[i].count || rates[i].idx < 0)
743 break;
744
745 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
746 return true;
747 }
748
749 return false;
750 }
751
752 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
753 struct ath_atx_tid *tid)
754 {
755 struct sk_buff *skb;
756 struct ieee80211_tx_info *tx_info;
757 struct ieee80211_tx_rate *rates;
758 u32 max_4ms_framelen, frmlen;
759 u16 aggr_limit, bt_aggr_limit, legacy = 0;
760 int q = tid->txq->mac80211_qnum;
761 int i;
762
763 skb = bf->bf_mpdu;
764 tx_info = IEEE80211_SKB_CB(skb);
765 rates = bf->rates;
766
767 /*
768 * Find the lowest frame length among the rate series that will have a
769 * 4ms (or TXOP limited) transmit duration.
770 */
771 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
772
773 for (i = 0; i < 4; i++) {
774 int modeidx;
775
776 if (!rates[i].count)
777 continue;
778
779 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
780 legacy = 1;
781 break;
782 }
783
784 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
785 modeidx = MCS_HT40;
786 else
787 modeidx = MCS_HT20;
788
789 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
790 modeidx++;
791
792 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
793 max_4ms_framelen = min(max_4ms_framelen, frmlen);
794 }
795
796 /*
797 * limit aggregate size by the minimum rate if rate selected is
798 * not a probe rate, if rate selected is a probe rate then
799 * avoid aggregation of this packet.
800 */
801 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
802 return 0;
803
804 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
805
806 /*
807 * Override the default aggregation limit for BTCOEX.
808 */
809 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
810 if (bt_aggr_limit)
811 aggr_limit = bt_aggr_limit;
812
813 if (tid->an->maxampdu)
814 aggr_limit = min(aggr_limit, tid->an->maxampdu);
815
816 return aggr_limit;
817 }
818
819 /*
820 * Returns the number of delimiters to be added to
821 * meet the minimum required mpdudensity.
822 */
823 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
824 struct ath_buf *bf, u16 frmlen,
825 bool first_subfrm)
826 {
827 #define FIRST_DESC_NDELIMS 60
828 u32 nsymbits, nsymbols;
829 u16 minlen;
830 u8 flags, rix;
831 int width, streams, half_gi, ndelim, mindelim;
832 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
833
834 /* Select standard number of delimiters based on frame length alone */
835 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
836
837 /*
838 * If encryption enabled, hardware requires some more padding between
839 * subframes.
840 * TODO - this could be improved to be dependent on the rate.
841 * The hardware can keep up at lower rates, but not higher rates
842 */
843 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
844 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
845 ndelim += ATH_AGGR_ENCRYPTDELIM;
846
847 /*
848 * Add delimiter when using RTS/CTS with aggregation
849 * and non enterprise AR9003 card
850 */
851 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
852 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
853 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
854
855 /*
856 * Convert desired mpdu density from microeconds to bytes based
857 * on highest rate in rate series (i.e. first rate) to determine
858 * required minimum length for subframe. Take into account
859 * whether high rate is 20 or 40Mhz and half or full GI.
860 *
861 * If there is no mpdu density restriction, no further calculation
862 * is needed.
863 */
864
865 if (tid->an->mpdudensity == 0)
866 return ndelim;
867
868 rix = bf->rates[0].idx;
869 flags = bf->rates[0].flags;
870 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
871 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
872
873 if (half_gi)
874 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
875 else
876 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
877
878 if (nsymbols == 0)
879 nsymbols = 1;
880
881 streams = HT_RC_2_STREAMS(rix);
882 nsymbits = bits_per_symbol[rix % 8][width] * streams;
883 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
884
885 if (frmlen < minlen) {
886 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
887 ndelim = max(mindelim, ndelim);
888 }
889
890 return ndelim;
891 }
892
893 static int
894 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
895 struct ath_atx_tid *tid, struct ath_buf **buf)
896 {
897 struct ieee80211_tx_info *tx_info;
898 struct ath_frame_info *fi;
899 struct ath_buf *bf;
900 struct sk_buff *skb, *first_skb = NULL;
901 u16 seqno;
902 int ret;
903
904 while (1) {
905 ret = ath_tid_dequeue(tid, &skb);
906 if (ret < 0)
907 return ret;
908
909 fi = get_frame_info(skb);
910 bf = fi->bf;
911 if (!fi->bf)
912 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
913 else
914 bf->bf_state.stale = false;
915
916 if (!bf) {
917 ath_txq_skb_done(sc, txq, skb);
918 ieee80211_free_txskb(sc->hw, skb);
919 continue;
920 }
921
922 bf->bf_next = NULL;
923 bf->bf_lastbf = bf;
924
925 tx_info = IEEE80211_SKB_CB(skb);
926 tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT |
927 IEEE80211_TX_STATUS_EOSP);
928
929 /*
930 * No aggregation session is running, but there may be frames
931 * from a previous session or a failed attempt in the queue.
932 * Send them out as normal data frames
933 */
934 if (!tid->active)
935 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
936
937 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
938 bf->bf_state.bf_type = 0;
939 break;
940 }
941
942 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
943 seqno = bf->bf_state.seqno;
944
945 /* do not step over block-ack window */
946 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
947 __skb_queue_tail(&tid->retry_q, skb);
948
949 /* If there are other skbs in the retry q, they are
950 * probably within the BAW, so loop immediately to get
951 * one of them. Otherwise the queue can get stuck. */
952 if (!skb_queue_is_first(&tid->retry_q, skb) &&
953 !WARN_ON(skb == first_skb)) {
954 if(!first_skb) /* infinite loop prevention */
955 first_skb = skb;
956 continue;
957 }
958 return -EINPROGRESS;
959 }
960
961 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
962 struct ath_tx_status ts = {};
963 struct list_head bf_head;
964
965 INIT_LIST_HEAD(&bf_head);
966 list_add(&bf->list, &bf_head);
967 ath_tx_update_baw(sc, tid, bf);
968 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
969 continue;
970 }
971
972 if (bf_isampdu(bf))
973 ath_tx_addto_baw(sc, tid, bf);
974
975 break;
976 }
977
978 *buf = bf;
979 return 0;
980 }
981
982 static int
983 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
984 struct ath_atx_tid *tid, struct list_head *bf_q,
985 struct ath_buf *bf_first)
986 {
987 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
988 struct ath_buf *bf = bf_first, *bf_prev = NULL;
989 int nframes = 0, ndelim, ret;
990 u16 aggr_limit = 0, al = 0, bpad = 0,
991 al_delta, h_baw = tid->baw_size / 2;
992 struct ieee80211_tx_info *tx_info;
993 struct ath_frame_info *fi;
994 struct sk_buff *skb;
995
996
997 bf = bf_first;
998 aggr_limit = ath_lookup_rate(sc, bf, tid);
999
1000 while (bf)
1001 {
1002 skb = bf->bf_mpdu;
1003 fi = get_frame_info(skb);
1004
1005 /* do not exceed aggregation limit */
1006 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1007 if (nframes) {
1008 if (aggr_limit < al + bpad + al_delta ||
1009 ath_lookup_legacy(bf) || nframes >= h_baw)
1010 goto stop;
1011
1012 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1013 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1014 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1015 goto stop;
1016 }
1017
1018 /* add padding for previous frame to aggregation length */
1019 al += bpad + al_delta;
1020
1021 /*
1022 * Get the delimiters needed to meet the MPDU
1023 * density for this node.
1024 */
1025 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1026 !nframes);
1027 bpad = PADBYTES(al_delta) + (ndelim << 2);
1028
1029 nframes++;
1030 bf->bf_next = NULL;
1031
1032 /* link buffers of this frame to the aggregate */
1033 bf->bf_state.ndelim = ndelim;
1034
1035 list_add_tail(&bf->list, bf_q);
1036 if (bf_prev)
1037 bf_prev->bf_next = bf;
1038
1039 bf_prev = bf;
1040
1041 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1042 if (ret < 0)
1043 break;
1044 }
1045 goto finish;
1046 stop:
1047 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1048 finish:
1049 bf = bf_first;
1050 bf->bf_lastbf = bf_prev;
1051
1052 if (bf == bf_prev) {
1053 al = get_frame_info(bf->bf_mpdu)->framelen;
1054 bf->bf_state.bf_type = BUF_AMPDU;
1055 } else {
1056 TX_STAT_INC(sc, txq->axq_qnum, a_aggr);
1057 }
1058
1059 return al;
1060 #undef PADBYTES
1061 }
1062
1063 /*
1064 * rix - rate index
1065 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1066 * width - 0 for 20 MHz, 1 for 40 MHz
1067 * half_gi - to use 4us v/s 3.6 us for symbol time
1068 */
1069 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1070 int width, int half_gi, bool shortPreamble)
1071 {
1072 u32 nbits, nsymbits, duration, nsymbols;
1073 int streams;
1074
1075 /* find number of symbols: PLCP + data */
1076 streams = HT_RC_2_STREAMS(rix);
1077 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1078 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1079 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1080
1081 if (!half_gi)
1082 duration = SYMBOL_TIME(nsymbols);
1083 else
1084 duration = SYMBOL_TIME_HALFGI(nsymbols);
1085
1086 /* addup duration for legacy/ht training and signal fields */
1087 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1088
1089 return duration;
1090 }
1091
1092 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1093 {
1094 int streams = HT_RC_2_STREAMS(mcs);
1095 int symbols, bits;
1096 int bytes = 0;
1097
1098 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1099 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1100 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1101 bits -= OFDM_PLCP_BITS;
1102 bytes = bits / 8;
1103 if (bytes > 65532)
1104 bytes = 65532;
1105
1106 return bytes;
1107 }
1108
1109 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1110 {
1111 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1112 int mcs;
1113
1114 /* 4ms is the default (and maximum) duration */
1115 if (!txop || txop > 4096)
1116 txop = 4096;
1117
1118 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1119 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1120 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1121 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1122 for (mcs = 0; mcs < 32; mcs++) {
1123 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1124 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1125 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1126 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1127 }
1128 }
1129
1130 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1131 u8 rateidx, bool is_40, bool is_cck)
1132 {
1133 u8 max_power;
1134 struct sk_buff *skb;
1135 struct ath_frame_info *fi;
1136 struct ieee80211_tx_info *info;
1137 struct ath_hw *ah = sc->sc_ah;
1138
1139 if (sc->tx99_state || !ah->tpc_enabled)
1140 return MAX_RATE_POWER;
1141
1142 skb = bf->bf_mpdu;
1143 fi = get_frame_info(skb);
1144 info = IEEE80211_SKB_CB(skb);
1145
1146 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1147 int txpower = fi->tx_power;
1148
1149 if (is_40) {
1150 u8 power_ht40delta;
1151 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1152 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1153
1154 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1155 bool is_2ghz;
1156 struct modal_eep_header *pmodal;
1157
1158 is_2ghz = info->band == NL80211_BAND_2GHZ;
1159 pmodal = &eep->modalHeader[is_2ghz];
1160 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1161 } else {
1162 power_ht40delta = 2;
1163 }
1164 txpower += power_ht40delta;
1165 }
1166
1167 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1168 AR_SREV_9271(ah)) {
1169 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1170 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1171 s8 power_offset;
1172
1173 power_offset = ah->eep_ops->get_eeprom(ah,
1174 EEP_PWR_TABLE_OFFSET);
1175 txpower -= 2 * power_offset;
1176 }
1177
1178 if (OLC_FOR_AR9280_20_LATER && is_cck)
1179 txpower -= 2;
1180
1181 txpower = max(txpower, 0);
1182 max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1183
1184 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1185 * max_power is set to 0, frames are transmitted at max
1186 * TX power
1187 */
1188 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1189 max_power = 1;
1190 } else if (!bf->bf_state.bfs_paprd) {
1191 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1192 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1193 fi->tx_power);
1194 else
1195 max_power = min_t(u8, ah->tx_power[rateidx],
1196 fi->tx_power);
1197 } else {
1198 max_power = ah->paprd_training_power;
1199 }
1200
1201 return max_power;
1202 }
1203
1204 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1205 struct ath_tx_info *info, int len, bool rts)
1206 {
1207 struct ath_hw *ah = sc->sc_ah;
1208 struct ath_common *common = ath9k_hw_common(ah);
1209 struct sk_buff *skb;
1210 struct ieee80211_tx_info *tx_info;
1211 struct ieee80211_tx_rate *rates;
1212 const struct ieee80211_rate *rate;
1213 struct ieee80211_hdr *hdr;
1214 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1215 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1216 int i;
1217 u8 rix = 0;
1218
1219 skb = bf->bf_mpdu;
1220 tx_info = IEEE80211_SKB_CB(skb);
1221 rates = bf->rates;
1222 hdr = (struct ieee80211_hdr *)skb->data;
1223
1224 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1225 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1226 info->rtscts_rate = fi->rtscts_rate;
1227
1228 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1229 bool is_40, is_sgi, is_sp, is_cck;
1230 int phy;
1231
1232 if (!rates[i].count || (rates[i].idx < 0))
1233 continue;
1234
1235 rix = rates[i].idx;
1236 info->rates[i].Tries = rates[i].count;
1237
1238 /*
1239 * Handle RTS threshold for unaggregated HT frames.
1240 */
1241 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1242 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1243 unlikely(rts_thresh != (u32) -1)) {
1244 if (!rts_thresh || (len > rts_thresh))
1245 rts = true;
1246 }
1247
1248 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1249 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1250 info->flags |= ATH9K_TXDESC_RTSENA;
1251 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1252 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1253 info->flags |= ATH9K_TXDESC_CTSENA;
1254 }
1255
1256 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1257 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1258 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1259 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1260
1261 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1262 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1263 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1264
1265 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1266 /* MCS rates */
1267 info->rates[i].Rate = rix | 0x80;
1268 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1269 ah->txchainmask, info->rates[i].Rate);
1270 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1271 is_40, is_sgi, is_sp);
1272 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1273 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1274
1275 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1276 is_40, false);
1277 continue;
1278 }
1279
1280 /* legacy rates */
1281 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1282 if ((tx_info->band == NL80211_BAND_2GHZ) &&
1283 !(rate->flags & IEEE80211_RATE_ERP_G))
1284 phy = WLAN_RC_PHY_CCK;
1285 else
1286 phy = WLAN_RC_PHY_OFDM;
1287
1288 info->rates[i].Rate = rate->hw_value;
1289 if (rate->hw_value_short) {
1290 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1291 info->rates[i].Rate |= rate->hw_value_short;
1292 } else {
1293 is_sp = false;
1294 }
1295
1296 if (bf->bf_state.bfs_paprd)
1297 info->rates[i].ChSel = ah->txchainmask;
1298 else
1299 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1300 ah->txchainmask, info->rates[i].Rate);
1301
1302 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1303 phy, rate->bitrate * 100, len, rix, is_sp);
1304
1305 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1306 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1307 is_cck);
1308 }
1309
1310 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1311 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1312 info->flags &= ~ATH9K_TXDESC_RTSENA;
1313
1314 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1315 if (info->flags & ATH9K_TXDESC_RTSENA)
1316 info->flags &= ~ATH9K_TXDESC_CTSENA;
1317 }
1318
1319 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1320 {
1321 struct ieee80211_hdr *hdr;
1322 enum ath9k_pkt_type htype;
1323 __le16 fc;
1324
1325 hdr = (struct ieee80211_hdr *)skb->data;
1326 fc = hdr->frame_control;
1327
1328 if (ieee80211_is_beacon(fc))
1329 htype = ATH9K_PKT_TYPE_BEACON;
1330 else if (ieee80211_is_probe_resp(fc))
1331 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1332 else if (ieee80211_is_atim(fc))
1333 htype = ATH9K_PKT_TYPE_ATIM;
1334 else if (ieee80211_is_pspoll(fc))
1335 htype = ATH9K_PKT_TYPE_PSPOLL;
1336 else
1337 htype = ATH9K_PKT_TYPE_NORMAL;
1338
1339 return htype;
1340 }
1341
1342 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1343 struct ath_txq *txq, int len)
1344 {
1345 struct ath_hw *ah = sc->sc_ah;
1346 struct ath_buf *bf_first = NULL;
1347 struct ath_tx_info info;
1348 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1349 bool rts = false;
1350
1351 memset(&info, 0, sizeof(info));
1352 info.is_first = true;
1353 info.is_last = true;
1354 info.qcu = txq->axq_qnum;
1355
1356 while (bf) {
1357 struct sk_buff *skb = bf->bf_mpdu;
1358 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1359 struct ath_frame_info *fi = get_frame_info(skb);
1360 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1361
1362 info.type = get_hw_packet_type(skb);
1363 if (bf->bf_next)
1364 info.link = bf->bf_next->bf_daddr;
1365 else
1366 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1367
1368 if (!bf_first) {
1369 bf_first = bf;
1370
1371 if (!sc->tx99_state)
1372 info.flags = ATH9K_TXDESC_INTREQ;
1373 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1374 txq == sc->tx.uapsdq)
1375 info.flags |= ATH9K_TXDESC_CLRDMASK;
1376
1377 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1378 info.flags |= ATH9K_TXDESC_NOACK;
1379 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1380 info.flags |= ATH9K_TXDESC_LDPC;
1381
1382 if (bf->bf_state.bfs_paprd)
1383 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1384 ATH9K_TXDESC_PAPRD_S;
1385
1386 /*
1387 * mac80211 doesn't handle RTS threshold for HT because
1388 * the decision has to be taken based on AMPDU length
1389 * and aggregation is done entirely inside ath9k.
1390 * Set the RTS/CTS flag for the first subframe based
1391 * on the threshold.
1392 */
1393 if (aggr && (bf == bf_first) &&
1394 unlikely(rts_thresh != (u32) -1)) {
1395 /*
1396 * "len" is the size of the entire AMPDU.
1397 */
1398 if (!rts_thresh || (len > rts_thresh))
1399 rts = true;
1400 }
1401
1402 if (!aggr)
1403 len = fi->framelen;
1404
1405 ath_buf_set_rate(sc, bf, &info, len, rts);
1406 }
1407
1408 info.buf_addr[0] = bf->bf_buf_addr;
1409 info.buf_len[0] = skb->len;
1410 info.pkt_len = fi->framelen;
1411 info.keyix = fi->keyix;
1412 info.keytype = fi->keytype;
1413
1414 if (aggr) {
1415 if (bf == bf_first)
1416 info.aggr = AGGR_BUF_FIRST;
1417 else if (bf == bf_first->bf_lastbf)
1418 info.aggr = AGGR_BUF_LAST;
1419 else
1420 info.aggr = AGGR_BUF_MIDDLE;
1421
1422 info.ndelim = bf->bf_state.ndelim;
1423 info.aggr_len = len;
1424 }
1425
1426 if (bf == bf_first->bf_lastbf)
1427 bf_first = NULL;
1428
1429 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1430 bf = bf->bf_next;
1431 }
1432 }
1433
1434 static void
1435 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1436 struct ath_atx_tid *tid, struct list_head *bf_q,
1437 struct ath_buf *bf_first)
1438 {
1439 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1440 int nframes = 0, ret;
1441
1442 do {
1443 struct ieee80211_tx_info *tx_info;
1444
1445 nframes++;
1446 list_add_tail(&bf->list, bf_q);
1447 if (bf_prev)
1448 bf_prev->bf_next = bf;
1449 bf_prev = bf;
1450
1451 if (nframes >= 2)
1452 break;
1453
1454 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1455 if (ret < 0)
1456 break;
1457
1458 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1459 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1460 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1461 break;
1462 }
1463
1464 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1465 } while (1);
1466 }
1467
1468 static int ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1469 struct ath_atx_tid *tid)
1470 {
1471 struct ath_buf *bf = NULL;
1472 struct ieee80211_tx_info *tx_info;
1473 struct list_head bf_q;
1474 int aggr_len = 0, ret;
1475 bool aggr;
1476
1477 INIT_LIST_HEAD(&bf_q);
1478
1479 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1480 if (ret < 0)
1481 return ret;
1482
1483 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1484 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1485 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1486 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1487 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1488 return -EBUSY;
1489 }
1490
1491 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1492 if (aggr)
1493 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1494 else
1495 ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1496
1497 if (list_empty(&bf_q))
1498 return -EAGAIN;
1499
1500 if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1501 tid->clear_ps_filter = false;
1502 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1503 }
1504
1505 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1506 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1507 return 0;
1508 }
1509
1510 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1511 u16 tid, u16 *ssn)
1512 {
1513 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1514 struct ath_atx_tid *txtid;
1515 struct ath_txq *txq;
1516 struct ath_node *an;
1517 u8 density;
1518
1519 ath_dbg(common, XMIT, "%s called\n", __func__);
1520
1521 an = (struct ath_node *)sta->drv_priv;
1522 txtid = ATH_AN_2_TID(an, tid);
1523 txq = txtid->txq;
1524
1525 ath_txq_lock(sc, txq);
1526
1527 /* update ampdu factor/density, they may have changed. This may happen
1528 * in HT IBSS when a beacon with HT-info is received after the station
1529 * has already been added.
1530 */
1531 if (sta->ht_cap.ht_supported) {
1532 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1533 sta->ht_cap.ampdu_factor)) - 1;
1534 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1535 an->mpdudensity = density;
1536 }
1537
1538 txtid->active = true;
1539 *ssn = txtid->seq_start = txtid->seq_next;
1540 txtid->bar_index = -1;
1541
1542 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1543 txtid->baw_head = txtid->baw_tail = 0;
1544
1545 ath_txq_unlock_complete(sc, txq);
1546
1547 return 0;
1548 }
1549
1550 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1551 {
1552 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1553 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1554 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1555 struct ath_txq *txq = txtid->txq;
1556
1557 ath_dbg(common, XMIT, "%s called\n", __func__);
1558
1559 ath_txq_lock(sc, txq);
1560 txtid->active = false;
1561 ath_tx_flush_tid(sc, txtid);
1562 ath_txq_unlock_complete(sc, txq);
1563 }
1564
1565 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1566 struct ath_node *an)
1567 {
1568 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1569 struct ath_atx_tid *tid;
1570 int tidno;
1571
1572 ath_dbg(common, XMIT, "%s called\n", __func__);
1573
1574 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1575 tid = ath_node_to_tid(an, tidno);
1576
1577 if (!skb_queue_empty(&tid->retry_q))
1578 ieee80211_sta_set_buffered(sta, tid->tidno, true);
1579
1580 }
1581 }
1582
1583 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1584 {
1585 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1586 struct ath_atx_tid *tid;
1587 struct ath_txq *txq;
1588 int tidno;
1589
1590 ath_dbg(common, XMIT, "%s called\n", __func__);
1591
1592 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1593 tid = ath_node_to_tid(an, tidno);
1594 txq = tid->txq;
1595
1596 ath_txq_lock(sc, txq);
1597 tid->clear_ps_filter = true;
1598 if (!skb_queue_empty(&tid->retry_q)) {
1599 ath_tx_queue_tid(sc, tid);
1600 ath_txq_schedule(sc, txq);
1601 }
1602 ath_txq_unlock_complete(sc, txq);
1603
1604 }
1605 }
1606
1607
1608 static void
1609 ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val)
1610 {
1611 struct ieee80211_hdr *hdr;
1612 u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1613 u16 mask_val = mask * val;
1614
1615 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
1616 if ((hdr->frame_control & mask) != mask_val) {
1617 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val;
1618 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
1619 sizeof(*hdr), DMA_TO_DEVICE);
1620 }
1621 }
1622
1623 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1624 struct ieee80211_sta *sta,
1625 u16 tids, int nframes,
1626 enum ieee80211_frame_release_type reason,
1627 bool more_data)
1628 {
1629 struct ath_softc *sc = hw->priv;
1630 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1631 struct ath_txq *txq = sc->tx.uapsdq;
1632 struct ieee80211_tx_info *info;
1633 struct list_head bf_q;
1634 struct ath_buf *bf_tail = NULL, *bf = NULL;
1635 int sent = 0;
1636 int i, ret;
1637
1638 INIT_LIST_HEAD(&bf_q);
1639 for (i = 0; tids && nframes; i++, tids >>= 1) {
1640 struct ath_atx_tid *tid;
1641
1642 if (!(tids & 1))
1643 continue;
1644
1645 tid = ATH_AN_2_TID(an, i);
1646
1647 ath_txq_lock(sc, tid->txq);
1648 while (nframes > 0) {
1649 ret = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq,
1650 tid, &bf);
1651 if (ret < 0)
1652 break;
1653
1654 ath9k_set_moredata(sc, bf, true);
1655 list_add_tail(&bf->list, &bf_q);
1656 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1657 if (bf_isampdu(bf))
1658 bf->bf_state.bf_type &= ~BUF_AGGR;
1659 if (bf_tail)
1660 bf_tail->bf_next = bf;
1661
1662 bf_tail = bf;
1663 nframes--;
1664 sent++;
1665 TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw);
1666
1667 if (an->sta && skb_queue_empty(&tid->retry_q))
1668 ieee80211_sta_set_buffered(an->sta, i, false);
1669 }
1670 ath_txq_unlock_complete(sc, tid->txq);
1671 }
1672
1673 if (list_empty(&bf_q))
1674 return;
1675
1676 if (!more_data)
1677 ath9k_set_moredata(sc, bf_tail, false);
1678
1679 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1680 info->flags |= IEEE80211_TX_STATUS_EOSP;
1681
1682 bf = list_first_entry(&bf_q, struct ath_buf, list);
1683 ath_txq_lock(sc, txq);
1684 ath_tx_fill_desc(sc, bf, txq, 0);
1685 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1686 ath_txq_unlock(sc, txq);
1687 }
1688
1689 /********************/
1690 /* Queue Management */
1691 /********************/
1692
1693 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1694 {
1695 struct ath_hw *ah = sc->sc_ah;
1696 struct ath9k_tx_queue_info qi;
1697 static const int subtype_txq_to_hwq[] = {
1698 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1699 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1700 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1701 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1702 };
1703 int axq_qnum, i;
1704
1705 memset(&qi, 0, sizeof(qi));
1706 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1707 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1708 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1709 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1710 qi.tqi_physCompBuf = 0;
1711
1712 /*
1713 * Enable interrupts only for EOL and DESC conditions.
1714 * We mark tx descriptors to receive a DESC interrupt
1715 * when a tx queue gets deep; otherwise waiting for the
1716 * EOL to reap descriptors. Note that this is done to
1717 * reduce interrupt load and this only defers reaping
1718 * descriptors, never transmitting frames. Aside from
1719 * reducing interrupts this also permits more concurrency.
1720 * The only potential downside is if the tx queue backs
1721 * up in which case the top half of the kernel may backup
1722 * due to a lack of tx descriptors.
1723 *
1724 * The UAPSD queue is an exception, since we take a desc-
1725 * based intr on the EOSP frames.
1726 */
1727 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1728 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1729 } else {
1730 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1731 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1732 else
1733 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1734 TXQ_FLAG_TXDESCINT_ENABLE;
1735 }
1736 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1737 if (axq_qnum == -1) {
1738 /*
1739 * NB: don't print a message, this happens
1740 * normally on parts with too few tx queues
1741 */
1742 return NULL;
1743 }
1744 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1745 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1746
1747 txq->axq_qnum = axq_qnum;
1748 txq->mac80211_qnum = -1;
1749 txq->axq_link = NULL;
1750 __skb_queue_head_init(&txq->complete_q);
1751 INIT_LIST_HEAD(&txq->axq_q);
1752 spin_lock_init(&txq->axq_lock);
1753 txq->axq_depth = 0;
1754 txq->axq_ampdu_depth = 0;
1755 txq->axq_tx_inprogress = false;
1756 sc->tx.txqsetup |= 1<<axq_qnum;
1757
1758 txq->txq_headidx = txq->txq_tailidx = 0;
1759 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1760 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1761 }
1762 return &sc->tx.txq[axq_qnum];
1763 }
1764
1765 int ath_txq_update(struct ath_softc *sc, int qnum,
1766 struct ath9k_tx_queue_info *qinfo)
1767 {
1768 struct ath_hw *ah = sc->sc_ah;
1769 int error = 0;
1770 struct ath9k_tx_queue_info qi;
1771
1772 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1773
1774 ath9k_hw_get_txq_props(ah, qnum, &qi);
1775 qi.tqi_aifs = qinfo->tqi_aifs;
1776 qi.tqi_cwmin = qinfo->tqi_cwmin;
1777 qi.tqi_cwmax = qinfo->tqi_cwmax;
1778 qi.tqi_burstTime = qinfo->tqi_burstTime;
1779 qi.tqi_readyTime = qinfo->tqi_readyTime;
1780
1781 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1782 ath_err(ath9k_hw_common(sc->sc_ah),
1783 "Unable to update hardware queue %u!\n", qnum);
1784 error = -EIO;
1785 } else {
1786 ath9k_hw_resettxqueue(ah, qnum);
1787 }
1788
1789 return error;
1790 }
1791
1792 int ath_cabq_update(struct ath_softc *sc)
1793 {
1794 struct ath9k_tx_queue_info qi;
1795 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1796 int qnum = sc->beacon.cabq->axq_qnum;
1797
1798 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1799
1800 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1801 ATH_CABQ_READY_TIME) / 100;
1802 ath_txq_update(sc, qnum, &qi);
1803
1804 return 0;
1805 }
1806
1807 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1808 struct list_head *list)
1809 {
1810 struct ath_buf *bf, *lastbf;
1811 struct list_head bf_head;
1812 struct ath_tx_status ts;
1813
1814 memset(&ts, 0, sizeof(ts));
1815 ts.ts_status = ATH9K_TX_FLUSH;
1816 INIT_LIST_HEAD(&bf_head);
1817
1818 while (!list_empty(list)) {
1819 bf = list_first_entry(list, struct ath_buf, list);
1820
1821 if (bf->bf_state.stale) {
1822 list_del(&bf->list);
1823
1824 ath_tx_return_buffer(sc, bf);
1825 continue;
1826 }
1827
1828 lastbf = bf->bf_lastbf;
1829 list_cut_position(&bf_head, list, &lastbf->list);
1830 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1831 }
1832 }
1833
1834 /*
1835 * Drain a given TX queue (could be Beacon or Data)
1836 *
1837 * This assumes output has been stopped and
1838 * we do not need to block ath_tx_tasklet.
1839 */
1840 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1841 {
1842 rcu_read_lock();
1843 ath_txq_lock(sc, txq);
1844
1845 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1846 int idx = txq->txq_tailidx;
1847
1848 while (!list_empty(&txq->txq_fifo[idx])) {
1849 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1850
1851 INCR(idx, ATH_TXFIFO_DEPTH);
1852 }
1853 txq->txq_tailidx = idx;
1854 }
1855
1856 txq->axq_link = NULL;
1857 txq->axq_tx_inprogress = false;
1858 ath_drain_txq_list(sc, txq, &txq->axq_q);
1859
1860 ath_txq_unlock_complete(sc, txq);
1861 rcu_read_unlock();
1862 }
1863
1864 bool ath_drain_all_txq(struct ath_softc *sc)
1865 {
1866 struct ath_hw *ah = sc->sc_ah;
1867 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1868 struct ath_txq *txq;
1869 int i;
1870 u32 npend = 0;
1871
1872 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1873 return true;
1874
1875 ath9k_hw_abort_tx_dma(ah);
1876
1877 /* Check if any queue remains active */
1878 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1879 if (!ATH_TXQ_SETUP(sc, i))
1880 continue;
1881
1882 if (!sc->tx.txq[i].axq_depth)
1883 continue;
1884
1885 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1886 npend |= BIT(i);
1887 }
1888
1889 if (npend) {
1890 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1891 ath_dbg(common, RESET,
1892 "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1893 }
1894
1895 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1896 if (!ATH_TXQ_SETUP(sc, i))
1897 continue;
1898
1899 txq = &sc->tx.txq[i];
1900 ath_draintxq(sc, txq);
1901 }
1902
1903 return !npend;
1904 }
1905
1906 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1907 {
1908 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1909 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1910 }
1911
1912 /* For each acq entry, for each tid, try to schedule packets
1913 * for transmit until ampdu_depth has reached min Q depth.
1914 */
1915 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1916 {
1917 struct ieee80211_hw *hw = sc->hw;
1918 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1919 struct ieee80211_txq *queue;
1920 struct ath_atx_tid *tid;
1921 int ret;
1922
1923 if (txq->mac80211_qnum < 0)
1924 return;
1925
1926 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1927 return;
1928
1929 ieee80211_txq_schedule_start(hw, txq->mac80211_qnum);
1930 spin_lock_bh(&sc->chan_lock);
1931 rcu_read_lock();
1932
1933 if (sc->cur_chan->stopped)
1934 goto out;
1935
1936 while ((queue = ieee80211_next_txq(hw, txq->mac80211_qnum))) {
1937 bool force;
1938
1939 tid = (struct ath_atx_tid *)queue->drv_priv;
1940
1941 ret = ath_tx_sched_aggr(sc, txq, tid);
1942 ath_dbg(common, QUEUE, "ath_tx_sched_aggr returned %d\n", ret);
1943
1944 force = !skb_queue_empty(&tid->retry_q);
1945 ieee80211_return_txq(hw, queue, force);
1946 }
1947
1948 out:
1949 rcu_read_unlock();
1950 spin_unlock_bh(&sc->chan_lock);
1951 ieee80211_txq_schedule_end(hw, txq->mac80211_qnum);
1952 }
1953
1954 void ath_txq_schedule_all(struct ath_softc *sc)
1955 {
1956 struct ath_txq *txq;
1957 int i;
1958
1959 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1960 txq = sc->tx.txq_map[i];
1961
1962 spin_lock_bh(&txq->axq_lock);
1963 ath_txq_schedule(sc, txq);
1964 spin_unlock_bh(&txq->axq_lock);
1965 }
1966 }
1967
1968 /***********/
1969 /* TX, DMA */
1970 /***********/
1971
1972 /*
1973 * Insert a chain of ath_buf (descriptors) on a txq and
1974 * assume the descriptors are already chained together by caller.
1975 */
1976 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1977 struct list_head *head, bool internal)
1978 {
1979 struct ath_hw *ah = sc->sc_ah;
1980 struct ath_common *common = ath9k_hw_common(ah);
1981 struct ath_buf *bf, *bf_last;
1982 bool puttxbuf = false;
1983 bool edma;
1984
1985 /*
1986 * Insert the frame on the outbound list and
1987 * pass it on to the hardware.
1988 */
1989
1990 if (list_empty(head))
1991 return;
1992
1993 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1994 bf = list_first_entry(head, struct ath_buf, list);
1995 bf_last = list_entry(head->prev, struct ath_buf, list);
1996
1997 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1998 txq->axq_qnum, txq->axq_depth);
1999
2000 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2001 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2002 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2003 puttxbuf = true;
2004 } else {
2005 list_splice_tail_init(head, &txq->axq_q);
2006
2007 if (txq->axq_link) {
2008 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2009 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2010 txq->axq_qnum, txq->axq_link,
2011 ito64(bf->bf_daddr), bf->bf_desc);
2012 } else if (!edma)
2013 puttxbuf = true;
2014
2015 txq->axq_link = bf_last->bf_desc;
2016 }
2017
2018 if (puttxbuf) {
2019 TX_STAT_INC(sc, txq->axq_qnum, puttxbuf);
2020 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2021 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2022 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2023 }
2024
2025 if (!edma || sc->tx99_state) {
2026 TX_STAT_INC(sc, txq->axq_qnum, txstart);
2027 ath9k_hw_txstart(ah, txq->axq_qnum);
2028 }
2029
2030 if (!internal) {
2031 while (bf) {
2032 txq->axq_depth++;
2033 if (bf_is_ampdu_not_probing(bf))
2034 txq->axq_ampdu_depth++;
2035
2036 bf_last = bf->bf_lastbf;
2037 bf = bf_last->bf_next;
2038 bf_last->bf_next = NULL;
2039 }
2040 }
2041 }
2042
2043 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2044 struct ath_atx_tid *tid, struct sk_buff *skb)
2045 {
2046 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2047 struct ath_frame_info *fi = get_frame_info(skb);
2048 struct list_head bf_head;
2049 struct ath_buf *bf = fi->bf;
2050
2051 INIT_LIST_HEAD(&bf_head);
2052 list_add_tail(&bf->list, &bf_head);
2053 bf->bf_state.bf_type = 0;
2054 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2055 bf->bf_state.bf_type = BUF_AMPDU;
2056 ath_tx_addto_baw(sc, tid, bf);
2057 }
2058
2059 bf->bf_next = NULL;
2060 bf->bf_lastbf = bf;
2061 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2062 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2063 TX_STAT_INC(sc, txq->axq_qnum, queued);
2064 }
2065
2066 static void setup_frame_info(struct ieee80211_hw *hw,
2067 struct ieee80211_sta *sta,
2068 struct sk_buff *skb,
2069 int framelen)
2070 {
2071 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2072 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2073 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2074 const struct ieee80211_rate *rate;
2075 struct ath_frame_info *fi = get_frame_info(skb);
2076 struct ath_node *an = NULL;
2077 enum ath9k_key_type keytype;
2078 bool short_preamble = false;
2079 u8 txpower;
2080
2081 /*
2082 * We check if Short Preamble is needed for the CTS rate by
2083 * checking the BSS's global flag.
2084 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2085 */
2086 if (tx_info->control.vif &&
2087 tx_info->control.vif->bss_conf.use_short_preamble)
2088 short_preamble = true;
2089
2090 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2091 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2092
2093 if (sta)
2094 an = (struct ath_node *) sta->drv_priv;
2095
2096 if (tx_info->control.vif) {
2097 struct ieee80211_vif *vif = tx_info->control.vif;
2098 if (vif->bss_conf.txpower == INT_MIN)
2099 goto nonvifpower;
2100 txpower = 2 * vif->bss_conf.txpower;
2101 } else {
2102 struct ath_softc *sc;
2103 nonvifpower:
2104 sc = hw->priv;
2105
2106 txpower = sc->cur_chan->cur_txpower;
2107 }
2108
2109 memset(fi, 0, sizeof(*fi));
2110 fi->txq = -1;
2111 if (hw_key)
2112 fi->keyix = hw_key->hw_key_idx;
2113 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2114 fi->keyix = an->ps_key;
2115 else
2116 fi->keyix = ATH9K_TXKEYIX_INVALID;
2117 fi->keytype = keytype;
2118 fi->framelen = framelen;
2119 fi->tx_power = txpower;
2120
2121 if (!rate)
2122 return;
2123 fi->rtscts_rate = rate->hw_value;
2124 if (short_preamble)
2125 fi->rtscts_rate |= rate->hw_value_short;
2126 }
2127
2128 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2129 {
2130 struct ath_hw *ah = sc->sc_ah;
2131 struct ath9k_channel *curchan = ah->curchan;
2132
2133 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2134 (chainmask == 0x7) && (rate < 0x90))
2135 return 0x3;
2136 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2137 IS_CCK_RATE(rate))
2138 return 0x2;
2139 else
2140 return chainmask;
2141 }
2142
2143 /*
2144 * Assign a descriptor (and sequence number if necessary,
2145 * and map buffer for DMA. Frees skb on error
2146 */
2147 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2148 struct ath_txq *txq,
2149 struct ath_atx_tid *tid,
2150 struct sk_buff *skb)
2151 {
2152 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2153 struct ath_frame_info *fi = get_frame_info(skb);
2154 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2155 struct ath_buf *bf;
2156 int fragno;
2157 u16 seqno;
2158
2159 bf = ath_tx_get_buffer(sc);
2160 if (!bf) {
2161 ath_dbg(common, XMIT, "TX buffers are full\n");
2162 return NULL;
2163 }
2164
2165 ATH_TXBUF_RESET(bf);
2166
2167 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2168 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2169 seqno = tid->seq_next;
2170 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2171
2172 if (fragno)
2173 hdr->seq_ctrl |= cpu_to_le16(fragno);
2174
2175 if (!ieee80211_has_morefrags(hdr->frame_control))
2176 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2177
2178 bf->bf_state.seqno = seqno;
2179 }
2180
2181 bf->bf_mpdu = skb;
2182
2183 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2184 skb->len, DMA_TO_DEVICE);
2185 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2186 bf->bf_mpdu = NULL;
2187 bf->bf_buf_addr = 0;
2188 ath_err(ath9k_hw_common(sc->sc_ah),
2189 "dma_mapping_error() on TX\n");
2190 ath_tx_return_buffer(sc, bf);
2191 return NULL;
2192 }
2193
2194 fi->bf = bf;
2195
2196 return bf;
2197 }
2198
2199 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2200 {
2201 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2202 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2203 struct ieee80211_vif *vif = info->control.vif;
2204 struct ath_vif *avp;
2205
2206 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2207 return;
2208
2209 if (!vif)
2210 return;
2211
2212 avp = (struct ath_vif *)vif->drv_priv;
2213
2214 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2215 avp->seq_no += 0x10;
2216
2217 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2218 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2219 }
2220
2221 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2222 struct ath_tx_control *txctl)
2223 {
2224 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2225 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2226 struct ieee80211_sta *sta = txctl->sta;
2227 struct ieee80211_vif *vif = info->control.vif;
2228 struct ath_vif *avp;
2229 struct ath_softc *sc = hw->priv;
2230 int frmlen = skb->len + FCS_LEN;
2231 int padpos, padsize;
2232
2233 /* NOTE: sta can be NULL according to net/mac80211.h */
2234 if (sta)
2235 txctl->an = (struct ath_node *)sta->drv_priv;
2236 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2237 avp = (void *)vif->drv_priv;
2238 txctl->an = &avp->mcast_node;
2239 }
2240
2241 if (info->control.hw_key)
2242 frmlen += info->control.hw_key->icv_len;
2243
2244 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2245
2246 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2247 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2248 !ieee80211_is_data(hdr->frame_control))
2249 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2250
2251 /* Add the padding after the header if this is not already done */
2252 padpos = ieee80211_hdrlen(hdr->frame_control);
2253 padsize = padpos & 3;
2254 if (padsize && skb->len > padpos) {
2255 if (skb_headroom(skb) < padsize)
2256 return -ENOMEM;
2257
2258 skb_push(skb, padsize);
2259 memmove(skb->data, skb->data + padsize, padpos);
2260 }
2261
2262 setup_frame_info(hw, sta, skb, frmlen);
2263 return 0;
2264 }
2265
2266
2267 /* Upon failure caller should free skb */
2268 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2269 struct ath_tx_control *txctl)
2270 {
2271 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2272 struct ieee80211_sta *sta = txctl->sta;
2273 struct ieee80211_vif *vif = info->control.vif;
2274 struct ath_frame_info *fi = get_frame_info(skb);
2275 struct ath_softc *sc = hw->priv;
2276 struct ath_txq *txq = txctl->txq;
2277 struct ath_atx_tid *tid = NULL;
2278 struct ath_node *an = NULL;
2279 struct ath_buf *bf;
2280 bool ps_resp;
2281 int q, ret;
2282
2283 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2284
2285 ret = ath_tx_prepare(hw, skb, txctl);
2286 if (ret)
2287 return ret;
2288
2289 /*
2290 * At this point, the vif, hw_key and sta pointers in the tx control
2291 * info are no longer valid (overwritten by the ath_frame_info data.
2292 */
2293
2294 q = skb_get_queue_mapping(skb);
2295
2296 if (ps_resp)
2297 txq = sc->tx.uapsdq;
2298
2299 if (txctl->sta) {
2300 an = (struct ath_node *) sta->drv_priv;
2301 tid = ath_get_skb_tid(sc, an, skb);
2302 }
2303
2304 ath_txq_lock(sc, txq);
2305 if (txq == sc->tx.txq_map[q]) {
2306 fi->txq = q;
2307 ++txq->pending_frames;
2308 }
2309
2310 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2311 if (!bf) {
2312 ath_txq_skb_done(sc, txq, skb);
2313 if (txctl->paprd)
2314 dev_kfree_skb_any(skb);
2315 else
2316 ieee80211_free_txskb(sc->hw, skb);
2317 goto out;
2318 }
2319
2320 bf->bf_state.bfs_paprd = txctl->paprd;
2321
2322 if (txctl->paprd)
2323 bf->bf_state.bfs_paprd_timestamp = jiffies;
2324
2325 ath_set_rates(vif, sta, bf);
2326 ath_tx_send_normal(sc, txq, tid, skb);
2327
2328 out:
2329 ath_txq_unlock(sc, txq);
2330
2331 return 0;
2332 }
2333
2334 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2335 struct sk_buff *skb)
2336 {
2337 struct ath_softc *sc = hw->priv;
2338 struct ath_tx_control txctl = {
2339 .txq = sc->beacon.cabq
2340 };
2341 struct ath_tx_info info = {};
2342 struct ath_buf *bf_tail = NULL;
2343 struct ath_buf *bf;
2344 LIST_HEAD(bf_q);
2345 int duration = 0;
2346 int max_duration;
2347
2348 max_duration =
2349 sc->cur_chan->beacon.beacon_interval * 1000 *
2350 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2351
2352 do {
2353 struct ath_frame_info *fi = get_frame_info(skb);
2354
2355 if (ath_tx_prepare(hw, skb, &txctl))
2356 break;
2357
2358 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2359 if (!bf)
2360 break;
2361
2362 bf->bf_lastbf = bf;
2363 ath_set_rates(vif, NULL, bf);
2364 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2365 duration += info.rates[0].PktDuration;
2366 if (bf_tail)
2367 bf_tail->bf_next = bf;
2368
2369 list_add_tail(&bf->list, &bf_q);
2370 bf_tail = bf;
2371 skb = NULL;
2372
2373 if (duration > max_duration)
2374 break;
2375
2376 skb = ieee80211_get_buffered_bc(hw, vif);
2377 } while(skb);
2378
2379 if (skb)
2380 ieee80211_free_txskb(hw, skb);
2381
2382 if (list_empty(&bf_q))
2383 return;
2384
2385 bf = list_last_entry(&bf_q, struct ath_buf, list);
2386 ath9k_set_moredata(sc, bf, false);
2387
2388 bf = list_first_entry(&bf_q, struct ath_buf, list);
2389 ath_txq_lock(sc, txctl.txq);
2390 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2391 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2392 TX_STAT_INC(sc, txctl.txq->axq_qnum, queued);
2393 ath_txq_unlock(sc, txctl.txq);
2394 }
2395
2396 /*****************/
2397 /* TX Completion */
2398 /*****************/
2399
2400 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2401 int tx_flags, struct ath_txq *txq,
2402 struct ieee80211_sta *sta)
2403 {
2404 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2405 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2406 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2407 int padpos, padsize;
2408 unsigned long flags;
2409
2410 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2411
2412 if (sc->sc_ah->caldata)
2413 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2414
2415 if (!(tx_flags & ATH_TX_ERROR)) {
2416 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2417 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2418 else
2419 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2420 }
2421
2422 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2423 padpos = ieee80211_hdrlen(hdr->frame_control);
2424 padsize = padpos & 3;
2425 if (padsize && skb->len>padpos+padsize) {
2426 /*
2427 * Remove MAC header padding before giving the frame back to
2428 * mac80211.
2429 */
2430 memmove(skb->data + padsize, skb->data, padpos);
2431 skb_pull(skb, padsize);
2432 }
2433 }
2434
2435 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2436 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2437 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2438 ath_dbg(common, PS,
2439 "Going back to sleep after having received TX status (0x%lx)\n",
2440 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2441 PS_WAIT_FOR_CAB |
2442 PS_WAIT_FOR_PSPOLL_DATA |
2443 PS_WAIT_FOR_TX_ACK));
2444 }
2445 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2446
2447 ath_txq_skb_done(sc, txq, skb);
2448 tx_info->status.status_driver_data[0] = sta;
2449 __skb_queue_tail(&txq->complete_q, skb);
2450 }
2451
2452 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2453 struct ath_txq *txq, struct list_head *bf_q,
2454 struct ieee80211_sta *sta,
2455 struct ath_tx_status *ts, int txok)
2456 {
2457 struct sk_buff *skb = bf->bf_mpdu;
2458 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2459 unsigned long flags;
2460 int tx_flags = 0;
2461
2462 if (!txok)
2463 tx_flags |= ATH_TX_ERROR;
2464
2465 if (ts->ts_status & ATH9K_TXERR_FILT)
2466 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2467
2468 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2469 bf->bf_buf_addr = 0;
2470 if (sc->tx99_state)
2471 goto skip_tx_complete;
2472
2473 if (bf->bf_state.bfs_paprd) {
2474 if (time_after(jiffies,
2475 bf->bf_state.bfs_paprd_timestamp +
2476 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2477 dev_kfree_skb_any(skb);
2478 else
2479 complete(&sc->paprd_complete);
2480 } else {
2481 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2482 ath_tx_complete(sc, skb, tx_flags, txq, sta);
2483 }
2484 skip_tx_complete:
2485 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2486 * accidentally reference it later.
2487 */
2488 bf->bf_mpdu = NULL;
2489
2490 /*
2491 * Return the list of ath_buf of this mpdu to free queue
2492 */
2493 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2494 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2495 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2496 }
2497
2498 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2499 struct ath_tx_status *ts, int nframes, int nbad,
2500 int txok)
2501 {
2502 struct sk_buff *skb = bf->bf_mpdu;
2503 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2504 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2505 struct ieee80211_hw *hw = sc->hw;
2506 struct ath_hw *ah = sc->sc_ah;
2507 u8 i, tx_rateindex;
2508
2509 if (txok)
2510 tx_info->status.ack_signal = ts->ts_rssi;
2511
2512 tx_rateindex = ts->ts_rateindex;
2513 WARN_ON(tx_rateindex >= hw->max_rates);
2514
2515 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2516 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2517
2518 BUG_ON(nbad > nframes);
2519 }
2520 tx_info->status.ampdu_len = nframes;
2521 tx_info->status.ampdu_ack_len = nframes - nbad;
2522
2523 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2524 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2525 /*
2526 * If an underrun error is seen assume it as an excessive
2527 * retry only if max frame trigger level has been reached
2528 * (2 KB for single stream, and 4 KB for dual stream).
2529 * Adjust the long retry as if the frame was tried
2530 * hw->max_rate_tries times to affect how rate control updates
2531 * PER for the failed rate.
2532 * In case of congestion on the bus penalizing this type of
2533 * underruns should help hardware actually transmit new frames
2534 * successfully by eventually preferring slower rates.
2535 * This itself should also alleviate congestion on the bus.
2536 */
2537 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2538 ATH9K_TX_DELIM_UNDERRUN)) &&
2539 ieee80211_is_data(hdr->frame_control) &&
2540 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2541 tx_info->status.rates[tx_rateindex].count =
2542 hw->max_rate_tries;
2543 }
2544
2545 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2546 tx_info->status.rates[i].count = 0;
2547 tx_info->status.rates[i].idx = -1;
2548 }
2549
2550 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2551
2552 /* we report airtime in ath_tx_count_airtime(), don't report twice */
2553 tx_info->status.tx_time = 0;
2554 }
2555
2556 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2557 {
2558 struct ath_hw *ah = sc->sc_ah;
2559 struct ath_common *common = ath9k_hw_common(ah);
2560 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2561 struct list_head bf_head;
2562 struct ath_desc *ds;
2563 struct ath_tx_status ts;
2564 int status;
2565
2566 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2567 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2568 txq->axq_link);
2569
2570 ath_txq_lock(sc, txq);
2571 for (;;) {
2572 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2573 break;
2574
2575 if (list_empty(&txq->axq_q)) {
2576 txq->axq_link = NULL;
2577 ath_txq_schedule(sc, txq);
2578 break;
2579 }
2580 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2581
2582 /*
2583 * There is a race condition that a BH gets scheduled
2584 * after sw writes TxE and before hw re-load the last
2585 * descriptor to get the newly chained one.
2586 * Software must keep the last DONE descriptor as a
2587 * holding descriptor - software does so by marking
2588 * it with the STALE flag.
2589 */
2590 bf_held = NULL;
2591 if (bf->bf_state.stale) {
2592 bf_held = bf;
2593 if (list_is_last(&bf_held->list, &txq->axq_q))
2594 break;
2595
2596 bf = list_entry(bf_held->list.next, struct ath_buf,
2597 list);
2598 }
2599
2600 lastbf = bf->bf_lastbf;
2601 ds = lastbf->bf_desc;
2602
2603 memset(&ts, 0, sizeof(ts));
2604 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2605 if (status == -EINPROGRESS)
2606 break;
2607
2608 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2609
2610 /*
2611 * Remove ath_buf's of the same transmit unit from txq,
2612 * however leave the last descriptor back as the holding
2613 * descriptor for hw.
2614 */
2615 lastbf->bf_state.stale = true;
2616 INIT_LIST_HEAD(&bf_head);
2617 if (!list_is_singular(&lastbf->list))
2618 list_cut_position(&bf_head,
2619 &txq->axq_q, lastbf->list.prev);
2620
2621 if (bf_held) {
2622 list_del(&bf_held->list);
2623 ath_tx_return_buffer(sc, bf_held);
2624 }
2625
2626 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2627 }
2628 ath_txq_unlock_complete(sc, txq);
2629 }
2630
2631 void ath_tx_tasklet(struct ath_softc *sc)
2632 {
2633 struct ath_hw *ah = sc->sc_ah;
2634 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2635 int i;
2636
2637 rcu_read_lock();
2638 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2639 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2640 ath_tx_processq(sc, &sc->tx.txq[i]);
2641 }
2642 rcu_read_unlock();
2643 }
2644
2645 void ath_tx_edma_tasklet(struct ath_softc *sc)
2646 {
2647 struct ath_tx_status ts;
2648 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2649 struct ath_hw *ah = sc->sc_ah;
2650 struct ath_txq *txq;
2651 struct ath_buf *bf, *lastbf;
2652 struct list_head bf_head;
2653 struct list_head *fifo_list;
2654 int status;
2655
2656 rcu_read_lock();
2657 for (;;) {
2658 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2659 break;
2660
2661 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2662 if (status == -EINPROGRESS)
2663 break;
2664 if (status == -EIO) {
2665 ath_dbg(common, XMIT, "Error processing tx status\n");
2666 break;
2667 }
2668
2669 /* Process beacon completions separately */
2670 if (ts.qid == sc->beacon.beaconq) {
2671 sc->beacon.tx_processed = true;
2672 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2673
2674 if (ath9k_is_chanctx_enabled()) {
2675 ath_chanctx_event(sc, NULL,
2676 ATH_CHANCTX_EVENT_BEACON_SENT);
2677 }
2678
2679 ath9k_csa_update(sc);
2680 continue;
2681 }
2682
2683 txq = &sc->tx.txq[ts.qid];
2684
2685 ath_txq_lock(sc, txq);
2686
2687 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2688
2689 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2690 if (list_empty(fifo_list)) {
2691 ath_txq_unlock(sc, txq);
2692 break;
2693 }
2694
2695 bf = list_first_entry(fifo_list, struct ath_buf, list);
2696 if (bf->bf_state.stale) {
2697 list_del(&bf->list);
2698 ath_tx_return_buffer(sc, bf);
2699 bf = list_first_entry(fifo_list, struct ath_buf, list);
2700 }
2701
2702 lastbf = bf->bf_lastbf;
2703
2704 INIT_LIST_HEAD(&bf_head);
2705 if (list_is_last(&lastbf->list, fifo_list)) {
2706 list_splice_tail_init(fifo_list, &bf_head);
2707 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2708
2709 if (!list_empty(&txq->axq_q)) {
2710 struct list_head bf_q;
2711
2712 INIT_LIST_HEAD(&bf_q);
2713 txq->axq_link = NULL;
2714 list_splice_tail_init(&txq->axq_q, &bf_q);
2715 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2716 }
2717 } else {
2718 lastbf->bf_state.stale = true;
2719 if (bf != lastbf)
2720 list_cut_position(&bf_head, fifo_list,
2721 lastbf->list.prev);
2722 }
2723
2724 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2725 ath_txq_unlock_complete(sc, txq);
2726 }
2727 rcu_read_unlock();
2728 }
2729
2730 /*****************/
2731 /* Init, Cleanup */
2732 /*****************/
2733
2734 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2735 {
2736 struct ath_descdma *dd = &sc->txsdma;
2737 u8 txs_len = sc->sc_ah->caps.txs_len;
2738
2739 dd->dd_desc_len = size * txs_len;
2740 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2741 &dd->dd_desc_paddr, GFP_KERNEL);
2742 if (!dd->dd_desc)
2743 return -ENOMEM;
2744
2745 return 0;
2746 }
2747
2748 static int ath_tx_edma_init(struct ath_softc *sc)
2749 {
2750 int err;
2751
2752 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2753 if (!err)
2754 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2755 sc->txsdma.dd_desc_paddr,
2756 ATH_TXSTATUS_RING_SIZE);
2757
2758 return err;
2759 }
2760
2761 int ath_tx_init(struct ath_softc *sc, int nbufs)
2762 {
2763 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2764 int error = 0;
2765
2766 spin_lock_init(&sc->tx.txbuflock);
2767
2768 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2769 "tx", nbufs, 1, 1);
2770 if (error != 0) {
2771 ath_err(common,
2772 "Failed to allocate tx descriptors: %d\n", error);
2773 return error;
2774 }
2775
2776 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2777 "beacon", ATH_BCBUF, 1, 1);
2778 if (error != 0) {
2779 ath_err(common,
2780 "Failed to allocate beacon descriptors: %d\n", error);
2781 return error;
2782 }
2783
2784 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2785 error = ath_tx_edma_init(sc);
2786
2787 return error;
2788 }
2789
2790 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2791 {
2792 struct ath_atx_tid *tid;
2793 int tidno, acno;
2794
2795 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2796 tid = ath_node_to_tid(an, tidno);
2797 tid->an = an;
2798 tid->tidno = tidno;
2799 tid->seq_start = tid->seq_next = 0;
2800 tid->baw_size = WME_MAX_BA;
2801 tid->baw_head = tid->baw_tail = 0;
2802 tid->active = false;
2803 tid->clear_ps_filter = true;
2804 __skb_queue_head_init(&tid->retry_q);
2805 INIT_LIST_HEAD(&tid->list);
2806 acno = TID_TO_WME_AC(tidno);
2807 tid->txq = sc->tx.txq_map[acno];
2808
2809 if (!an->sta)
2810 break; /* just one multicast ath_atx_tid */
2811 }
2812 }
2813
2814 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2815 {
2816 struct ath_atx_tid *tid;
2817 struct ath_txq *txq;
2818 int tidno;
2819
2820 rcu_read_lock();
2821
2822 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2823 tid = ath_node_to_tid(an, tidno);
2824 txq = tid->txq;
2825
2826 ath_txq_lock(sc, txq);
2827
2828 if (!list_empty(&tid->list))
2829 list_del_init(&tid->list);
2830
2831 ath_tid_drain(sc, txq, tid);
2832 tid->active = false;
2833
2834 ath_txq_unlock(sc, txq);
2835
2836 if (!an->sta)
2837 break; /* just one multicast ath_atx_tid */
2838 }
2839
2840 rcu_read_unlock();
2841 }
2842
2843 #ifdef CONFIG_ATH9K_TX99
2844
2845 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2846 struct ath_tx_control *txctl)
2847 {
2848 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2849 struct ath_frame_info *fi = get_frame_info(skb);
2850 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2851 struct ath_buf *bf;
2852 int padpos, padsize;
2853
2854 padpos = ieee80211_hdrlen(hdr->frame_control);
2855 padsize = padpos & 3;
2856
2857 if (padsize && skb->len > padpos) {
2858 if (skb_headroom(skb) < padsize) {
2859 ath_dbg(common, XMIT,
2860 "tx99 padding failed\n");
2861 return -EINVAL;
2862 }
2863
2864 skb_push(skb, padsize);
2865 memmove(skb->data, skb->data + padsize, padpos);
2866 }
2867
2868 fi->keyix = ATH9K_TXKEYIX_INVALID;
2869 fi->framelen = skb->len + FCS_LEN;
2870 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2871
2872 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2873 if (!bf) {
2874 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2875 return -EINVAL;
2876 }
2877
2878 ath_set_rates(sc->tx99_vif, NULL, bf);
2879
2880 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2881 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2882
2883 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2884
2885 return 0;
2886 }
2887
2888 #endif /* CONFIG_ATH9K_TX99 */
Linux with added FPC-III support