1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
10 * Copyright(C) 2018 - 2019 Intel Corporation
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * The full GNU General Public License is included in this distribution in the
22 * file called COPYING.
24 * Contact Information:
25 * Intel Linux Wireless <linuxwifi@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
31 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
32 * Copyright (C) 2018 - 2019 Intel Corporation
33 * All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
39 * * Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * * Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in
43 * the documentation and/or other materials provided with the
45 * * Neither the name Intel Corporation nor the names of its
46 * contributors may be used to endorse or promote products derived
47 * from this software without specific prior written permission.
49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
62 #include <linux/delay.h>
63 #include <linux/device.h>
64 #include <linux/export.h>
69 #include "iwl-debug.h"
73 void iwl_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
75 trace_iwlwifi_dev_iowrite8(trans
->dev
, ofs
, val
);
76 iwl_trans_write8(trans
, ofs
, val
);
78 IWL_EXPORT_SYMBOL(iwl_write8
);
80 void iwl_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
82 trace_iwlwifi_dev_iowrite32(trans
->dev
, ofs
, val
);
83 iwl_trans_write32(trans
, ofs
, val
);
85 IWL_EXPORT_SYMBOL(iwl_write32
);
87 void iwl_write64(struct iwl_trans
*trans
, u64 ofs
, u64 val
)
89 trace_iwlwifi_dev_iowrite64(trans
->dev
, ofs
, val
);
90 iwl_trans_write32(trans
, ofs
, lower_32_bits(val
));
91 iwl_trans_write32(trans
, ofs
+ 4, upper_32_bits(val
));
93 IWL_EXPORT_SYMBOL(iwl_write64
);
95 u32
iwl_read32(struct iwl_trans
*trans
, u32 ofs
)
97 u32 val
= iwl_trans_read32(trans
, ofs
);
99 trace_iwlwifi_dev_ioread32(trans
->dev
, ofs
, val
);
102 IWL_EXPORT_SYMBOL(iwl_read32
);
104 #define IWL_POLL_INTERVAL 10 /* microseconds */
106 int iwl_poll_bit(struct iwl_trans
*trans
, u32 addr
,
107 u32 bits
, u32 mask
, int timeout
)
112 if ((iwl_read32(trans
, addr
) & mask
) == (bits
& mask
))
114 udelay(IWL_POLL_INTERVAL
);
115 t
+= IWL_POLL_INTERVAL
;
116 } while (t
< timeout
);
120 IWL_EXPORT_SYMBOL(iwl_poll_bit
);
122 u32
iwl_read_direct32(struct iwl_trans
*trans
, u32 reg
)
124 u32 value
= 0x5a5a5a5a;
126 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
127 value
= iwl_read32(trans
, reg
);
128 iwl_trans_release_nic_access(trans
, &flags
);
133 IWL_EXPORT_SYMBOL(iwl_read_direct32
);
135 void iwl_write_direct32(struct iwl_trans
*trans
, u32 reg
, u32 value
)
139 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
140 iwl_write32(trans
, reg
, value
);
141 iwl_trans_release_nic_access(trans
, &flags
);
144 IWL_EXPORT_SYMBOL(iwl_write_direct32
);
146 void iwl_write_direct64(struct iwl_trans
*trans
, u64 reg
, u64 value
)
150 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
151 iwl_write64(trans
, reg
, value
);
152 iwl_trans_release_nic_access(trans
, &flags
);
155 IWL_EXPORT_SYMBOL(iwl_write_direct64
);
157 int iwl_poll_direct_bit(struct iwl_trans
*trans
, u32 addr
, u32 mask
,
163 if ((iwl_read_direct32(trans
, addr
) & mask
) == mask
)
165 udelay(IWL_POLL_INTERVAL
);
166 t
+= IWL_POLL_INTERVAL
;
167 } while (t
< timeout
);
171 IWL_EXPORT_SYMBOL(iwl_poll_direct_bit
);
173 u32
iwl_read_prph_no_grab(struct iwl_trans
*trans
, u32 ofs
)
175 u32 val
= iwl_trans_read_prph(trans
, ofs
);
176 trace_iwlwifi_dev_ioread_prph32(trans
->dev
, ofs
, val
);
179 IWL_EXPORT_SYMBOL(iwl_read_prph_no_grab
);
181 void iwl_write_prph_no_grab(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
183 trace_iwlwifi_dev_iowrite_prph32(trans
->dev
, ofs
, val
);
184 iwl_trans_write_prph(trans
, ofs
, val
);
186 IWL_EXPORT_SYMBOL(iwl_write_prph_no_grab
);
188 void iwl_write_prph64_no_grab(struct iwl_trans
*trans
, u64 ofs
, u64 val
)
190 trace_iwlwifi_dev_iowrite_prph64(trans
->dev
, ofs
, val
);
191 iwl_write_prph_no_grab(trans
, ofs
, val
& 0xffffffff);
192 iwl_write_prph_no_grab(trans
, ofs
+ 4, val
>> 32);
194 IWL_EXPORT_SYMBOL(iwl_write_prph64_no_grab
);
196 u32
iwl_read_prph(struct iwl_trans
*trans
, u32 ofs
)
199 u32 val
= 0x5a5a5a5a;
201 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
202 val
= iwl_read_prph_no_grab(trans
, ofs
);
203 iwl_trans_release_nic_access(trans
, &flags
);
207 IWL_EXPORT_SYMBOL(iwl_read_prph
);
209 void iwl_write_prph(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
213 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
214 iwl_write_prph_no_grab(trans
, ofs
, val
);
215 iwl_trans_release_nic_access(trans
, &flags
);
218 IWL_EXPORT_SYMBOL(iwl_write_prph
);
220 int iwl_poll_prph_bit(struct iwl_trans
*trans
, u32 addr
,
221 u32 bits
, u32 mask
, int timeout
)
226 if ((iwl_read_prph(trans
, addr
) & mask
) == (bits
& mask
))
228 udelay(IWL_POLL_INTERVAL
);
229 t
+= IWL_POLL_INTERVAL
;
230 } while (t
< timeout
);
235 void iwl_set_bits_prph(struct iwl_trans
*trans
, u32 ofs
, u32 mask
)
239 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
240 iwl_write_prph_no_grab(trans
, ofs
,
241 iwl_read_prph_no_grab(trans
, ofs
) |
243 iwl_trans_release_nic_access(trans
, &flags
);
246 IWL_EXPORT_SYMBOL(iwl_set_bits_prph
);
248 void iwl_set_bits_mask_prph(struct iwl_trans
*trans
, u32 ofs
,
253 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
254 iwl_write_prph_no_grab(trans
, ofs
,
255 (iwl_read_prph_no_grab(trans
, ofs
) &
257 iwl_trans_release_nic_access(trans
, &flags
);
260 IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph
);
262 void iwl_clear_bits_prph(struct iwl_trans
*trans
, u32 ofs
, u32 mask
)
267 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
268 val
= iwl_read_prph_no_grab(trans
, ofs
);
269 iwl_write_prph_no_grab(trans
, ofs
, (val
& ~mask
));
270 iwl_trans_release_nic_access(trans
, &flags
);
273 IWL_EXPORT_SYMBOL(iwl_clear_bits_prph
);
275 void iwl_force_nmi(struct iwl_trans
*trans
)
277 if (trans
->trans_cfg
->device_family
< IWL_DEVICE_FAMILY_9000
)
278 iwl_write_prph(trans
, DEVICE_SET_NMI_REG
,
279 DEVICE_SET_NMI_VAL_DRV
);
280 else if (trans
->trans_cfg
->device_family
< IWL_DEVICE_FAMILY_AX210
)
281 iwl_write_umac_prph(trans
, UREG_NIC_SET_NMI_DRIVER
,
282 UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER_MSK
);
284 iwl_write_umac_prph(trans
, UREG_DOORBELL_TO_ISR6
,
285 UREG_DOORBELL_TO_ISR6_NMI_BIT
);
287 IWL_EXPORT_SYMBOL(iwl_force_nmi
);
289 static const char *get_rfh_string(int cmd
)
291 #define IWL_CMD(x) case x: return #x
292 #define IWL_CMD_MQ(arg, reg, q) { if (arg == reg(q)) return #reg; }
296 for (i
= 0; i
< IWL_MAX_RX_HW_QUEUES
; i
++) {
297 IWL_CMD_MQ(cmd
, RFH_Q_FRBDCB_BA_LSB
, i
);
298 IWL_CMD_MQ(cmd
, RFH_Q_FRBDCB_WIDX
, i
);
299 IWL_CMD_MQ(cmd
, RFH_Q_FRBDCB_RIDX
, i
);
300 IWL_CMD_MQ(cmd
, RFH_Q_URBD_STTS_WPTR_LSB
, i
);
304 IWL_CMD(RFH_RXF_DMA_CFG
);
305 IWL_CMD(RFH_GEN_CFG
);
306 IWL_CMD(RFH_GEN_STATUS
);
307 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
308 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
320 static int iwl_dump_rfh(struct iwl_trans
*trans
, char **buf
)
323 int num_q
= trans
->num_rx_queues
;
324 static const u32 rfh_tbl
[] = {
328 FH_TSSR_TX_STATUS_REG
,
329 FH_TSSR_TX_ERROR_REG
,
331 static const struct reg rfh_mq_tbl
[] = {
332 { RFH_Q0_FRBDCB_BA_LSB
, true },
333 { RFH_Q0_FRBDCB_WIDX
, false },
334 { RFH_Q0_FRBDCB_RIDX
, false },
335 { RFH_Q0_URBD_STTS_WPTR_LSB
, true },
338 #ifdef CONFIG_IWLWIFI_DEBUGFS
342 * Register (up to 34 for name + 8 blank/q for MQ): 40 chars
343 * Colon + space: 2 characters
344 * 0X%08x: 10 characters
345 * New line: 1 character
346 * Total of 53 characters
348 size_t bufsz
= ARRAY_SIZE(rfh_tbl
) * 53 +
349 ARRAY_SIZE(rfh_mq_tbl
) * 53 * num_q
+ 40;
351 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
355 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
356 "RFH register values:\n");
358 for (i
= 0; i
< ARRAY_SIZE(rfh_tbl
); i
++)
359 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
361 get_rfh_string(rfh_tbl
[i
]),
362 iwl_read_prph(trans
, rfh_tbl
[i
]));
364 for (i
= 0; i
< ARRAY_SIZE(rfh_mq_tbl
); i
++)
365 for (q
= 0; q
< num_q
; q
++) {
366 u32 addr
= rfh_mq_tbl
[i
].addr
;
368 addr
+= q
* (rfh_mq_tbl
[i
].is64
? 8 : 4);
369 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
370 "%34s(q %2d): 0X%08x\n",
371 get_rfh_string(addr
), q
,
372 iwl_read_prph(trans
, addr
));
379 IWL_ERR(trans
, "RFH register values:\n");
380 for (i
= 0; i
< ARRAY_SIZE(rfh_tbl
); i
++)
381 IWL_ERR(trans
, " %34s: 0X%08x\n",
382 get_rfh_string(rfh_tbl
[i
]),
383 iwl_read_prph(trans
, rfh_tbl
[i
]));
385 for (i
= 0; i
< ARRAY_SIZE(rfh_mq_tbl
); i
++)
386 for (q
= 0; q
< num_q
; q
++) {
387 u32 addr
= rfh_mq_tbl
[i
].addr
;
389 addr
+= q
* (rfh_mq_tbl
[i
].is64
? 8 : 4);
390 IWL_ERR(trans
, " %34s(q %d): 0X%08x\n",
391 get_rfh_string(addr
), q
,
392 iwl_read_prph(trans
, addr
));
398 static const char *get_fh_string(int cmd
)
401 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG
);
402 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG
);
403 IWL_CMD(FH_RSCSR_CHNL0_WPTR
);
404 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG
);
405 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG
);
406 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG
);
407 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
);
408 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
409 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
416 int iwl_dump_fh(struct iwl_trans
*trans
, char **buf
)
419 static const u32 fh_tbl
[] = {
420 FH_RSCSR_CHNL0_STTS_WPTR_REG
,
421 FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
423 FH_MEM_RCSR_CHNL0_CONFIG_REG
,
424 FH_MEM_RSSR_SHARED_CTRL_REG
,
425 FH_MEM_RSSR_RX_STATUS_REG
,
426 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
,
427 FH_TSSR_TX_STATUS_REG
,
431 if (trans
->trans_cfg
->mq_rx_supported
)
432 return iwl_dump_rfh(trans
, buf
);
434 #ifdef CONFIG_IWLWIFI_DEBUGFS
437 size_t bufsz
= ARRAY_SIZE(fh_tbl
) * 48 + 40;
439 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
443 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
444 "FH register values:\n");
446 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++)
447 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
449 get_fh_string(fh_tbl
[i
]),
450 iwl_read_direct32(trans
, fh_tbl
[i
]));
456 IWL_ERR(trans
, "FH register values:\n");
457 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++)
458 IWL_ERR(trans
, " %34s: 0X%08x\n",
459 get_fh_string(fh_tbl
[i
]),
460 iwl_read_direct32(trans
, fh_tbl
[i
]));
465 int iwl_finish_nic_init(struct iwl_trans
*trans
,
466 const struct iwl_cfg_trans_params
*cfg_trans
)
470 if (cfg_trans
->bisr_workaround
) {
471 /* ensure the TOP FSM isn't still in previous reset */
476 * Set "initialization complete" bit to move adapter from
477 * D0U* --> D0A* (powered-up active) state.
479 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
481 if (cfg_trans
->device_family
== IWL_DEVICE_FAMILY_8000
)
485 * Wait for clock stabilization; once stabilized, access to
486 * device-internal resources is supported, e.g. iwl_write_prph()
487 * and accesses to uCode SRAM.
489 err
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
490 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
491 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
494 IWL_DEBUG_INFO(trans
, "Failed to wake NIC\n");
496 if (cfg_trans
->bisr_workaround
) {
497 /* ensure BISR shift has finished */
501 return err
< 0 ? err
: 0;
503 IWL_EXPORT_SYMBOL(iwl_finish_nic_init
);