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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / wireless / realtek / rtw88 / main.h
blobc6b590fdb573b459d013fb85380ae028fb55ca5e
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTK_MAIN_H_
6 #define __RTK_MAIN_H_
7
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/interrupt.h>
15
16 #include "util.h"
17
18 #define RTW_MAX_MAC_ID_NUM 32
19 #define RTW_MAX_SEC_CAM_NUM 32
20 #define MAX_PG_CAM_BACKUP_NUM 8
21
22 #define RTW_MAX_PATTERN_NUM 12
23 #define RTW_MAX_PATTERN_MASK_SIZE 16
24 #define RTW_MAX_PATTERN_SIZE 128
25
26 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
27
28 #define RFREG_MASK 0xfffff
29 #define INV_RF_DATA 0xffffffff
30 #define TX_PAGE_SIZE_SHIFT 7
31
32 #define RTW_CHANNEL_WIDTH_MAX 3
33 #define RTW_RF_PATH_MAX 4
34 #define HW_FEATURE_LEN 13
35
36 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
37
38 extern bool rtw_bf_support;
39 extern unsigned int rtw_fw_lps_deep_mode;
40 extern unsigned int rtw_debug_mask;
41 extern const struct ieee80211_ops rtw_ops;
42 extern struct rtw_chip_info rtw8822b_hw_spec;
43 extern struct rtw_chip_info rtw8822c_hw_spec;
44
45 #define RTW_MAX_CHANNEL_NUM_2G 14
46 #define RTW_MAX_CHANNEL_NUM_5G 49
47
48 struct rtw_dev;
49
50 enum rtw_hci_type {
51 RTW_HCI_TYPE_PCIE,
52 RTW_HCI_TYPE_USB,
53 RTW_HCI_TYPE_SDIO,
54
55 RTW_HCI_TYPE_UNDEFINE,
56 };
57
58 struct rtw_hci {
59 struct rtw_hci_ops *ops;
60 enum rtw_hci_type type;
61
62 u32 rpwm_addr;
63 u32 cpwm_addr;
64
65 u8 bulkout_num;
66 };
67
68 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
69 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
70 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
71 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
72
73 #define IS_CH_5G_BAND_MID(channel) \
74 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
75
76 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
77 #define IS_CH_5G_BAND(channel) \
78 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
79 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
80
81 enum rtw_supported_band {
82 RTW_BAND_2G = 1 << 0,
83 RTW_BAND_5G = 1 << 1,
84 RTW_BAND_60G = 1 << 2,
85
86 RTW_BAND_MAX,
87 };
88
89 /* now, support upto 80M bw */
90 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
91
92 enum rtw_bandwidth {
93 RTW_CHANNEL_WIDTH_20 = 0,
94 RTW_CHANNEL_WIDTH_40 = 1,
95 RTW_CHANNEL_WIDTH_80 = 2,
96 RTW_CHANNEL_WIDTH_160 = 3,
97 RTW_CHANNEL_WIDTH_80_80 = 4,
98 RTW_CHANNEL_WIDTH_5 = 5,
99 RTW_CHANNEL_WIDTH_10 = 6,
100 };
101
102 enum rtw_sc_offset {
103 RTW_SC_DONT_CARE = 0,
104 RTW_SC_20_UPPER = 1,
105 RTW_SC_20_LOWER = 2,
106 RTW_SC_20_UPMOST = 3,
107 RTW_SC_20_LOWEST = 4,
108 RTW_SC_40_UPPER = 9,
109 RTW_SC_40_LOWER = 10,
110 };
111
112 enum rtw_net_type {
113 RTW_NET_NO_LINK = 0,
114 RTW_NET_AD_HOC = 1,
115 RTW_NET_MGD_LINKED = 2,
116 RTW_NET_AP_MODE = 3,
117 };
118
119 enum rtw_rf_type {
120 RF_1T1R = 0,
121 RF_1T2R = 1,
122 RF_2T2R = 2,
123 RF_2T3R = 3,
124 RF_2T4R = 4,
125 RF_3T3R = 5,
126 RF_3T4R = 6,
127 RF_4T4R = 7,
128 RF_TYPE_MAX,
129 };
130
131 enum rtw_rf_path {
132 RF_PATH_A = 0,
133 RF_PATH_B = 1,
134 RF_PATH_C = 2,
135 RF_PATH_D = 3,
136 };
137
138 enum rtw_bb_path {
139 BB_PATH_A = BIT(0),
140 BB_PATH_B = BIT(1),
141 BB_PATH_C = BIT(2),
142 BB_PATH_D = BIT(3),
143
144 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
145 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
146 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
147 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
148 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
149 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
150
151 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
152 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
153 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
154 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
155
156 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
157 };
158
159 enum rtw_rate_section {
160 RTW_RATE_SECTION_CCK = 0,
161 RTW_RATE_SECTION_OFDM,
162 RTW_RATE_SECTION_HT_1S,
163 RTW_RATE_SECTION_HT_2S,
164 RTW_RATE_SECTION_VHT_1S,
165 RTW_RATE_SECTION_VHT_2S,
166
167 /* keep last */
168 RTW_RATE_SECTION_MAX,
169 };
170
171 enum rtw_wireless_set {
172 WIRELESS_CCK = 0x00000001,
173 WIRELESS_OFDM = 0x00000002,
174 WIRELESS_HT = 0x00000004,
175 WIRELESS_VHT = 0x00000008,
176 };
177
178 #define HT_STBC_EN BIT(0)
179 #define VHT_STBC_EN BIT(1)
180 #define HT_LDPC_EN BIT(0)
181 #define VHT_LDPC_EN BIT(1)
182
183 enum rtw_chip_type {
184 RTW_CHIP_TYPE_8822B,
185 RTW_CHIP_TYPE_8822C,
186 };
187
188 enum rtw_tx_queue_type {
189 /* the order of AC queues matters */
190 RTW_TX_QUEUE_BK = 0x0,
191 RTW_TX_QUEUE_BE = 0x1,
192 RTW_TX_QUEUE_VI = 0x2,
193 RTW_TX_QUEUE_VO = 0x3,
194
195 RTW_TX_QUEUE_BCN = 0x4,
196 RTW_TX_QUEUE_MGMT = 0x5,
197 RTW_TX_QUEUE_HI0 = 0x6,
198 RTW_TX_QUEUE_H2C = 0x7,
199 /* keep it last */
200 RTK_MAX_TX_QUEUE_NUM
201 };
202
203 enum rtw_rx_queue_type {
204 RTW_RX_QUEUE_MPDU = 0x0,
205 RTW_RX_QUEUE_C2H = 0x1,
206 /* keep it last */
207 RTK_MAX_RX_QUEUE_NUM
208 };
209
210 enum rtw_fw_type {
211 RTW_NORMAL_FW = 0x0,
212 RTW_WOWLAN_FW = 0x1,
213 };
214
215 enum rtw_rate_index {
216 RTW_RATEID_BGN_40M_2SS = 0,
217 RTW_RATEID_BGN_40M_1SS = 1,
218 RTW_RATEID_BGN_20M_2SS = 2,
219 RTW_RATEID_BGN_20M_1SS = 3,
220 RTW_RATEID_GN_N2SS = 4,
221 RTW_RATEID_GN_N1SS = 5,
222 RTW_RATEID_BG = 6,
223 RTW_RATEID_G = 7,
224 RTW_RATEID_B_20M = 8,
225 RTW_RATEID_ARFR0_AC_2SS = 9,
226 RTW_RATEID_ARFR1_AC_1SS = 10,
227 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
228 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
229 RTW_RATEID_ARFR4_AC_3SS = 13,
230 RTW_RATEID_ARFR5_N_3SS = 14,
231 RTW_RATEID_ARFR7_N_4SS = 15,
232 RTW_RATEID_ARFR6_AC_4SS = 16
233 };
234
235 enum rtw_trx_desc_rate {
236 DESC_RATE1M = 0x00,
237 DESC_RATE2M = 0x01,
238 DESC_RATE5_5M = 0x02,
239 DESC_RATE11M = 0x03,
240
241 DESC_RATE6M = 0x04,
242 DESC_RATE9M = 0x05,
243 DESC_RATE12M = 0x06,
244 DESC_RATE18M = 0x07,
245 DESC_RATE24M = 0x08,
246 DESC_RATE36M = 0x09,
247 DESC_RATE48M = 0x0a,
248 DESC_RATE54M = 0x0b,
249
250 DESC_RATEMCS0 = 0x0c,
251 DESC_RATEMCS1 = 0x0d,
252 DESC_RATEMCS2 = 0x0e,
253 DESC_RATEMCS3 = 0x0f,
254 DESC_RATEMCS4 = 0x10,
255 DESC_RATEMCS5 = 0x11,
256 DESC_RATEMCS6 = 0x12,
257 DESC_RATEMCS7 = 0x13,
258 DESC_RATEMCS8 = 0x14,
259 DESC_RATEMCS9 = 0x15,
260 DESC_RATEMCS10 = 0x16,
261 DESC_RATEMCS11 = 0x17,
262 DESC_RATEMCS12 = 0x18,
263 DESC_RATEMCS13 = 0x19,
264 DESC_RATEMCS14 = 0x1a,
265 DESC_RATEMCS15 = 0x1b,
266 DESC_RATEMCS16 = 0x1c,
267 DESC_RATEMCS17 = 0x1d,
268 DESC_RATEMCS18 = 0x1e,
269 DESC_RATEMCS19 = 0x1f,
270 DESC_RATEMCS20 = 0x20,
271 DESC_RATEMCS21 = 0x21,
272 DESC_RATEMCS22 = 0x22,
273 DESC_RATEMCS23 = 0x23,
274 DESC_RATEMCS24 = 0x24,
275 DESC_RATEMCS25 = 0x25,
276 DESC_RATEMCS26 = 0x26,
277 DESC_RATEMCS27 = 0x27,
278 DESC_RATEMCS28 = 0x28,
279 DESC_RATEMCS29 = 0x29,
280 DESC_RATEMCS30 = 0x2a,
281 DESC_RATEMCS31 = 0x2b,
282
283 DESC_RATEVHT1SS_MCS0 = 0x2c,
284 DESC_RATEVHT1SS_MCS1 = 0x2d,
285 DESC_RATEVHT1SS_MCS2 = 0x2e,
286 DESC_RATEVHT1SS_MCS3 = 0x2f,
287 DESC_RATEVHT1SS_MCS4 = 0x30,
288 DESC_RATEVHT1SS_MCS5 = 0x31,
289 DESC_RATEVHT1SS_MCS6 = 0x32,
290 DESC_RATEVHT1SS_MCS7 = 0x33,
291 DESC_RATEVHT1SS_MCS8 = 0x34,
292 DESC_RATEVHT1SS_MCS9 = 0x35,
293
294 DESC_RATEVHT2SS_MCS0 = 0x36,
295 DESC_RATEVHT2SS_MCS1 = 0x37,
296 DESC_RATEVHT2SS_MCS2 = 0x38,
297 DESC_RATEVHT2SS_MCS3 = 0x39,
298 DESC_RATEVHT2SS_MCS4 = 0x3a,
299 DESC_RATEVHT2SS_MCS5 = 0x3b,
300 DESC_RATEVHT2SS_MCS6 = 0x3c,
301 DESC_RATEVHT2SS_MCS7 = 0x3d,
302 DESC_RATEVHT2SS_MCS8 = 0x3e,
303 DESC_RATEVHT2SS_MCS9 = 0x3f,
304
305 DESC_RATEVHT3SS_MCS0 = 0x40,
306 DESC_RATEVHT3SS_MCS1 = 0x41,
307 DESC_RATEVHT3SS_MCS2 = 0x42,
308 DESC_RATEVHT3SS_MCS3 = 0x43,
309 DESC_RATEVHT3SS_MCS4 = 0x44,
310 DESC_RATEVHT3SS_MCS5 = 0x45,
311 DESC_RATEVHT3SS_MCS6 = 0x46,
312 DESC_RATEVHT3SS_MCS7 = 0x47,
313 DESC_RATEVHT3SS_MCS8 = 0x48,
314 DESC_RATEVHT3SS_MCS9 = 0x49,
315
316 DESC_RATEVHT4SS_MCS0 = 0x4a,
317 DESC_RATEVHT4SS_MCS1 = 0x4b,
318 DESC_RATEVHT4SS_MCS2 = 0x4c,
319 DESC_RATEVHT4SS_MCS3 = 0x4d,
320 DESC_RATEVHT4SS_MCS4 = 0x4e,
321 DESC_RATEVHT4SS_MCS5 = 0x4f,
322 DESC_RATEVHT4SS_MCS6 = 0x50,
323 DESC_RATEVHT4SS_MCS7 = 0x51,
324 DESC_RATEVHT4SS_MCS8 = 0x52,
325 DESC_RATEVHT4SS_MCS9 = 0x53,
326
327 DESC_RATE_MAX,
328 };
329
330 enum rtw_regulatory_domains {
331 RTW_REGD_FCC = 0,
332 RTW_REGD_MKK = 1,
333 RTW_REGD_ETSI = 2,
334 RTW_REGD_IC = 3,
335 RTW_REGD_KCC = 4,
336 RTW_REGD_ACMA = 5,
337 RTW_REGD_CHILE = 6,
338 RTW_REGD_UKRAINE = 7,
339 RTW_REGD_MEXICO = 8,
340 RTW_REGD_WW,
341
342 RTW_REGD_MAX
343 };
344
345 enum rtw_txq_flags {
346 RTW_TXQ_AMPDU,
347 RTW_TXQ_BLOCK_BA,
348 };
349
350 enum rtw_flags {
351 RTW_FLAG_RUNNING,
352 RTW_FLAG_FW_RUNNING,
353 RTW_FLAG_SCANNING,
354 RTW_FLAG_INACTIVE_PS,
355 RTW_FLAG_LEISURE_PS,
356 RTW_FLAG_LEISURE_PS_DEEP,
357 RTW_FLAG_DIG_DISABLE,
358 RTW_FLAG_BUSY_TRAFFIC,
359 RTW_FLAG_WOWLAN,
360
361 NUM_OF_RTW_FLAGS,
362 };
363
364 enum rtw_evm {
365 RTW_EVM_OFDM = 0,
366 RTW_EVM_1SS,
367 RTW_EVM_2SS_A,
368 RTW_EVM_2SS_B,
369 /* keep it last */
370 RTW_EVM_NUM
371 };
372
373 enum rtw_snr {
374 RTW_SNR_OFDM_A = 0,
375 RTW_SNR_OFDM_B,
376 RTW_SNR_OFDM_C,
377 RTW_SNR_OFDM_D,
378 RTW_SNR_1SS_A,
379 RTW_SNR_1SS_B,
380 RTW_SNR_1SS_C,
381 RTW_SNR_1SS_D,
382 RTW_SNR_2SS_A,
383 RTW_SNR_2SS_B,
384 RTW_SNR_2SS_C,
385 RTW_SNR_2SS_D,
386 /* keep it last */
387 RTW_SNR_NUM
388 };
389
390 enum rtw_wow_flags {
391 RTW_WOW_FLAG_EN_MAGIC_PKT,
392 RTW_WOW_FLAG_EN_REKEY_PKT,
393 RTW_WOW_FLAG_EN_DISCONNECT,
394
395 /* keep it last */
396 RTW_WOW_FLAG_MAX,
397 };
398
399 /* the power index is represented by differences, which cck-1s & ht40-1s are
400 * the base values, so for 1s's differences, there are only ht20 & ofdm
401 */
402 struct rtw_2g_1s_pwr_idx_diff {
403 #ifdef __LITTLE_ENDIAN
404 s8 ofdm:4;
405 s8 bw20:4;
406 #else
407 s8 bw20:4;
408 s8 ofdm:4;
409 #endif
410 } __packed;
411
412 struct rtw_2g_ns_pwr_idx_diff {
413 #ifdef __LITTLE_ENDIAN
414 s8 bw20:4;
415 s8 bw40:4;
416 s8 cck:4;
417 s8 ofdm:4;
418 #else
419 s8 ofdm:4;
420 s8 cck:4;
421 s8 bw40:4;
422 s8 bw20:4;
423 #endif
424 } __packed;
425
426 struct rtw_2g_txpwr_idx {
427 u8 cck_base[6];
428 u8 bw40_base[5];
429 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
430 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
431 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
432 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
433 };
434
435 struct rtw_5g_ht_1s_pwr_idx_diff {
436 #ifdef __LITTLE_ENDIAN
437 s8 ofdm:4;
438 s8 bw20:4;
439 #else
440 s8 bw20:4;
441 s8 ofdm:4;
442 #endif
443 } __packed;
444
445 struct rtw_5g_ht_ns_pwr_idx_diff {
446 #ifdef __LITTLE_ENDIAN
447 s8 bw20:4;
448 s8 bw40:4;
449 #else
450 s8 bw40:4;
451 s8 bw20:4;
452 #endif
453 } __packed;
454
455 struct rtw_5g_ofdm_ns_pwr_idx_diff {
456 #ifdef __LITTLE_ENDIAN
457 s8 ofdm_3s:4;
458 s8 ofdm_2s:4;
459 s8 ofdm_4s:4;
460 s8 res:4;
461 #else
462 s8 res:4;
463 s8 ofdm_4s:4;
464 s8 ofdm_2s:4;
465 s8 ofdm_3s:4;
466 #endif
467 } __packed;
468
469 struct rtw_5g_vht_ns_pwr_idx_diff {
470 #ifdef __LITTLE_ENDIAN
471 s8 bw160:4;
472 s8 bw80:4;
473 #else
474 s8 bw80:4;
475 s8 bw160:4;
476 #endif
477 } __packed;
478
479 struct rtw_5g_txpwr_idx {
480 u8 bw40_base[14];
481 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
482 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
483 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
484 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
485 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
486 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
487 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
488 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
489 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
490 };
491
492 struct rtw_txpwr_idx {
493 struct rtw_2g_txpwr_idx pwr_idx_2g;
494 struct rtw_5g_txpwr_idx pwr_idx_5g;
495 };
496
497 struct rtw_timer_list {
498 struct timer_list timer;
499 void (*function)(void *data);
500 void *args;
501 };
502
503 struct rtw_channel_params {
504 u8 center_chan;
505 u8 bandwidth;
506 u8 primary_chan_idx;
507 /* center channel by different available bandwidth,
508 * val of (bw > current bandwidth) is invalid
509 */
510 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
511 };
512
513 struct rtw_hw_reg {
514 u32 addr;
515 u32 mask;
516 };
517
518 struct rtw_reg_domain {
519 u32 addr;
520 u32 mask;
521 #define RTW_REG_DOMAIN_MAC32 0
522 #define RTW_REG_DOMAIN_MAC16 1
523 #define RTW_REG_DOMAIN_MAC8 2
524 #define RTW_REG_DOMAIN_RF_A 3
525 #define RTW_REG_DOMAIN_RF_B 4
526 #define RTW_REG_DOMAIN_NL 0xFF
527 u8 domain;
528 };
529
530 struct rtw_backup_info {
531 u8 len;
532 u32 reg;
533 u32 val;
534 };
535
536 enum rtw_vif_port_set {
537 PORT_SET_MAC_ADDR = BIT(0),
538 PORT_SET_BSSID = BIT(1),
539 PORT_SET_NET_TYPE = BIT(2),
540 PORT_SET_AID = BIT(3),
541 PORT_SET_BCN_CTRL = BIT(4),
542 };
543
544 struct rtw_vif_port {
545 struct rtw_hw_reg mac_addr;
546 struct rtw_hw_reg bssid;
547 struct rtw_hw_reg net_type;
548 struct rtw_hw_reg aid;
549 struct rtw_hw_reg bcn_ctrl;
550 };
551
552 struct rtw_tx_pkt_info {
553 u32 tx_pkt_size;
554 u8 offset;
555 u8 pkt_offset;
556 u8 mac_id;
557 u8 rate_id;
558 u8 rate;
559 u8 qsel;
560 u8 bw;
561 u8 sec_type;
562 u8 sn;
563 bool ampdu_en;
564 u8 ampdu_factor;
565 u8 ampdu_density;
566 u16 seq;
567 bool stbc;
568 bool ldpc;
569 bool dis_rate_fallback;
570 bool bmc;
571 bool use_rate;
572 bool ls;
573 bool fs;
574 bool short_gi;
575 bool report;
576 bool rts;
577 bool dis_qselseq;
578 bool en_hwseq;
579 u8 hw_ssn_sel;
580 };
581
582 struct rtw_rx_pkt_stat {
583 bool phy_status;
584 bool icv_err;
585 bool crc_err;
586 bool decrypted;
587 bool is_c2h;
588
589 s32 signal_power;
590 u16 pkt_len;
591 u8 bw;
592 u8 drv_info_sz;
593 u8 shift;
594 u8 rate;
595 u8 mac_id;
596 u8 cam_id;
597 u8 ppdu_cnt;
598 u32 tsf_low;
599 s8 rx_power[RTW_RF_PATH_MAX];
600 u8 rssi;
601 u8 rxsc;
602 s8 rx_snr[RTW_RF_PATH_MAX];
603 u8 rx_evm[RTW_RF_PATH_MAX];
604 s8 cfo_tail[RTW_RF_PATH_MAX];
605
606 struct rtw_sta_info *si;
607 struct ieee80211_vif *vif;
608 };
609
610 DECLARE_EWMA(tp, 10, 2);
611
612 struct rtw_traffic_stats {
613 /* units in bytes */
614 u64 tx_unicast;
615 u64 rx_unicast;
616
617 /* count for packets */
618 u64 tx_cnt;
619 u64 rx_cnt;
620
621 /* units in Mbps */
622 u32 tx_throughput;
623 u32 rx_throughput;
624 struct ewma_tp tx_ewma_tp;
625 struct ewma_tp rx_ewma_tp;
626 };
627
628 enum rtw_lps_mode {
629 RTW_MODE_ACTIVE = 0,
630 RTW_MODE_LPS = 1,
631 RTW_MODE_WMM_PS = 2,
632 };
633
634 enum rtw_lps_deep_mode {
635 LPS_DEEP_MODE_NONE = 0,
636 LPS_DEEP_MODE_LCLK = 1,
637 LPS_DEEP_MODE_PG = 2,
638 };
639
640 enum rtw_pwr_state {
641 RTW_RF_OFF = 0x0,
642 RTW_RF_ON = 0x4,
643 RTW_ALL_ON = 0xc,
644 };
645
646 struct rtw_lps_conf {
647 enum rtw_lps_mode mode;
648 enum rtw_lps_deep_mode deep_mode;
649 enum rtw_pwr_state state;
650 u8 awake_interval;
651 u8 rlbm;
652 u8 smart_ps;
653 u8 port_id;
654 bool sec_cam_backup;
655 bool pattern_cam_backup;
656 };
657
658 enum rtw_hw_key_type {
659 RTW_CAM_NONE = 0,
660 RTW_CAM_WEP40 = 1,
661 RTW_CAM_TKIP = 2,
662 RTW_CAM_AES = 4,
663 RTW_CAM_WEP104 = 5,
664 };
665
666 struct rtw_cam_entry {
667 bool valid;
668 bool group;
669 u8 addr[ETH_ALEN];
670 u8 hw_key_type;
671 struct ieee80211_key_conf *key;
672 };
673
674 struct rtw_sec_desc {
675 /* search strategy */
676 bool default_key_search;
677
678 u32 total_cam_num;
679 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
680 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
681 };
682
683 struct rtw_tx_report {
684 /* protect the tx report queue */
685 spinlock_t q_lock;
686 struct sk_buff_head queue;
687 atomic_t sn;
688 struct timer_list purge_timer;
689 };
690
691 struct rtw_ra_report {
692 struct rate_info txrate;
693 u32 bit_rate;
694 u8 desc_rate;
695 };
696
697 struct rtw_txq {
698 struct list_head list;
699
700 unsigned long flags;
701 unsigned long last_push;
702 };
703
704 #define RTW_BC_MC_MACID 1
705 DECLARE_EWMA(rssi, 10, 16);
706
707 struct rtw_sta_info {
708 struct ieee80211_sta *sta;
709 struct ieee80211_vif *vif;
710
711 struct ewma_rssi avg_rssi;
712 u8 rssi_level;
713
714 u8 mac_id;
715 u8 rate_id;
716 enum rtw_bandwidth bw_mode;
717 enum rtw_rf_type rf_type;
718 enum rtw_wireless_set wireless_set;
719 u8 stbc_en:2;
720 u8 ldpc_en:2;
721 bool sgi_enable;
722 bool vht_enable;
723 bool updated;
724 u8 init_ra_lv;
725 u64 ra_mask;
726
727 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
728
729 struct rtw_ra_report ra_report;
730
731 bool use_cfg_mask;
732 struct cfg80211_bitrate_mask *mask;
733 };
734
735 enum rtw_bfee_role {
736 RTW_BFEE_NONE,
737 RTW_BFEE_SU,
738 RTW_BFEE_MU
739 };
740
741 struct rtw_bfee {
742 enum rtw_bfee_role role;
743
744 u16 p_aid;
745 u8 g_id;
746 u8 mac_addr[ETH_ALEN];
747 u8 sound_dim;
748
749 /* SU-MIMO */
750 u8 su_reg_index;
751
752 /* MU-MIMO */
753 u16 aid;
754 };
755
756 struct rtw_bf_info {
757 u8 bfer_mu_cnt;
758 u8 bfer_su_cnt;
759 DECLARE_BITMAP(bfer_su_reg_maping, 2);
760 u8 cur_csi_rpt_rate;
761 };
762
763 struct rtw_vif {
764 enum rtw_net_type net_type;
765 u16 aid;
766 u8 mac_addr[ETH_ALEN];
767 u8 bssid[ETH_ALEN];
768 u8 port;
769 u8 bcn_ctrl;
770 struct list_head rsvd_page_list;
771 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
772 const struct rtw_vif_port *conf;
773
774 struct rtw_traffic_stats stats;
775
776 struct rtw_bfee bfee;
777 };
778
779 struct rtw_regulatory {
780 char alpha2[2];
781 u8 chplan;
782 u8 txpwr_regd;
783 };
784
785 struct rtw_chip_ops {
786 int (*mac_init)(struct rtw_dev *rtwdev);
787 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
788 void (*phy_set_param)(struct rtw_dev *rtwdev);
789 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
790 u8 bandwidth, u8 primary_chan_idx);
791 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
792 struct rtw_rx_pkt_stat *pkt_stat,
793 struct ieee80211_rx_status *rx_status);
794 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
795 u32 addr, u32 mask);
796 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
797 u32 addr, u32 mask, u32 data);
798 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
799 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
800 u32 size);
801 void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx,
802 u8 antenna_rx);
803 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
804 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
805 void (*phy_calibration)(struct rtw_dev *rtwdev);
806 void (*dpk_track)(struct rtw_dev *rtwdev);
807 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
808 void (*pwr_track)(struct rtw_dev *rtwdev);
809 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
810 struct rtw_bfee *bfee, bool enable);
811 void (*set_gid_table)(struct rtw_dev *rtwdev,
812 struct ieee80211_vif *vif,
813 struct ieee80211_bss_conf *conf);
814 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
815 u8 fixrate_en, u8 *new_rate);
816
817 /* for coex */
818 void (*coex_set_init)(struct rtw_dev *rtwdev);
819 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
820 u8 ctrl_type, u8 pos_type);
821 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
822 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
823 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
824 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
825 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
826 };
827
828 #define RTW_PWR_POLLING_CNT 20000
829
830 #define RTW_PWR_CMD_READ 0x00
831 #define RTW_PWR_CMD_WRITE 0x01
832 #define RTW_PWR_CMD_POLLING 0x02
833 #define RTW_PWR_CMD_DELAY 0x03
834 #define RTW_PWR_CMD_END 0x04
835
836 /* define the base address of each block */
837 #define RTW_PWR_ADDR_MAC 0x00
838 #define RTW_PWR_ADDR_USB 0x01
839 #define RTW_PWR_ADDR_PCIE 0x02
840 #define RTW_PWR_ADDR_SDIO 0x03
841
842 #define RTW_PWR_INTF_SDIO_MSK BIT(0)
843 #define RTW_PWR_INTF_USB_MSK BIT(1)
844 #define RTW_PWR_INTF_PCI_MSK BIT(2)
845 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
846
847 #define RTW_PWR_CUT_A_MSK BIT(1)
848 #define RTW_PWR_CUT_B_MSK BIT(2)
849 #define RTW_PWR_CUT_C_MSK BIT(3)
850 #define RTW_PWR_CUT_D_MSK BIT(4)
851 #define RTW_PWR_CUT_E_MSK BIT(5)
852 #define RTW_PWR_CUT_F_MSK BIT(6)
853 #define RTW_PWR_CUT_G_MSK BIT(7)
854 #define RTW_PWR_CUT_ALL_MSK 0xFF
855
856 enum rtw_pwr_seq_cmd_delay_unit {
857 RTW_PWR_DELAY_US,
858 RTW_PWR_DELAY_MS,
859 };
860
861 struct rtw_pwr_seq_cmd {
862 u16 offset;
863 u8 cut_mask;
864 u8 intf_mask;
865 u8 base:4;
866 u8 cmd:4;
867 u8 mask;
868 u8 value;
869 };
870
871 enum rtw_chip_ver {
872 RTW_CHIP_VER_CUT_A = 0x00,
873 RTW_CHIP_VER_CUT_B = 0x01,
874 RTW_CHIP_VER_CUT_C = 0x02,
875 RTW_CHIP_VER_CUT_D = 0x03,
876 RTW_CHIP_VER_CUT_E = 0x04,
877 RTW_CHIP_VER_CUT_F = 0x05,
878 RTW_CHIP_VER_CUT_G = 0x06,
879 };
880
881 #define RTW_INTF_PHY_PLATFORM_ALL 0
882
883 enum rtw_intf_phy_cut {
884 RTW_INTF_PHY_CUT_A = BIT(0),
885 RTW_INTF_PHY_CUT_B = BIT(1),
886 RTW_INTF_PHY_CUT_C = BIT(2),
887 RTW_INTF_PHY_CUT_D = BIT(3),
888 RTW_INTF_PHY_CUT_E = BIT(4),
889 RTW_INTF_PHY_CUT_F = BIT(5),
890 RTW_INTF_PHY_CUT_G = BIT(6),
891 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
892 };
893
894 enum rtw_ip_sel {
895 RTW_IP_SEL_PHY = 0,
896 RTW_IP_SEL_MAC = 1,
897 RTW_IP_SEL_DBI = 2,
898
899 RTW_IP_SEL_UNDEF = 0xFFFF
900 };
901
902 enum rtw_pq_map_id {
903 RTW_PQ_MAP_VO = 0x0,
904 RTW_PQ_MAP_VI = 0x1,
905 RTW_PQ_MAP_BE = 0x2,
906 RTW_PQ_MAP_BK = 0x3,
907 RTW_PQ_MAP_MG = 0x4,
908 RTW_PQ_MAP_HI = 0x5,
909 RTW_PQ_MAP_NUM = 0x6,
910
911 RTW_PQ_MAP_UNDEF,
912 };
913
914 enum rtw_dma_mapping {
915 RTW_DMA_MAPPING_EXTRA = 0,
916 RTW_DMA_MAPPING_LOW = 1,
917 RTW_DMA_MAPPING_NORMAL = 2,
918 RTW_DMA_MAPPING_HIGH = 3,
919
920 RTW_DMA_MAPPING_MAX,
921 RTW_DMA_MAPPING_UNDEF,
922 };
923
924 struct rtw_rqpn {
925 enum rtw_dma_mapping dma_map_vo;
926 enum rtw_dma_mapping dma_map_vi;
927 enum rtw_dma_mapping dma_map_be;
928 enum rtw_dma_mapping dma_map_bk;
929 enum rtw_dma_mapping dma_map_mg;
930 enum rtw_dma_mapping dma_map_hi;
931 };
932
933 struct rtw_page_table {
934 u16 hq_num;
935 u16 nq_num;
936 u16 lq_num;
937 u16 exq_num;
938 u16 gapq_num;
939 };
940
941 struct rtw_intf_phy_para {
942 u16 offset;
943 u16 value;
944 u16 ip_sel;
945 u16 cut_mask;
946 u16 platform;
947 };
948
949 struct rtw_wow_pattern {
950 u16 crc;
951 u8 type;
952 u8 valid;
953 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
954 };
955
956 struct rtw_pno_request {
957 bool inited;
958 u32 match_set_cnt;
959 struct cfg80211_match_set *match_sets;
960 u8 channel_cnt;
961 struct ieee80211_channel *channels;
962 struct cfg80211_sched_scan_plan scan_plan;
963 };
964
965 struct rtw_wow_param {
966 struct ieee80211_vif *wow_vif;
967 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
968 u8 txpause;
969 u8 pattern_cnt;
970 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
971
972 bool ips_enabled;
973 struct rtw_pno_request pno_req;
974 };
975
976 struct rtw_intf_phy_para_table {
977 const struct rtw_intf_phy_para *usb2_para;
978 const struct rtw_intf_phy_para *usb3_para;
979 const struct rtw_intf_phy_para *gen1_para;
980 const struct rtw_intf_phy_para *gen2_para;
981 u8 n_usb2_para;
982 u8 n_usb3_para;
983 u8 n_gen1_para;
984 u8 n_gen2_para;
985 };
986
987 struct rtw_table {
988 const void *data;
989 const u32 size;
990 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
991 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
992 u32 addr, u32 data);
993 enum rtw_rf_path rf_path;
994 };
995
996 static inline void rtw_load_table(struct rtw_dev *rtwdev,
997 const struct rtw_table *tbl)
998 {
999 (*tbl->parse)(rtwdev, tbl);
1000 }
1001
1002 enum rtw_rfe_fem {
1003 RTW_RFE_IFEM,
1004 RTW_RFE_EFEM,
1005 RTW_RFE_IFEM2G_EFEM5G,
1006 RTW_RFE_NUM,
1007 };
1008
1009 struct rtw_rfe_def {
1010 const struct rtw_table *phy_pg_tbl;
1011 const struct rtw_table *txpwr_lmt_tbl;
1012 };
1013
1014 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
1015 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1016 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1017 }
1018
1019 #define RTW_PWR_TRK_5G_1 0
1020 #define RTW_PWR_TRK_5G_2 1
1021 #define RTW_PWR_TRK_5G_3 2
1022 #define RTW_PWR_TRK_5G_NUM 3
1023
1024 #define RTW_PWR_TRK_TBL_SZ 30
1025
1026 /* This table stores the values of TX power that will be adjusted by power
1027 * tracking.
1028 *
1029 * For 5G bands, there are 3 different settings.
1030 * For 2G there are cck rate and ofdm rate with different settings.
1031 */
1032 struct rtw_pwr_track_tbl {
1033 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1034 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1035 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1036 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1037 const u8 *pwrtrk_2gb_n;
1038 const u8 *pwrtrk_2gb_p;
1039 const u8 *pwrtrk_2ga_n;
1040 const u8 *pwrtrk_2ga_p;
1041 const u8 *pwrtrk_2g_cckb_n;
1042 const u8 *pwrtrk_2g_cckb_p;
1043 const u8 *pwrtrk_2g_ccka_n;
1044 const u8 *pwrtrk_2g_ccka_p;
1045 };
1046
1047 /* hardware configuration for each IC */
1048 struct rtw_chip_info {
1049 struct rtw_chip_ops *ops;
1050 u8 id;
1051
1052 const char *fw_name;
1053 u8 tx_pkt_desc_sz;
1054 u8 tx_buf_desc_sz;
1055 u8 rx_pkt_desc_sz;
1056 u8 rx_buf_desc_sz;
1057 u32 phy_efuse_size;
1058 u32 log_efuse_size;
1059 u32 ptct_efuse_size;
1060 u32 txff_size;
1061 u32 rxff_size;
1062 u8 band;
1063 u8 page_size;
1064 u8 csi_buf_pg_num;
1065 u8 dig_max;
1066 u8 dig_min;
1067 u8 txgi_factor;
1068 bool is_pwr_by_rate_dec;
1069 u8 max_power_index;
1070
1071 bool ht_supported;
1072 bool vht_supported;
1073 u8 lps_deep_mode_supported;
1074
1075 /* init values */
1076 u8 sys_func_en;
1077 const struct rtw_pwr_seq_cmd **pwr_on_seq;
1078 const struct rtw_pwr_seq_cmd **pwr_off_seq;
1079 const struct rtw_rqpn *rqpn_table;
1080 const struct rtw_page_table *page_table;
1081 const struct rtw_intf_phy_para_table *intf_table;
1082
1083 const struct rtw_hw_reg *dig;
1084 u32 rf_base_addr[2];
1085 u32 rf_sipi_addr[2];
1086
1087 const struct rtw_table *mac_tbl;
1088 const struct rtw_table *agc_tbl;
1089 const struct rtw_table *bb_tbl;
1090 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1091 const struct rtw_table *rfk_init_tbl;
1092
1093 const struct rtw_rfe_def *rfe_defs;
1094 u32 rfe_defs_size;
1095
1096 bool en_dis_dpd;
1097 u16 dpd_ratemask;
1098 u8 iqk_threshold;
1099 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1100
1101 u8 bfer_su_max_num;
1102 u8 bfer_mu_max_num;
1103
1104 const char *wow_fw_name;
1105 const struct wiphy_wowlan_support *wowlan_stub;
1106 const u8 max_sched_scan_ssids;
1107
1108 /* coex paras */
1109 u32 coex_para_ver;
1110 u8 bt_desired_ver;
1111 bool scbd_support;
1112 bool new_scbd10_def; /* true: fix 2M(8822c) */
1113 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1114 u8 bt_rssi_type;
1115 u8 ant_isolation;
1116 u8 rssi_tolerance;
1117 u8 table_sant_num;
1118 u8 table_nsant_num;
1119 u8 tdma_sant_num;
1120 u8 tdma_nsant_num;
1121 u8 bt_afh_span_bw20;
1122 u8 bt_afh_span_bw40;
1123 u8 afh_5g_num;
1124 u8 wl_rf_para_num;
1125 u8 coex_info_hw_regs_num;
1126 const u8 *bt_rssi_step;
1127 const u8 *wl_rssi_step;
1128 const struct coex_table_para *table_nsant;
1129 const struct coex_table_para *table_sant;
1130 const struct coex_tdma_para *tdma_sant;
1131 const struct coex_tdma_para *tdma_nsant;
1132 const struct coex_rf_para *wl_rf_para_tx;
1133 const struct coex_rf_para *wl_rf_para_rx;
1134 const struct coex_5g_afh_map *afh_5g;
1135 const struct rtw_reg_domain *coex_info_hw_regs;
1136 };
1137
1138 enum rtw_coex_bt_state_cnt {
1139 COEX_CNT_BT_RETRY,
1140 COEX_CNT_BT_REINIT,
1141 COEX_CNT_BT_REENABLE,
1142 COEX_CNT_BT_POPEVENT,
1143 COEX_CNT_BT_SETUPLINK,
1144 COEX_CNT_BT_IGNWLANACT,
1145 COEX_CNT_BT_INQ,
1146 COEX_CNT_BT_PAGE,
1147 COEX_CNT_BT_ROLESWITCH,
1148 COEX_CNT_BT_AFHUPDATE,
1149 COEX_CNT_BT_INFOUPDATE,
1150 COEX_CNT_BT_IQK,
1151 COEX_CNT_BT_IQKFAIL,
1152
1153 COEX_CNT_BT_MAX
1154 };
1155
1156 enum rtw_coex_wl_state_cnt {
1157 COEX_CNT_WL_CONNPKT,
1158 COEX_CNT_WL_COEXRUN,
1159 COEX_CNT_WL_NOISY0,
1160 COEX_CNT_WL_NOISY1,
1161 COEX_CNT_WL_NOISY2,
1162 COEX_CNT_WL_5MS_NOEXTEND,
1163 COEX_CNT_WL_FW_NOTIFY,
1164
1165 COEX_CNT_WL_MAX
1166 };
1167
1168 struct rtw_coex_rfe {
1169 bool ant_switch_exist;
1170 bool ant_switch_diversity;
1171 bool ant_switch_with_bt;
1172 u8 rfe_module_type;
1173 u8 ant_switch_polarity;
1174
1175 /* true if WLG at BTG, else at WLAG */
1176 bool wlg_at_btg;
1177 };
1178
1179 struct rtw_coex_dm {
1180 bool cur_ps_tdma_on;
1181 bool cur_wl_rx_low_gain_en;
1182 bool ignore_wl_act;
1183
1184 u8 reason;
1185 u8 bt_rssi_state[4];
1186 u8 wl_rssi_state[4];
1187 u8 wl_ch_info[3];
1188 u8 cur_ps_tdma;
1189 u8 cur_table;
1190 u8 ps_tdma_para[5];
1191 u8 cur_bt_pwr_lvl;
1192 u8 cur_bt_lna_lvl;
1193 u8 cur_wl_pwr_lvl;
1194 u8 bt_status;
1195 u32 cur_ant_pos_type;
1196 u32 cur_switch_status;
1197 u32 setting_tdma;
1198 };
1199
1200 #define COEX_BTINFO_SRC_WL_FW 0x0
1201 #define COEX_BTINFO_SRC_BT_RSP 0x1
1202 #define COEX_BTINFO_SRC_BT_ACT 0x2
1203 #define COEX_BTINFO_SRC_BT_IQK 0x3
1204 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1205 #define COEX_BTINFO_SRC_MAX 0x5
1206
1207 #define COEX_INFO_FTP BIT(7)
1208 #define COEX_INFO_A2DP BIT(6)
1209 #define COEX_INFO_HID BIT(5)
1210 #define COEX_INFO_SCO_BUSY BIT(4)
1211 #define COEX_INFO_ACL_BUSY BIT(3)
1212 #define COEX_INFO_INQ_PAGE BIT(2)
1213 #define COEX_INFO_SCO_ESCO BIT(1)
1214 #define COEX_INFO_CONNECTION BIT(0)
1215 #define COEX_BTINFO_LENGTH_MAX 10
1216
1217 struct rtw_coex_stat {
1218 bool bt_disabled;
1219 bool bt_disabled_pre;
1220 bool bt_link_exist;
1221 bool bt_whck_test;
1222 bool bt_inq_page;
1223 bool bt_inq;
1224 bool bt_page;
1225 bool bt_ble_voice;
1226 bool bt_ble_exist;
1227 bool bt_hfp_exist;
1228 bool bt_a2dp_exist;
1229 bool bt_hid_exist;
1230 bool bt_pan_exist; /* PAN or OPP */
1231 bool bt_opp_exist; /* OPP only */
1232 bool bt_acl_busy;
1233 bool bt_fix_2M;
1234 bool bt_setup_link;
1235 bool bt_multi_link;
1236 bool bt_a2dp_sink;
1237 bool bt_a2dp_active;
1238 bool bt_reenable;
1239 bool bt_ble_scan_en;
1240 bool bt_init_scan;
1241 bool bt_slave;
1242 bool bt_418_hid_exist;
1243 bool bt_mailbox_reply;
1244
1245 bool wl_under_lps;
1246 bool wl_under_ips;
1247 bool wl_hi_pri_task1;
1248 bool wl_hi_pri_task2;
1249 bool wl_force_lps_ctrl;
1250 bool wl_gl_busy;
1251 bool wl_linkscan_proc;
1252 bool wl_ps_state_fail;
1253 bool wl_tx_limit_en;
1254 bool wl_ampdu_limit_en;
1255 bool wl_connected;
1256 bool wl_slot_extend;
1257 bool wl_cck_lock;
1258 bool wl_cck_lock_pre;
1259 bool wl_cck_lock_ever;
1260
1261 u32 bt_supported_version;
1262 u32 bt_supported_feature;
1263 u32 patch_ver;
1264 u16 bt_reg_vendor_ae;
1265 u16 bt_reg_vendor_ac;
1266 s8 bt_rssi;
1267 u8 kt_ver;
1268 u8 gnt_workaround_state;
1269 u8 tdma_timer_base;
1270 u8 bt_profile_num;
1271 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1272 u8 bt_info_lb2;
1273 u8 bt_info_lb3;
1274 u8 bt_info_hb0;
1275 u8 bt_info_hb1;
1276 u8 bt_info_hb2;
1277 u8 bt_info_hb3;
1278 u8 bt_ble_scan_type;
1279 u8 bt_hid_pair_num;
1280 u8 bt_hid_slot;
1281 u8 bt_a2dp_bitpool;
1282 u8 bt_iqk_state;
1283
1284 u8 wl_noisy_level;
1285 u8 wl_fw_dbg_info[10];
1286 u8 wl_fw_dbg_info_pre[10];
1287 u8 wl_coex_mode;
1288 u8 ampdu_max_time;
1289 u8 wl_tput_dir;
1290
1291 u16 score_board;
1292 u16 retry_limit;
1293
1294 /* counters to record bt states */
1295 u32 cnt_bt[COEX_CNT_BT_MAX];
1296
1297 /* counters to record wifi states */
1298 u32 cnt_wl[COEX_CNT_WL_MAX];
1299
1300 u32 darfrc;
1301 u32 darfrch;
1302 };
1303
1304 struct rtw_coex {
1305 /* protects coex info request section */
1306 struct mutex mutex;
1307 struct sk_buff_head queue;
1308 wait_queue_head_t wait;
1309
1310 bool under_5g;
1311 bool stop_dm;
1312 bool freeze;
1313 bool freerun;
1314 bool wl_rf_off;
1315
1316 struct rtw_coex_stat stat;
1317 struct rtw_coex_dm dm;
1318 struct rtw_coex_rfe rfe;
1319
1320 struct delayed_work bt_relink_work;
1321 struct delayed_work bt_reenable_work;
1322 struct delayed_work defreeze_work;
1323 };
1324
1325 #define DPK_RF_REG_NUM 7
1326 #define DPK_RF_PATH_NUM 2
1327 #define DPK_BB_REG_NUM 18
1328 #define DPK_CHANNEL_WIDTH_80 1
1329
1330 DECLARE_EWMA(thermal, 10, 4);
1331
1332 struct rtw_dpk_info {
1333 bool is_dpk_pwr_on;
1334 bool is_reload;
1335
1336 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1337
1338 u8 thermal_dpk[DPK_RF_PATH_NUM];
1339 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1340
1341 u32 gnt_control;
1342 u32 gnt_value;
1343
1344 u8 result[RTW_RF_PATH_MAX];
1345 u8 dpk_txagc[RTW_RF_PATH_MAX];
1346 u32 coef[RTW_RF_PATH_MAX][20];
1347 u16 dpk_gs[RTW_RF_PATH_MAX];
1348 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1349 u8 pre_pwsf[RTW_RF_PATH_MAX];
1350
1351 u8 dpk_band;
1352 u8 dpk_ch;
1353 u8 dpk_bw;
1354 };
1355
1356 struct rtw_phy_cck_pd_reg {
1357 u32 reg_pd;
1358 u32 mask_pd;
1359 u32 reg_cs;
1360 u32 mask_cs;
1361 };
1362
1363 #define DACK_MSBK_BACKUP_NUM 0xf
1364 #define DACK_DCK_BACKUP_NUM 0x2
1365
1366 struct rtw_swing_table {
1367 const u8 *p[RTW_RF_PATH_MAX];
1368 const u8 *n[RTW_RF_PATH_MAX];
1369 };
1370
1371 struct rtw_pkt_count {
1372 u16 num_bcn_pkt;
1373 u16 num_qry_pkt[DESC_RATE_MAX];
1374 };
1375
1376 DECLARE_EWMA(evm, 10, 4);
1377 DECLARE_EWMA(snr, 10, 4);
1378
1379 struct rtw_dm_info {
1380 u32 cck_fa_cnt;
1381 u32 ofdm_fa_cnt;
1382 u32 total_fa_cnt;
1383 u32 cck_cca_cnt;
1384 u32 ofdm_cca_cnt;
1385 u32 total_cca_cnt;
1386
1387 u32 cck_ok_cnt;
1388 u32 cck_err_cnt;
1389 u32 ofdm_ok_cnt;
1390 u32 ofdm_err_cnt;
1391 u32 ht_ok_cnt;
1392 u32 ht_err_cnt;
1393 u32 vht_ok_cnt;
1394 u32 vht_err_cnt;
1395
1396 u8 min_rssi;
1397 u8 pre_min_rssi;
1398 u16 fa_history[4];
1399 u8 igi_history[4];
1400 u8 igi_bitmap;
1401 bool damping;
1402 u8 damping_cnt;
1403 u8 damping_rssi;
1404
1405 u8 cck_gi_u_bnd;
1406 u8 cck_gi_l_bnd;
1407
1408 u8 tx_rate;
1409 u8 thermal_avg[RTW_RF_PATH_MAX];
1410 u8 thermal_meter_k;
1411 s8 delta_power_index[RTW_RF_PATH_MAX];
1412 u8 default_ofdm_index;
1413 bool pwr_trk_triggered;
1414 bool pwr_trk_init_trigger;
1415 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1416
1417 /* backup dack results for each path and I/Q */
1418 u32 dack_adck[RTW_RF_PATH_MAX];
1419 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1420 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1421
1422 struct rtw_dpk_info dpk_info;
1423
1424 /* [bandwidth 0:20M/1:40M][number of path] */
1425 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1426 u32 cck_fa_avg;
1427
1428 /* save the last rx phy status for debug */
1429 s8 rx_snr[RTW_RF_PATH_MAX];
1430 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1431 s16 cfo_tail[RTW_RF_PATH_MAX];
1432 u8 rssi[RTW_RF_PATH_MAX];
1433 u8 curr_rx_rate;
1434 struct rtw_pkt_count cur_pkt_count;
1435 struct rtw_pkt_count last_pkt_count;
1436 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1437 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1438 };
1439
1440 struct rtw_efuse {
1441 u32 size;
1442 u32 physical_size;
1443 u32 logical_size;
1444 u32 protect_size;
1445
1446 u8 addr[ETH_ALEN];
1447 u8 channel_plan;
1448 u8 country_code[2];
1449 u8 rf_board_option;
1450 u8 rfe_option;
1451 u8 power_track_type;
1452 u8 thermal_meter[RTW_RF_PATH_MAX];
1453 u8 thermal_meter_k;
1454 u8 crystal_cap;
1455 u8 ant_div_cfg;
1456 u8 ant_div_type;
1457 u8 regd;
1458
1459 u8 lna_type_2g;
1460 u8 lna_type_5g;
1461 u8 glna_type;
1462 u8 alna_type;
1463 bool ext_lna_2g;
1464 bool ext_lna_5g;
1465 u8 pa_type_2g;
1466 u8 pa_type_5g;
1467 u8 gpa_type;
1468 u8 apa_type;
1469 bool ext_pa_2g;
1470 bool ext_pa_5g;
1471
1472 bool btcoex;
1473 /* bt share antenna with wifi */
1474 bool share_ant;
1475 u8 bt_setting;
1476
1477 struct {
1478 u8 hci;
1479 u8 bw;
1480 u8 ptcl;
1481 u8 nss;
1482 u8 ant_num;
1483 } hw_cap;
1484
1485 struct rtw_txpwr_idx txpwr_idx_table[4];
1486 };
1487
1488 struct rtw_phy_cond {
1489 #ifdef __LITTLE_ENDIAN
1490 u32 rfe:8;
1491 u32 intf:4;
1492 u32 pkg:4;
1493 u32 plat:4;
1494 u32 intf_rsvd:4;
1495 u32 cut:4;
1496 u32 branch:2;
1497 u32 neg:1;
1498 u32 pos:1;
1499 #else
1500 u32 pos:1;
1501 u32 neg:1;
1502 u32 branch:2;
1503 u32 cut:4;
1504 u32 intf_rsvd:4;
1505 u32 plat:4;
1506 u32 pkg:4;
1507 u32 intf:4;
1508 u32 rfe:8;
1509 #endif
1510 /* for intf:4 */
1511 #define INTF_PCIE BIT(0)
1512 #define INTF_USB BIT(1)
1513 #define INTF_SDIO BIT(2)
1514 /* for branch:2 */
1515 #define BRANCH_IF 0
1516 #define BRANCH_ELIF 1
1517 #define BRANCH_ELSE 2
1518 #define BRANCH_ENDIF 3
1519 };
1520
1521 struct rtw_fifo_conf {
1522 /* tx fifo information */
1523 u16 rsvd_boundary;
1524 u16 rsvd_pg_num;
1525 u16 rsvd_drv_pg_num;
1526 u16 txff_pg_num;
1527 u16 acq_pg_num;
1528 u16 rsvd_drv_addr;
1529 u16 rsvd_h2c_info_addr;
1530 u16 rsvd_h2c_sta_info_addr;
1531 u16 rsvd_h2cq_addr;
1532 u16 rsvd_cpu_instr_addr;
1533 u16 rsvd_fw_txbuf_addr;
1534 u16 rsvd_csibuf_addr;
1535 const struct rtw_rqpn *rqpn;
1536 };
1537
1538 struct rtw_fw_state {
1539 const struct firmware *firmware;
1540 struct rtw_dev *rtwdev;
1541 struct completion completion;
1542 u16 version;
1543 u8 sub_version;
1544 u8 sub_index;
1545 u16 h2c_version;
1546 };
1547
1548 struct rtw_hal {
1549 u32 rcr;
1550
1551 u32 chip_version;
1552 u8 cut_version;
1553 u8 mp_chip;
1554 u8 oem_id;
1555 struct rtw_phy_cond phy_cond;
1556
1557 u8 ps_mode;
1558 u8 current_channel;
1559 u8 current_band_width;
1560 u8 current_band_type;
1561
1562 /* center channel for different available bandwidth,
1563 * val of (bw > current_band_width) is invalid
1564 */
1565 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1566
1567 u8 sec_ch_offset;
1568 u8 rf_type;
1569 u8 rf_path_num;
1570 u8 antenna_tx;
1571 u8 antenna_rx;
1572 u8 bfee_sts_cap;
1573
1574 /* protect tx power section */
1575 struct mutex tx_power_mutex;
1576 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1577 [DESC_RATE_MAX];
1578 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1579 [DESC_RATE_MAX];
1580 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1581 [RTW_RATE_SECTION_MAX];
1582 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1583 [RTW_RATE_SECTION_MAX];
1584 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1585 [RTW_CHANNEL_WIDTH_MAX]
1586 [RTW_RATE_SECTION_MAX]
1587 [RTW_MAX_CHANNEL_NUM_2G];
1588 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1589 [RTW_CHANNEL_WIDTH_MAX]
1590 [RTW_RATE_SECTION_MAX]
1591 [RTW_MAX_CHANNEL_NUM_5G];
1592 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1593 [DESC_RATE_MAX];
1594 };
1595
1596 struct rtw_dev {
1597 struct ieee80211_hw *hw;
1598 struct device *dev;
1599
1600 struct rtw_hci hci;
1601
1602 struct rtw_chip_info *chip;
1603 struct rtw_hal hal;
1604 struct rtw_fifo_conf fifo;
1605 struct rtw_fw_state fw;
1606 struct rtw_efuse efuse;
1607 struct rtw_sec_desc sec;
1608 struct rtw_traffic_stats stats;
1609 struct rtw_regulatory regd;
1610 struct rtw_bf_info bf_info;
1611
1612 struct rtw_dm_info dm_info;
1613 struct rtw_coex coex;
1614
1615 /* ensures exclusive access from mac80211 callbacks */
1616 struct mutex mutex;
1617
1618 /* read/write rf register */
1619 spinlock_t rf_lock;
1620
1621 /* watch dog every 2 sec */
1622 struct delayed_work watch_dog_work;
1623 u32 watch_dog_cnt;
1624
1625 struct list_head rsvd_page_list;
1626
1627 /* c2h cmd queue & handler work */
1628 struct sk_buff_head c2h_queue;
1629 struct work_struct c2h_work;
1630
1631 /* used to protect txqs list */
1632 spinlock_t txq_lock;
1633 struct list_head txqs;
1634 struct tasklet_struct tx_tasklet;
1635 struct work_struct ba_work;
1636
1637 struct rtw_tx_report tx_report;
1638
1639 struct {
1640 /* incicate the mail box to use with fw */
1641 u8 last_box_num;
1642 /* protect to send h2c to fw */
1643 spinlock_t lock;
1644 u32 seq;
1645 } h2c;
1646
1647 /* lps power state & handler work */
1648 struct rtw_lps_conf lps_conf;
1649 bool ps_enabled;
1650
1651 struct dentry *debugfs;
1652
1653 u8 sta_cnt;
1654 u32 rts_threshold;
1655
1656 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
1657 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
1658
1659 u8 mp_mode;
1660
1661 struct rtw_fw_state wow_fw;
1662 struct rtw_wow_param wow;
1663
1664 /* hci related data, must be last */
1665 u8 priv[] __aligned(sizeof(void *));
1666 };
1667
1668 #include "hci.h"
1669
1670 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
1671 {
1672 return !!rtwdev->sta_cnt;
1673 }
1674
1675 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
1676 {
1677 void *p = rtwtxq;
1678
1679 return container_of(p, struct ieee80211_txq, drv_priv);
1680 }
1681
1682 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
1683 {
1684 void *p = rtwvif;
1685
1686 return container_of(p, struct ieee80211_vif, drv_priv);
1687 }
1688
1689 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
1690 struct cfg80211_ssid *b)
1691 {
1692 if (!a || !b || a->ssid_len != b->ssid_len)
1693 return false;
1694
1695 if (memcmp(a->ssid, b->ssid, a->ssid_len))
1696 return false;
1697
1698 return true;
1699 }
1700
1701 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
1702 struct rtw_channel_params *ch_param);
1703 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
1704 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
1705 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
1706 void rtw_restore_reg(struct rtw_dev *rtwdev,
1707 struct rtw_backup_info *bckp, u32 num);
1708 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
1709 void rtw_set_channel(struct rtw_dev *rtwdev);
1710 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1711 u32 config);
1712 void rtw_tx_report_purge_timer(struct timer_list *t);
1713 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
1714 int rtw_core_start(struct rtw_dev *rtwdev);
1715 void rtw_core_stop(struct rtw_dev *rtwdev);
1716 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
1717 int rtw_core_init(struct rtw_dev *rtwdev);
1718 void rtw_core_deinit(struct rtw_dev *rtwdev);
1719 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1720 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1721 u16 rtw_desc_to_bitrate(u8 desc_rate);
1722
1723 #endif
Linux with added FPC-III support