1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * This file is part of wl12xx
5 * Copyright (C) 2011 Texas Instruments Inc.
8 #ifndef __WL12XX_PRIV_H__
9 #define __WL12XX_PRIV_H__
13 /* WiLink 6/7 chip IDs */
14 #define CHIP_ID_127X_PG10 (0x04030101)
15 #define CHIP_ID_127X_PG20 (0x04030111)
16 #define CHIP_ID_128X_PG10 (0x05030101)
17 #define CHIP_ID_128X_PG20 (0x05030111)
19 /* FW chip version for wl127x */
20 #define WL127X_CHIP_VER 6
21 /* minimum single-role FW version for wl127x */
22 #define WL127X_IFTYPE_SR_VER 3
23 #define WL127X_MAJOR_SR_VER 10
24 #define WL127X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE
25 #define WL127X_MINOR_SR_VER 133
26 /* minimum multi-role FW version for wl127x */
27 #define WL127X_IFTYPE_MR_VER 5
28 #define WL127X_MAJOR_MR_VER 7
29 #define WL127X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE
30 #define WL127X_MINOR_MR_VER 42
32 /* FW chip version for wl128x */
33 #define WL128X_CHIP_VER 7
34 /* minimum single-role FW version for wl128x */
35 #define WL128X_IFTYPE_SR_VER 3
36 #define WL128X_MAJOR_SR_VER 10
37 #define WL128X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE
38 #define WL128X_MINOR_SR_VER 133
39 /* minimum multi-role FW version for wl128x */
40 #define WL128X_IFTYPE_MR_VER 5
41 #define WL128X_MAJOR_MR_VER 7
42 #define WL128X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE
43 #define WL128X_MINOR_MR_VER 42
45 #define WL12XX_AGGR_BUFFER_SIZE (4 * PAGE_SIZE)
47 #define WL12XX_NUM_TX_DESCRIPTORS 16
48 #define WL12XX_NUM_RX_DESCRIPTORS 8
50 #define WL12XX_NUM_MAC_ADDRESSES 2
52 #define WL12XX_RX_BA_MAX_SESSIONS 3
54 #define WL12XX_MAX_AP_STATIONS 8
55 #define WL12XX_MAX_LINKS 12
57 struct wl127x_rx_mem_pool_addr
{
63 struct wl12xx_priv_conf conf
;
68 struct wl127x_rx_mem_pool_addr
*rx_mem_addr
;
71 /* Reference clock values */
73 WL12XX_REFCLOCK_19
= 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26
= 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38
= 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52
= 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL
= 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL
= 5, /* 26 MHz, XTAL */
81 /* TCXO clock values */
83 WL12XX_TCXOCLOCK_19_2
= 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26
= 1, /* 26 MHz */
85 WL12XX_TCXOCLOCK_38_4
= 2, /* 38.4MHz */
86 WL12XX_TCXOCLOCK_52
= 3, /* 52 MHz */
87 WL12XX_TCXOCLOCK_16_368
= 4, /* 16.368 MHz */
88 WL12XX_TCXOCLOCK_32_736
= 5, /* 32.736 MHz */
89 WL12XX_TCXOCLOCK_16_8
= 6, /* 16.8 MHz */
90 WL12XX_TCXOCLOCK_33_6
= 7, /* 33.6 MHz */
99 struct wl12xx_fw_packet_counters
{
100 /* Cumulative counter of released packets per AC */
101 u8 tx_released_pkts
[NUM_TX_QUEUES
];
103 /* Cumulative counter of freed packets per HLID */
104 u8 tx_lnk_free_pkts
[WL12XX_MAX_LINKS
];
106 /* Cumulative counter of released Voice memory blocks */
107 u8 tx_voice_released_blks
;
109 /* Tx rate of the last transmitted packet */
115 /* FW status registers */
116 struct wl12xx_fw_status
{
121 u8 tx_results_counter
;
122 __le32 rx_pkt_descs
[WL12XX_NUM_RX_DESCRIPTORS
];
127 * A bitmap (where each bit represents a single HLID)
128 * to indicate if the station is in PS mode.
130 __le32 link_ps_bitmap
;
133 * A bitmap (where each bit represents a single HLID) to indicate
134 * if the station is in Fast mode
136 __le32 link_fast_bitmap
;
138 /* Cumulative counter of total released mem blocks since FW-reset */
139 __le32 total_released_blks
;
141 /* Size (in Memory Blocks) of TX pool */
144 struct wl12xx_fw_packet_counters counters
;
146 __le32 log_start_addr
;
149 #endif /* __WL12XX_PRIV_H__ */