1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2005 David Shaohua Li <shaohua.li@intel.com>
6 * Copyright (C) 2004 Tom Long Nguyen <tom.l.nguyen@intel.com>
7 * Copyright (C) 2004 Intel Corp.
10 #include <linux/delay.h>
11 #include <linux/init.h>
12 #include <linux/irqdomain.h>
13 #include <linux/pci.h>
14 #include <linux/msi.h>
15 #include <linux/pci_hotplug.h>
16 #include <linux/module.h>
17 #include <linux/pci-acpi.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/pm_qos.h>
23 * The GUID is defined in the PCI Firmware Specification available here:
24 * https://www.pcisig.com/members/downloads/pcifw_r3_1_13Dec10.pdf
26 const guid_t pci_acpi_dsm_guid
=
27 GUID_INIT(0xe5c937d0, 0x3553, 0x4d7a,
28 0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d);
30 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
31 static int acpi_get_rc_addr(struct acpi_device
*adev
, struct resource
*res
)
33 struct device
*dev
= &adev
->dev
;
34 struct resource_entry
*entry
;
35 struct list_head list
;
39 INIT_LIST_HEAD(&list
);
40 flags
= IORESOURCE_MEM
;
41 ret
= acpi_dev_get_resources(adev
, &list
,
42 acpi_dev_filter_resource_type_cb
,
45 dev_err(dev
, "failed to parse _CRS method, error code %d\n",
51 dev_err(dev
, "no IO and memory resources present in _CRS\n");
55 entry
= list_first_entry(&list
, struct resource_entry
, node
);
57 acpi_dev_free_resource_list(&list
);
61 static acpi_status
acpi_match_rc(acpi_handle handle
, u32 lvl
, void *context
,
64 u16
*segment
= context
;
65 unsigned long long uid
;
68 status
= acpi_evaluate_integer(handle
, "_UID", NULL
, &uid
);
69 if (ACPI_FAILURE(status
) || uid
!= *segment
)
72 *(acpi_handle
*)retval
= handle
;
73 return AE_CTRL_TERMINATE
;
76 int acpi_get_rc_resources(struct device
*dev
, const char *hid
, u16 segment
,
79 struct acpi_device
*adev
;
84 status
= acpi_get_devices(hid
, acpi_match_rc
, &segment
, &handle
);
85 if (ACPI_FAILURE(status
)) {
86 dev_err(dev
, "can't find _HID %s device to locate resources\n",
91 ret
= acpi_bus_get_device(handle
, &adev
);
95 ret
= acpi_get_rc_addr(adev
, res
);
97 dev_err(dev
, "can't get resource from %s\n",
98 dev_name(&adev
->dev
));
106 phys_addr_t
acpi_pci_root_get_mcfg_addr(acpi_handle handle
)
108 acpi_status status
= AE_NOT_EXIST
;
109 unsigned long long mcfg_addr
;
112 status
= acpi_evaluate_integer(handle
, METHOD_NAME__CBA
,
114 if (ACPI_FAILURE(status
))
117 return (phys_addr_t
)mcfg_addr
;
120 /* _HPX PCI Setting Record (Type 0); same as _HPP */
122 u32 revision
; /* Not present in _HPP */
123 u8 cache_line_size
; /* Not applicable to PCIe */
124 u8 latency_timer
; /* Not applicable to PCIe */
129 static struct hpx_type0 pci_default_type0
= {
131 .cache_line_size
= 8,
132 .latency_timer
= 0x40,
137 static void program_hpx_type0(struct pci_dev
*dev
, struct hpx_type0
*hpx
)
139 u16 pci_cmd
, pci_bctl
;
142 hpx
= &pci_default_type0
;
144 if (hpx
->revision
> 1) {
145 pci_warn(dev
, "PCI settings rev %d not supported; using defaults\n",
147 hpx
= &pci_default_type0
;
150 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, hpx
->cache_line_size
);
151 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, hpx
->latency_timer
);
152 pci_read_config_word(dev
, PCI_COMMAND
, &pci_cmd
);
153 if (hpx
->enable_serr
)
154 pci_cmd
|= PCI_COMMAND_SERR
;
155 if (hpx
->enable_perr
)
156 pci_cmd
|= PCI_COMMAND_PARITY
;
157 pci_write_config_word(dev
, PCI_COMMAND
, pci_cmd
);
159 /* Program bridge control value */
160 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
161 pci_write_config_byte(dev
, PCI_SEC_LATENCY_TIMER
,
163 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &pci_bctl
);
164 if (hpx
->enable_perr
)
165 pci_bctl
|= PCI_BRIDGE_CTL_PARITY
;
166 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, pci_bctl
);
170 static acpi_status
decode_type0_hpx_record(union acpi_object
*record
,
171 struct hpx_type0
*hpx0
)
174 union acpi_object
*fields
= record
->package
.elements
;
175 u32 revision
= fields
[1].integer
.value
;
179 if (record
->package
.count
!= 6)
181 for (i
= 2; i
< 6; i
++)
182 if (fields
[i
].type
!= ACPI_TYPE_INTEGER
)
184 hpx0
->revision
= revision
;
185 hpx0
->cache_line_size
= fields
[2].integer
.value
;
186 hpx0
->latency_timer
= fields
[3].integer
.value
;
187 hpx0
->enable_serr
= fields
[4].integer
.value
;
188 hpx0
->enable_perr
= fields
[5].integer
.value
;
191 pr_warn("%s: Type 0 Revision %d record not supported\n",
198 /* _HPX PCI-X Setting Record (Type 1) */
206 static void program_hpx_type1(struct pci_dev
*dev
, struct hpx_type1
*hpx
)
213 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
217 pci_warn(dev
, "PCI-X settings not supported\n");
220 static acpi_status
decode_type1_hpx_record(union acpi_object
*record
,
221 struct hpx_type1
*hpx1
)
224 union acpi_object
*fields
= record
->package
.elements
;
225 u32 revision
= fields
[1].integer
.value
;
229 if (record
->package
.count
!= 5)
231 for (i
= 2; i
< 5; i
++)
232 if (fields
[i
].type
!= ACPI_TYPE_INTEGER
)
234 hpx1
->revision
= revision
;
235 hpx1
->max_mem_read
= fields
[2].integer
.value
;
236 hpx1
->avg_max_split
= fields
[3].integer
.value
;
237 hpx1
->tot_max_split
= fields
[4].integer
.value
;
240 pr_warn("%s: Type 1 Revision %d record not supported\n",
247 static bool pcie_root_rcb_set(struct pci_dev
*dev
)
249 struct pci_dev
*rp
= pcie_find_root_port(dev
);
255 pcie_capability_read_word(rp
, PCI_EXP_LNKCTL
, &lnkctl
);
256 if (lnkctl
& PCI_EXP_LNKCTL_RCB
)
262 /* _HPX PCI Express Setting Record (Type 2) */
265 u32 unc_err_mask_and
;
267 u32 unc_err_sever_and
;
268 u32 unc_err_sever_or
;
269 u32 cor_err_mask_and
;
273 u16 pci_exp_devctl_and
;
274 u16 pci_exp_devctl_or
;
275 u16 pci_exp_lnkctl_and
;
276 u16 pci_exp_lnkctl_or
;
277 u32 sec_unc_err_sever_and
;
278 u32 sec_unc_err_sever_or
;
279 u32 sec_unc_err_mask_and
;
280 u32 sec_unc_err_mask_or
;
283 static void program_hpx_type2(struct pci_dev
*dev
, struct hpx_type2
*hpx
)
291 if (!pci_is_pcie(dev
))
294 if (hpx
->revision
> 1) {
295 pci_warn(dev
, "PCIe settings rev %d not supported\n",
301 * Don't allow _HPX to change MPS or MRRS settings. We manage
302 * those to make sure they're consistent with the rest of the
305 hpx
->pci_exp_devctl_and
|= PCI_EXP_DEVCTL_PAYLOAD
|
306 PCI_EXP_DEVCTL_READRQ
;
307 hpx
->pci_exp_devctl_or
&= ~(PCI_EXP_DEVCTL_PAYLOAD
|
308 PCI_EXP_DEVCTL_READRQ
);
310 /* Initialize Device Control Register */
311 pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
312 ~hpx
->pci_exp_devctl_and
, hpx
->pci_exp_devctl_or
);
314 /* Initialize Link Control Register */
315 if (pcie_cap_has_lnkctl(dev
)) {
318 * If the Root Port supports Read Completion Boundary of
319 * 128, set RCB to 128. Otherwise, clear it.
321 hpx
->pci_exp_lnkctl_and
|= PCI_EXP_LNKCTL_RCB
;
322 hpx
->pci_exp_lnkctl_or
&= ~PCI_EXP_LNKCTL_RCB
;
323 if (pcie_root_rcb_set(dev
))
324 hpx
->pci_exp_lnkctl_or
|= PCI_EXP_LNKCTL_RCB
;
326 pcie_capability_clear_and_set_word(dev
, PCI_EXP_LNKCTL
,
327 ~hpx
->pci_exp_lnkctl_and
, hpx
->pci_exp_lnkctl_or
);
330 /* Find Advanced Error Reporting Enhanced Capability */
331 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
335 /* Initialize Uncorrectable Error Mask Register */
336 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, ®32
);
337 reg32
= (reg32
& hpx
->unc_err_mask_and
) | hpx
->unc_err_mask_or
;
338 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, reg32
);
340 /* Initialize Uncorrectable Error Severity Register */
341 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, ®32
);
342 reg32
= (reg32
& hpx
->unc_err_sever_and
) | hpx
->unc_err_sever_or
;
343 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, reg32
);
345 /* Initialize Correctable Error Mask Register */
346 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, ®32
);
347 reg32
= (reg32
& hpx
->cor_err_mask_and
) | hpx
->cor_err_mask_or
;
348 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, reg32
);
350 /* Initialize Advanced Error Capabilities and Control Register */
351 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, ®32
);
352 reg32
= (reg32
& hpx
->adv_err_cap_and
) | hpx
->adv_err_cap_or
;
354 /* Don't enable ECRC generation or checking if unsupported */
355 if (!(reg32
& PCI_ERR_CAP_ECRC_GENC
))
356 reg32
&= ~PCI_ERR_CAP_ECRC_GENE
;
357 if (!(reg32
& PCI_ERR_CAP_ECRC_CHKC
))
358 reg32
&= ~PCI_ERR_CAP_ECRC_CHKE
;
359 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, reg32
);
362 * FIXME: The following two registers are not supported yet.
364 * o Secondary Uncorrectable Error Severity Register
365 * o Secondary Uncorrectable Error Mask Register
369 static acpi_status
decode_type2_hpx_record(union acpi_object
*record
,
370 struct hpx_type2
*hpx2
)
373 union acpi_object
*fields
= record
->package
.elements
;
374 u32 revision
= fields
[1].integer
.value
;
378 if (record
->package
.count
!= 18)
380 for (i
= 2; i
< 18; i
++)
381 if (fields
[i
].type
!= ACPI_TYPE_INTEGER
)
383 hpx2
->revision
= revision
;
384 hpx2
->unc_err_mask_and
= fields
[2].integer
.value
;
385 hpx2
->unc_err_mask_or
= fields
[3].integer
.value
;
386 hpx2
->unc_err_sever_and
= fields
[4].integer
.value
;
387 hpx2
->unc_err_sever_or
= fields
[5].integer
.value
;
388 hpx2
->cor_err_mask_and
= fields
[6].integer
.value
;
389 hpx2
->cor_err_mask_or
= fields
[7].integer
.value
;
390 hpx2
->adv_err_cap_and
= fields
[8].integer
.value
;
391 hpx2
->adv_err_cap_or
= fields
[9].integer
.value
;
392 hpx2
->pci_exp_devctl_and
= fields
[10].integer
.value
;
393 hpx2
->pci_exp_devctl_or
= fields
[11].integer
.value
;
394 hpx2
->pci_exp_lnkctl_and
= fields
[12].integer
.value
;
395 hpx2
->pci_exp_lnkctl_or
= fields
[13].integer
.value
;
396 hpx2
->sec_unc_err_sever_and
= fields
[14].integer
.value
;
397 hpx2
->sec_unc_err_sever_or
= fields
[15].integer
.value
;
398 hpx2
->sec_unc_err_mask_and
= fields
[16].integer
.value
;
399 hpx2
->sec_unc_err_mask_or
= fields
[17].integer
.value
;
402 pr_warn("%s: Type 2 Revision %d record not supported\n",
409 /* _HPX PCI Express Setting Record (Type 3) */
413 u16 config_space_location
;
416 u16 pci_exp_vendor_id
;
427 enum hpx_type3_dev_type
{
428 HPX_TYPE_ENDPOINT
= BIT(0),
429 HPX_TYPE_LEG_END
= BIT(1),
430 HPX_TYPE_RC_END
= BIT(2),
431 HPX_TYPE_RC_EC
= BIT(3),
432 HPX_TYPE_ROOT_PORT
= BIT(4),
433 HPX_TYPE_UPSTREAM
= BIT(5),
434 HPX_TYPE_DOWNSTREAM
= BIT(6),
435 HPX_TYPE_PCI_BRIDGE
= BIT(7),
436 HPX_TYPE_PCIE_BRIDGE
= BIT(8),
439 static u16
hpx3_device_type(struct pci_dev
*dev
)
441 u16 pcie_type
= pci_pcie_type(dev
);
442 static const int pcie_to_hpx3_type
[] = {
443 [PCI_EXP_TYPE_ENDPOINT
] = HPX_TYPE_ENDPOINT
,
444 [PCI_EXP_TYPE_LEG_END
] = HPX_TYPE_LEG_END
,
445 [PCI_EXP_TYPE_RC_END
] = HPX_TYPE_RC_END
,
446 [PCI_EXP_TYPE_RC_EC
] = HPX_TYPE_RC_EC
,
447 [PCI_EXP_TYPE_ROOT_PORT
] = HPX_TYPE_ROOT_PORT
,
448 [PCI_EXP_TYPE_UPSTREAM
] = HPX_TYPE_UPSTREAM
,
449 [PCI_EXP_TYPE_DOWNSTREAM
] = HPX_TYPE_DOWNSTREAM
,
450 [PCI_EXP_TYPE_PCI_BRIDGE
] = HPX_TYPE_PCI_BRIDGE
,
451 [PCI_EXP_TYPE_PCIE_BRIDGE
] = HPX_TYPE_PCIE_BRIDGE
,
454 if (pcie_type
>= ARRAY_SIZE(pcie_to_hpx3_type
))
457 return pcie_to_hpx3_type
[pcie_type
];
460 enum hpx_type3_fn_type
{
461 HPX_FN_NORMAL
= BIT(0),
462 HPX_FN_SRIOV_PHYS
= BIT(1),
463 HPX_FN_SRIOV_VIRT
= BIT(2),
466 static u8
hpx3_function_type(struct pci_dev
*dev
)
469 return HPX_FN_SRIOV_VIRT
;
470 else if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_SRIOV
) > 0)
471 return HPX_FN_SRIOV_PHYS
;
473 return HPX_FN_NORMAL
;
476 static bool hpx3_cap_ver_matches(u8 pcie_cap_id
, u8 hpx3_cap_id
)
478 u8 cap_ver
= hpx3_cap_id
& 0xf;
480 if ((hpx3_cap_id
& BIT(4)) && cap_ver
>= pcie_cap_id
)
482 else if (cap_ver
== pcie_cap_id
)
488 enum hpx_type3_cfg_loc
{
490 HPX_CFG_PCIE_CAP
= 1,
491 HPX_CFG_PCIE_CAP_EXT
= 2,
492 HPX_CFG_VEND_CAP
= 3,
497 static void program_hpx_type3_register(struct pci_dev
*dev
,
498 const struct hpx_type3
*reg
)
500 u32 match_reg
, write_reg
, header
, orig_value
;
503 if (!(hpx3_device_type(dev
) & reg
->device_type
))
506 if (!(hpx3_function_type(dev
) & reg
->function_type
))
509 switch (reg
->config_space_location
) {
513 case HPX_CFG_PCIE_CAP
:
514 pos
= pci_find_capability(dev
, reg
->pci_exp_cap_id
);
519 case HPX_CFG_PCIE_CAP_EXT
:
520 pos
= pci_find_ext_capability(dev
, reg
->pci_exp_cap_id
);
524 pci_read_config_dword(dev
, pos
, &header
);
525 if (!hpx3_cap_ver_matches(PCI_EXT_CAP_VER(header
),
526 reg
->pci_exp_cap_ver
))
530 case HPX_CFG_VEND_CAP
: /* Fall through */
531 case HPX_CFG_DVSEC
: /* Fall through */
533 pci_warn(dev
, "Encountered _HPX type 3 with unsupported config space location");
537 pci_read_config_dword(dev
, pos
+ reg
->match_offset
, &match_reg
);
539 if ((match_reg
& reg
->match_mask_and
) != reg
->match_value
)
542 pci_read_config_dword(dev
, pos
+ reg
->reg_offset
, &write_reg
);
543 orig_value
= write_reg
;
544 write_reg
&= reg
->reg_mask_and
;
545 write_reg
|= reg
->reg_mask_or
;
547 if (orig_value
== write_reg
)
550 pci_write_config_dword(dev
, pos
+ reg
->reg_offset
, write_reg
);
552 pci_dbg(dev
, "Applied _HPX3 at [0x%x]: 0x%08x -> 0x%08x",
553 pos
, orig_value
, write_reg
);
556 static void program_hpx_type3(struct pci_dev
*dev
, struct hpx_type3
*hpx
)
561 if (!pci_is_pcie(dev
))
564 program_hpx_type3_register(dev
, hpx
);
567 static void parse_hpx3_register(struct hpx_type3
*hpx3_reg
,
568 union acpi_object
*reg_fields
)
570 hpx3_reg
->device_type
= reg_fields
[0].integer
.value
;
571 hpx3_reg
->function_type
= reg_fields
[1].integer
.value
;
572 hpx3_reg
->config_space_location
= reg_fields
[2].integer
.value
;
573 hpx3_reg
->pci_exp_cap_id
= reg_fields
[3].integer
.value
;
574 hpx3_reg
->pci_exp_cap_ver
= reg_fields
[4].integer
.value
;
575 hpx3_reg
->pci_exp_vendor_id
= reg_fields
[5].integer
.value
;
576 hpx3_reg
->dvsec_id
= reg_fields
[6].integer
.value
;
577 hpx3_reg
->dvsec_rev
= reg_fields
[7].integer
.value
;
578 hpx3_reg
->match_offset
= reg_fields
[8].integer
.value
;
579 hpx3_reg
->match_mask_and
= reg_fields
[9].integer
.value
;
580 hpx3_reg
->match_value
= reg_fields
[10].integer
.value
;
581 hpx3_reg
->reg_offset
= reg_fields
[11].integer
.value
;
582 hpx3_reg
->reg_mask_and
= reg_fields
[12].integer
.value
;
583 hpx3_reg
->reg_mask_or
= reg_fields
[13].integer
.value
;
586 static acpi_status
program_type3_hpx_record(struct pci_dev
*dev
,
587 union acpi_object
*record
)
589 union acpi_object
*fields
= record
->package
.elements
;
590 u32 desc_count
, expected_length
, revision
;
591 union acpi_object
*reg_fields
;
592 struct hpx_type3 hpx3
;
595 revision
= fields
[1].integer
.value
;
598 desc_count
= fields
[2].integer
.value
;
599 expected_length
= 3 + desc_count
* 14;
601 if (record
->package
.count
!= expected_length
)
604 for (i
= 2; i
< expected_length
; i
++)
605 if (fields
[i
].type
!= ACPI_TYPE_INTEGER
)
608 for (i
= 0; i
< desc_count
; i
++) {
609 reg_fields
= fields
+ 3 + i
* 14;
610 parse_hpx3_register(&hpx3
, reg_fields
);
611 program_hpx_type3(dev
, &hpx3
);
617 "%s: Type 3 Revision %d record not supported\n",
624 static acpi_status
acpi_run_hpx(struct pci_dev
*dev
, acpi_handle handle
)
627 struct acpi_buffer buffer
= {ACPI_ALLOCATE_BUFFER
, NULL
};
628 union acpi_object
*package
, *record
, *fields
;
629 struct hpx_type0 hpx0
;
630 struct hpx_type1 hpx1
;
631 struct hpx_type2 hpx2
;
635 status
= acpi_evaluate_object(handle
, "_HPX", NULL
, &buffer
);
636 if (ACPI_FAILURE(status
))
639 package
= (union acpi_object
*)buffer
.pointer
;
640 if (package
->type
!= ACPI_TYPE_PACKAGE
) {
645 for (i
= 0; i
< package
->package
.count
; i
++) {
646 record
= &package
->package
.elements
[i
];
647 if (record
->type
!= ACPI_TYPE_PACKAGE
) {
652 fields
= record
->package
.elements
;
653 if (fields
[0].type
!= ACPI_TYPE_INTEGER
||
654 fields
[1].type
!= ACPI_TYPE_INTEGER
) {
659 type
= fields
[0].integer
.value
;
662 memset(&hpx0
, 0, sizeof(hpx0
));
663 status
= decode_type0_hpx_record(record
, &hpx0
);
664 if (ACPI_FAILURE(status
))
666 program_hpx_type0(dev
, &hpx0
);
669 memset(&hpx1
, 0, sizeof(hpx1
));
670 status
= decode_type1_hpx_record(record
, &hpx1
);
671 if (ACPI_FAILURE(status
))
673 program_hpx_type1(dev
, &hpx1
);
676 memset(&hpx2
, 0, sizeof(hpx2
));
677 status
= decode_type2_hpx_record(record
, &hpx2
);
678 if (ACPI_FAILURE(status
))
680 program_hpx_type2(dev
, &hpx2
);
683 status
= program_type3_hpx_record(dev
, record
);
684 if (ACPI_FAILURE(status
))
688 pr_err("%s: Type %d record not supported\n",
695 kfree(buffer
.pointer
);
699 static acpi_status
acpi_run_hpp(struct pci_dev
*dev
, acpi_handle handle
)
702 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
703 union acpi_object
*package
, *fields
;
704 struct hpx_type0 hpx0
;
707 memset(&hpx0
, 0, sizeof(hpx0
));
709 status
= acpi_evaluate_object(handle
, "_HPP", NULL
, &buffer
);
710 if (ACPI_FAILURE(status
))
713 package
= (union acpi_object
*) buffer
.pointer
;
714 if (package
->type
!= ACPI_TYPE_PACKAGE
||
715 package
->package
.count
!= 4) {
720 fields
= package
->package
.elements
;
721 for (i
= 0; i
< 4; i
++) {
722 if (fields
[i
].type
!= ACPI_TYPE_INTEGER
) {
729 hpx0
.cache_line_size
= fields
[0].integer
.value
;
730 hpx0
.latency_timer
= fields
[1].integer
.value
;
731 hpx0
.enable_serr
= fields
[2].integer
.value
;
732 hpx0
.enable_perr
= fields
[3].integer
.value
;
734 program_hpx_type0(dev
, &hpx0
);
737 kfree(buffer
.pointer
);
741 /* pci_acpi_program_hp_params
743 * @dev - the pci_dev for which we want parameters
745 int pci_acpi_program_hp_params(struct pci_dev
*dev
)
748 acpi_handle handle
, phandle
;
749 struct pci_bus
*pbus
;
751 if (acpi_pci_disabled
)
755 for (pbus
= dev
->bus
; pbus
; pbus
= pbus
->parent
) {
756 handle
= acpi_pci_get_bridge_handle(pbus
);
762 * _HPP settings apply to all child buses, until another _HPP is
763 * encountered. If we don't find an _HPP for the input pci dev,
764 * look for it in the parent device scope since that would apply to
768 status
= acpi_run_hpx(dev
, handle
);
769 if (ACPI_SUCCESS(status
))
771 status
= acpi_run_hpp(dev
, handle
);
772 if (ACPI_SUCCESS(status
))
774 if (acpi_is_root_bridge(handle
))
776 status
= acpi_get_parent(handle
, &phandle
);
777 if (ACPI_FAILURE(status
))
785 * pciehp_is_native - Check whether a hotplug port is handled by the OS
786 * @bridge: Hotplug port to check
788 * Returns true if the given @bridge is handled by the native PCIe hotplug
791 bool pciehp_is_native(struct pci_dev
*bridge
)
793 const struct pci_host_bridge
*host
;
796 if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE
))
799 pcie_capability_read_dword(bridge
, PCI_EXP_SLTCAP
, &slot_cap
);
800 if (!(slot_cap
& PCI_EXP_SLTCAP_HPC
))
803 if (pcie_ports_native
)
806 host
= pci_find_host_bridge(bridge
->bus
);
807 return host
->native_pcie_hotplug
;
811 * shpchp_is_native - Check whether a hotplug port is handled by the OS
812 * @bridge: Hotplug port to check
814 * Returns true if the given @bridge is handled by the native SHPC hotplug
817 bool shpchp_is_native(struct pci_dev
*bridge
)
819 return bridge
->shpc_managed
;
823 * pci_acpi_wake_bus - Root bus wakeup notification fork function.
824 * @context: Device wakeup context.
826 static void pci_acpi_wake_bus(struct acpi_device_wakeup_context
*context
)
828 struct acpi_device
*adev
;
829 struct acpi_pci_root
*root
;
831 adev
= container_of(context
, struct acpi_device
, wakeup
.context
);
832 root
= acpi_driver_data(adev
);
833 pci_pme_wakeup_bus(root
->bus
);
837 * pci_acpi_wake_dev - PCI device wakeup notification work function.
838 * @context: Device wakeup context.
840 static void pci_acpi_wake_dev(struct acpi_device_wakeup_context
*context
)
842 struct pci_dev
*pci_dev
;
844 pci_dev
= to_pci_dev(context
->dev
);
846 if (pci_dev
->pme_poll
)
847 pci_dev
->pme_poll
= false;
849 if (pci_dev
->current_state
== PCI_D3cold
) {
850 pci_wakeup_event(pci_dev
);
851 pm_request_resume(&pci_dev
->dev
);
855 /* Clear PME Status if set. */
856 if (pci_dev
->pme_support
)
857 pci_check_pme_status(pci_dev
);
859 pci_wakeup_event(pci_dev
);
860 pm_request_resume(&pci_dev
->dev
);
862 pci_pme_wakeup_bus(pci_dev
->subordinate
);
866 * pci_acpi_add_bus_pm_notifier - Register PM notifier for root PCI bus.
867 * @dev: PCI root bridge ACPI device.
869 acpi_status
pci_acpi_add_bus_pm_notifier(struct acpi_device
*dev
)
871 return acpi_add_pm_notifier(dev
, NULL
, pci_acpi_wake_bus
);
875 * pci_acpi_add_pm_notifier - Register PM notifier for given PCI device.
876 * @dev: ACPI device to add the notifier for.
877 * @pci_dev: PCI device to check for the PME status if an event is signaled.
879 acpi_status
pci_acpi_add_pm_notifier(struct acpi_device
*dev
,
880 struct pci_dev
*pci_dev
)
882 return acpi_add_pm_notifier(dev
, &pci_dev
->dev
, pci_acpi_wake_dev
);
886 * _SxD returns the D-state with the highest power
887 * (lowest D-state number) supported in the S-state "x".
889 * If the devices does not have a _PRW
890 * (Power Resources for Wake) supporting system wakeup from "x"
891 * then the OS is free to choose a lower power (higher number
892 * D-state) than the return value from _SxD.
894 * But if _PRW is enabled at S-state "x", the OS
895 * must not choose a power lower than _SxD --
896 * unless the device has an _SxW method specifying
897 * the lowest power (highest D-state number) the device
898 * may enter while still able to wake the system.
900 * ie. depending on global OS policy:
902 * if (_PRW at S-state x)
903 * choose from highest power _SxD to lowest power _SxW
904 * else // no _PRW at S-state x
905 * choose highest power _SxD or any lower power
908 static pci_power_t
acpi_pci_choose_state(struct pci_dev
*pdev
)
910 int acpi_state
, d_max
;
913 d_max
= ACPI_STATE_D3_HOT
;
915 d_max
= ACPI_STATE_D3_COLD
;
916 acpi_state
= acpi_pm_device_sleep_state(&pdev
->dev
, NULL
, d_max
);
918 return PCI_POWER_ERROR
;
920 switch (acpi_state
) {
927 case ACPI_STATE_D3_HOT
:
929 case ACPI_STATE_D3_COLD
:
932 return PCI_POWER_ERROR
;
935 static struct acpi_device
*acpi_pci_find_companion(struct device
*dev
);
937 static bool acpi_pci_bridge_d3(struct pci_dev
*dev
)
939 const struct fwnode_handle
*fwnode
;
940 struct acpi_device
*adev
;
941 struct pci_dev
*root
;
944 if (!dev
->is_hotplug_bridge
)
948 * Look for a special _DSD property for the root port and if it
949 * is set we know the hierarchy behind it supports D3 just fine.
951 root
= pci_find_pcie_root_port(dev
);
955 adev
= ACPI_COMPANION(&root
->dev
);
958 * It is possible that the ACPI companion is not yet bound
959 * for the root port so look it up manually here.
961 if (!adev
&& !pci_dev_is_added(root
))
962 adev
= acpi_pci_find_companion(&root
->dev
);
968 fwnode
= acpi_fwnode_handle(adev
);
969 if (fwnode_property_read_u8(fwnode
, "HotPlugSupportInD3", &val
))
975 static bool acpi_pci_power_manageable(struct pci_dev
*dev
)
977 struct acpi_device
*adev
= ACPI_COMPANION(&dev
->dev
);
978 return adev
? acpi_device_power_manageable(adev
) : false;
981 static int acpi_pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
983 struct acpi_device
*adev
= ACPI_COMPANION(&dev
->dev
);
984 static const u8 state_conv
[] = {
985 [PCI_D0
] = ACPI_STATE_D0
,
986 [PCI_D1
] = ACPI_STATE_D1
,
987 [PCI_D2
] = ACPI_STATE_D2
,
988 [PCI_D3hot
] = ACPI_STATE_D3_HOT
,
989 [PCI_D3cold
] = ACPI_STATE_D3_COLD
,
993 /* If the ACPI device has _EJ0, ignore the device */
994 if (!adev
|| acpi_has_method(adev
->handle
, "_EJ0"))
999 if (dev_pm_qos_flags(&dev
->dev
, PM_QOS_FLAG_NO_POWER_OFF
) ==
1009 error
= acpi_device_set_power(adev
, state_conv
[state
]);
1013 pci_dbg(dev
, "power state changed by ACPI to %s\n",
1014 acpi_power_state_string(state_conv
[state
]));
1019 static pci_power_t
acpi_pci_get_power_state(struct pci_dev
*dev
)
1021 struct acpi_device
*adev
= ACPI_COMPANION(&dev
->dev
);
1022 static const pci_power_t state_conv
[] = {
1023 [ACPI_STATE_D0
] = PCI_D0
,
1024 [ACPI_STATE_D1
] = PCI_D1
,
1025 [ACPI_STATE_D2
] = PCI_D2
,
1026 [ACPI_STATE_D3_HOT
] = PCI_D3hot
,
1027 [ACPI_STATE_D3_COLD
] = PCI_D3cold
,
1031 if (!adev
|| !acpi_device_power_manageable(adev
))
1034 state
= adev
->power
.state
;
1035 if (state
== ACPI_STATE_UNKNOWN
)
1038 return state_conv
[state
];
1041 static void acpi_pci_refresh_power_state(struct pci_dev
*dev
)
1043 struct acpi_device
*adev
= ACPI_COMPANION(&dev
->dev
);
1045 if (adev
&& acpi_device_power_manageable(adev
))
1046 acpi_device_update_power(adev
, NULL
);
1049 static int acpi_pci_propagate_wakeup(struct pci_bus
*bus
, bool enable
)
1051 while (bus
->parent
) {
1052 if (acpi_pm_device_can_wakeup(&bus
->self
->dev
))
1053 return acpi_pm_set_bridge_wakeup(&bus
->self
->dev
, enable
);
1058 /* We have reached the root bus. */
1060 if (acpi_pm_device_can_wakeup(bus
->bridge
))
1061 return acpi_pm_set_bridge_wakeup(bus
->bridge
, enable
);
1066 static int acpi_pci_wakeup(struct pci_dev
*dev
, bool enable
)
1068 if (acpi_pm_device_can_wakeup(&dev
->dev
))
1069 return acpi_pm_set_device_wakeup(&dev
->dev
, enable
);
1071 return acpi_pci_propagate_wakeup(dev
->bus
, enable
);
1074 static bool acpi_pci_need_resume(struct pci_dev
*dev
)
1076 struct acpi_device
*adev
= ACPI_COMPANION(&dev
->dev
);
1079 * In some cases (eg. Samsung 305V4A) leaving a bridge in suspend over
1080 * system-wide suspend/resume confuses the platform firmware, so avoid
1081 * doing that. According to Section 16.1.6 of ACPI 6.2, endpoint
1082 * devices are expected to be in D3 before invoking the S3 entry path
1083 * from the firmware, so they should not be affected by this issue.
1085 if (pci_is_bridge(dev
) && acpi_target_system_state() != ACPI_STATE_S0
)
1088 if (!adev
|| !acpi_device_power_manageable(adev
))
1091 if (adev
->wakeup
.flags
.valid
&&
1092 device_may_wakeup(&dev
->dev
) != !!adev
->wakeup
.prepare_count
)
1095 if (acpi_target_system_state() == ACPI_STATE_S0
)
1098 return !!adev
->power
.flags
.dsw_present
;
1101 static const struct pci_platform_pm_ops acpi_pci_platform_pm
= {
1102 .bridge_d3
= acpi_pci_bridge_d3
,
1103 .is_manageable
= acpi_pci_power_manageable
,
1104 .set_state
= acpi_pci_set_power_state
,
1105 .get_state
= acpi_pci_get_power_state
,
1106 .refresh_state
= acpi_pci_refresh_power_state
,
1107 .choose_state
= acpi_pci_choose_state
,
1108 .set_wakeup
= acpi_pci_wakeup
,
1109 .need_resume
= acpi_pci_need_resume
,
1112 void acpi_pci_add_bus(struct pci_bus
*bus
)
1114 union acpi_object
*obj
;
1115 struct pci_host_bridge
*bridge
;
1117 if (acpi_pci_disabled
|| !bus
->bridge
|| !ACPI_HANDLE(bus
->bridge
))
1120 acpi_pci_slot_enumerate(bus
);
1121 acpiphp_enumerate_slots(bus
);
1124 * For a host bridge, check its _DSM for function 8 and if
1125 * that is available, mark it in pci_host_bridge.
1127 if (!pci_is_root_bus(bus
))
1130 obj
= acpi_evaluate_dsm(ACPI_HANDLE(bus
->bridge
), &pci_acpi_dsm_guid
, 3,
1131 RESET_DELAY_DSM
, NULL
);
1135 if (obj
->type
== ACPI_TYPE_INTEGER
&& obj
->integer
.value
== 1) {
1136 bridge
= pci_find_host_bridge(bus
);
1137 bridge
->ignore_reset_delay
= 1;
1142 void acpi_pci_remove_bus(struct pci_bus
*bus
)
1144 if (acpi_pci_disabled
|| !bus
->bridge
)
1147 acpiphp_remove_slots(bus
);
1148 acpi_pci_slot_remove(bus
);
1152 static struct acpi_device
*acpi_pci_find_companion(struct device
*dev
)
1154 struct pci_dev
*pci_dev
= to_pci_dev(dev
);
1155 bool check_children
;
1158 check_children
= pci_is_bridge(pci_dev
);
1159 /* Please ref to ACPI spec for the syntax of _ADR */
1160 addr
= (PCI_SLOT(pci_dev
->devfn
) << 16) | PCI_FUNC(pci_dev
->devfn
);
1161 return acpi_find_child_device(ACPI_COMPANION(dev
->parent
), addr
,
1166 * pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI
1167 * @pdev: the PCI device whose delay is to be updated
1168 * @handle: ACPI handle of this device
1170 * Update the d3_delay and d3cold_delay of a PCI device from the ACPI _DSM
1171 * control method of either the device itself or the PCI host bridge.
1173 * Function 8, "Reset Delay," applies to the entire hierarchy below a PCI
1174 * host bridge. If it returns one, the OS may assume that all devices in
1175 * the hierarchy have already completed power-on reset delays.
1177 * Function 9, "Device Readiness Durations," applies only to the object
1178 * where it is located. It returns delay durations required after various
1179 * events if the device requires less time than the spec requires. Delays
1180 * from this function take precedence over the Reset Delay function.
1182 * These _DSM functions are defined by the draft ECN of January 28, 2014,
1183 * titled "ACPI additions for FW latency optimizations."
1185 static void pci_acpi_optimize_delay(struct pci_dev
*pdev
,
1188 struct pci_host_bridge
*bridge
= pci_find_host_bridge(pdev
->bus
);
1190 union acpi_object
*obj
, *elements
;
1192 if (bridge
->ignore_reset_delay
)
1193 pdev
->d3cold_delay
= 0;
1195 obj
= acpi_evaluate_dsm(handle
, &pci_acpi_dsm_guid
, 3,
1196 FUNCTION_DELAY_DSM
, NULL
);
1200 if (obj
->type
== ACPI_TYPE_PACKAGE
&& obj
->package
.count
== 5) {
1201 elements
= obj
->package
.elements
;
1202 if (elements
[0].type
== ACPI_TYPE_INTEGER
) {
1203 value
= (int)elements
[0].integer
.value
/ 1000;
1204 if (value
< PCI_PM_D3COLD_WAIT
)
1205 pdev
->d3cold_delay
= value
;
1207 if (elements
[3].type
== ACPI_TYPE_INTEGER
) {
1208 value
= (int)elements
[3].integer
.value
/ 1000;
1209 if (value
< PCI_PM_D3_WAIT
)
1210 pdev
->d3_delay
= value
;
1216 static void pci_acpi_set_untrusted(struct pci_dev
*dev
)
1220 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
1222 if (device_property_read_u8(&dev
->dev
, "ExternalFacingPort", &val
))
1226 * These root ports expose PCIe (including DMA) outside of the
1227 * system so make sure we treat them and everything behind as
1234 static void pci_acpi_setup(struct device
*dev
)
1236 struct pci_dev
*pci_dev
= to_pci_dev(dev
);
1237 struct acpi_device
*adev
= ACPI_COMPANION(dev
);
1242 pci_acpi_optimize_delay(pci_dev
, adev
->handle
);
1243 pci_acpi_set_untrusted(pci_dev
);
1244 pci_acpi_add_edr_notifier(pci_dev
);
1246 pci_acpi_add_pm_notifier(adev
, pci_dev
);
1247 if (!adev
->wakeup
.flags
.valid
)
1250 device_set_wakeup_capable(dev
, true);
1252 * For bridges that can do D3 we enable wake automatically (as
1253 * we do for the power management itself in that case). The
1254 * reason is that the bridge may have additional methods such as
1255 * _DSW that need to be called.
1257 if (pci_dev
->bridge_d3
)
1258 device_wakeup_enable(dev
);
1260 acpi_pci_wakeup(pci_dev
, false);
1261 acpi_device_power_add_dependent(adev
, dev
);
1264 static void pci_acpi_cleanup(struct device
*dev
)
1266 struct acpi_device
*adev
= ACPI_COMPANION(dev
);
1267 struct pci_dev
*pci_dev
= to_pci_dev(dev
);
1272 pci_acpi_remove_edr_notifier(pci_dev
);
1273 pci_acpi_remove_pm_notifier(adev
);
1274 if (adev
->wakeup
.flags
.valid
) {
1275 acpi_device_power_remove_dependent(adev
, dev
);
1276 if (pci_dev
->bridge_d3
)
1277 device_wakeup_disable(dev
);
1279 device_set_wakeup_capable(dev
, false);
1283 static bool pci_acpi_bus_match(struct device
*dev
)
1285 return dev_is_pci(dev
);
1288 static struct acpi_bus_type acpi_pci_bus
= {
1290 .match
= pci_acpi_bus_match
,
1291 .find_companion
= acpi_pci_find_companion
,
1292 .setup
= pci_acpi_setup
,
1293 .cleanup
= pci_acpi_cleanup
,
1297 static struct fwnode_handle
*(*pci_msi_get_fwnode_cb
)(struct device
*dev
);
1300 * pci_msi_register_fwnode_provider - Register callback to retrieve fwnode
1301 * @fn: Callback matching a device to a fwnode that identifies a PCI
1304 * This should be called by irqchip driver, which is the parent of
1305 * the MSI domain to provide callback interface to query fwnode.
1308 pci_msi_register_fwnode_provider(struct fwnode_handle
*(*fn
)(struct device
*))
1310 pci_msi_get_fwnode_cb
= fn
;
1314 * pci_host_bridge_acpi_msi_domain - Retrieve MSI domain of a PCI host bridge
1315 * @bus: The PCI host bridge bus.
1317 * This function uses the callback function registered by
1318 * pci_msi_register_fwnode_provider() to retrieve the irq_domain with
1319 * type DOMAIN_BUS_PCI_MSI of the specified host bridge bus.
1320 * This returns NULL on error or when the domain is not found.
1322 struct irq_domain
*pci_host_bridge_acpi_msi_domain(struct pci_bus
*bus
)
1324 struct fwnode_handle
*fwnode
;
1326 if (!pci_msi_get_fwnode_cb
)
1329 fwnode
= pci_msi_get_fwnode_cb(&bus
->dev
);
1333 return irq_find_matching_fwnode(fwnode
, DOMAIN_BUS_PCI_MSI
);
1336 static int __init
acpi_pci_init(void)
1340 if (acpi_gbl_FADT
.boot_flags
& ACPI_FADT_NO_MSI
) {
1341 pr_info("ACPI FADT declares the system doesn't support MSI, so disable it\n");
1345 if (acpi_gbl_FADT
.boot_flags
& ACPI_FADT_NO_ASPM
) {
1346 pr_info("ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n");
1350 ret
= register_acpi_bus_type(&acpi_pci_bus
);
1354 pci_set_platform_pm(&acpi_pci_platform_pm
);
1355 acpi_pci_slot_init();
1360 arch_initcall(acpi_pci_init
);