gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / pci / probe.c
blob77b8a145c39b813f34f845486fe6dce9ab183b4b
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCI detection and setup code
4 */
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/msi.h>
11 #include <linux/of_device.h>
12 #include <linux/of_pci.h>
13 #include <linux/pci_hotplug.h>
14 #include <linux/slab.h>
15 #include <linux/module.h>
16 #include <linux/cpumask.h>
17 #include <linux/aer.h>
18 #include <linux/acpi.h>
19 #include <linux/hypervisor.h>
20 #include <linux/irqdomain.h>
21 #include <linux/pm_runtime.h>
22 #include "pci.h"
24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25 #define CARDBUS_RESERVE_BUSNR 3
27 static struct resource busn_resource = {
28 .name = "PCI busn",
29 .start = 0,
30 .end = 255,
31 .flags = IORESOURCE_BUS,
34 /* Ugh. Need to stop exporting this to modules. */
35 LIST_HEAD(pci_root_buses);
36 EXPORT_SYMBOL(pci_root_buses);
38 static LIST_HEAD(pci_domain_busn_res_list);
40 struct pci_domain_busn_res {
41 struct list_head list;
42 struct resource res;
43 int domain_nr;
46 static struct resource *get_pci_domain_busn_res(int domain_nr)
48 struct pci_domain_busn_res *r;
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
52 return &r->res;
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 if (!r)
56 return NULL;
58 r->domain_nr = domain_nr;
59 r->res.start = 0;
60 r->res.end = 0xff;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
65 return &r->res;
69 * Some device drivers need know if PCI is initiated.
70 * Basically, we think PCI is not initiated when there
71 * is no device to be found on the pci_bus_type.
73 int no_pci_devices(void)
75 struct device *dev;
76 int no_devices;
78 dev = bus_find_next_device(&pci_bus_type, NULL);
79 no_devices = (dev == NULL);
80 put_device(dev);
81 return no_devices;
83 EXPORT_SYMBOL(no_pci_devices);
86 * PCI Bus Class
88 static void release_pcibus_dev(struct device *dev)
90 struct pci_bus *pci_bus = to_pci_bus(dev);
92 put_device(pci_bus->bridge);
93 pci_bus_remove_resources(pci_bus);
94 pci_release_bus_of_node(pci_bus);
95 kfree(pci_bus);
98 static struct class pcibus_class = {
99 .name = "pci_bus",
100 .dev_release = &release_pcibus_dev,
101 .dev_groups = pcibus_groups,
104 static int __init pcibus_class_init(void)
106 return class_register(&pcibus_class);
108 postcore_initcall(pcibus_class_init);
110 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
112 u64 size = mask & maxbase; /* Find the significant bits */
113 if (!size)
114 return 0;
117 * Get the lowest of them to find the decode size, and from that
118 * the extent.
120 size = size & ~(size-1);
123 * base == maxbase can be valid only if the BAR has already been
124 * programmed with all 1s.
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
127 return 0;
129 return size;
132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
134 u32 mem_type;
135 unsigned long flags;
137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
139 flags |= IORESOURCE_IO;
140 return flags;
143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
144 flags |= IORESOURCE_MEM;
145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
146 flags |= IORESOURCE_PREFETCH;
148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 switch (mem_type) {
150 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 break;
152 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
153 /* 1M mem BAR treated as 32-bit BAR */
154 break;
155 case PCI_BASE_ADDRESS_MEM_TYPE_64:
156 flags |= IORESOURCE_MEM_64;
157 break;
158 default:
159 /* mem unknown type treated as 32-bit BAR */
160 break;
162 return flags;
165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
168 * pci_read_base - Read a PCI BAR
169 * @dev: the PCI device
170 * @type: type of the BAR
171 * @res: resource buffer to be filled in
172 * @pos: BAR position in the config space
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
177 struct resource *res, unsigned int pos)
179 u32 l = 0, sz = 0, mask;
180 u64 l64, sz64, mask64;
181 u16 orig_cmd;
182 struct pci_bus_region region, inverted_region;
184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186 /* No printks while decoding is disabled! */
187 if (!dev->mmio_always_on) {
188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
190 pci_write_config_word(dev, PCI_COMMAND,
191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
195 res->name = pci_name(dev);
197 pci_read_config_dword(dev, pos, &l);
198 pci_write_config_dword(dev, pos, l | mask);
199 pci_read_config_dword(dev, pos, &sz);
200 pci_write_config_dword(dev, pos, l);
203 * All bits set in sz means the device isn't working properly.
204 * If the BAR isn't implemented, all bits must be 0. If it's a
205 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
206 * 1 must be clear.
208 if (sz == 0xffffffff)
209 sz = 0;
212 * I don't know how l can have all bits set. Copied from old code.
213 * Maybe it fixes a bug on some ancient platform.
215 if (l == 0xffffffff)
216 l = 0;
218 if (type == pci_bar_unknown) {
219 res->flags = decode_bar(dev, l);
220 res->flags |= IORESOURCE_SIZEALIGN;
221 if (res->flags & IORESOURCE_IO) {
222 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
225 } else {
226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 } else {
231 if (l & PCI_ROM_ADDRESS_ENABLE)
232 res->flags |= IORESOURCE_ROM_ENABLE;
233 l64 = l & PCI_ROM_ADDRESS_MASK;
234 sz64 = sz & PCI_ROM_ADDRESS_MASK;
235 mask64 = PCI_ROM_ADDRESS_MASK;
238 if (res->flags & IORESOURCE_MEM_64) {
239 pci_read_config_dword(dev, pos + 4, &l);
240 pci_write_config_dword(dev, pos + 4, ~0);
241 pci_read_config_dword(dev, pos + 4, &sz);
242 pci_write_config_dword(dev, pos + 4, l);
244 l64 |= ((u64)l << 32);
245 sz64 |= ((u64)sz << 32);
246 mask64 |= ((u64)~0 << 32);
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252 if (!sz64)
253 goto fail;
255 sz64 = pci_size(l64, sz64, mask64);
256 if (!sz64) {
257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
258 pos);
259 goto fail;
262 if (res->flags & IORESOURCE_MEM_64) {
263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 res->start = 0;
267 res->end = 0;
268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
269 pos, (unsigned long long)sz64);
270 goto out;
273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
274 /* Above 32-bit boundary; try to reallocate */
275 res->flags |= IORESOURCE_UNSET;
276 res->start = 0;
277 res->end = sz64 - 1;
278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
279 pos, (unsigned long long)l64);
280 goto out;
284 region.start = l64;
285 region.end = l64 + sz64 - 1;
287 pcibios_bus_to_resource(dev->bus, res, &region);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
292 * the corresponding resource address (the physical address used by
293 * the CPU. Converting that resource address back to a bus address
294 * should yield the original BAR value:
296 * resource_to_bus(bus_to_resource(A)) == A
298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
299 * be claimed by the device.
301 if (inverted_region.start != region.start) {
302 res->flags |= IORESOURCE_UNSET;
303 res->start = 0;
304 res->end = region.end - region.start;
305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
306 pos, (unsigned long long)region.start);
309 goto out;
312 fail:
313 res->flags = 0;
314 out:
315 if (res->flags)
316 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
323 unsigned int pos, reg;
325 if (dev->non_compliant_bars)
326 return;
328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
329 if (dev->is_virtfn)
330 return;
332 for (pos = 0; pos < howmany; pos++) {
333 struct resource *res = &dev->resource[pos];
334 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
338 if (rom) {
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
340 dev->rom_base_reg = rom;
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
343 __pci_read_base(dev, pci_bar_mem32, res, rom);
347 static void pci_read_bridge_windows(struct pci_dev *bridge)
349 u16 io;
350 u32 pmem, tmp;
352 pci_read_config_word(bridge, PCI_IO_BASE, &io);
353 if (!io) {
354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
355 pci_read_config_word(bridge, PCI_IO_BASE, &io);
356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
358 if (io)
359 bridge->io_window = 1;
362 * DECchip 21050 pass 2 errata: the bridge may miss an address
363 * disconnect boundary by one PCI data phase. Workaround: do not
364 * use prefetching on this device.
366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
367 return;
369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
370 if (!pmem) {
371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
372 0xffe0fff0);
373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
376 if (!pmem)
377 return;
379 bridge->pref_window = 1;
381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
384 * Bridge claims to have a 64-bit prefetchable memory
385 * window; verify that the upper bits are actually
386 * writable.
388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
390 0xffffffff);
391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
393 if (tmp)
394 bridge->pref_64_window = 1;
398 static void pci_read_bridge_io(struct pci_bus *child)
400 struct pci_dev *dev = child->self;
401 u8 io_base_lo, io_limit_lo;
402 unsigned long io_mask, io_granularity, base, limit;
403 struct pci_bus_region region;
404 struct resource *res;
406 io_mask = PCI_IO_RANGE_MASK;
407 io_granularity = 0x1000;
408 if (dev->io_window_1k) {
409 /* Support 1K I/O space granularity */
410 io_mask = PCI_IO_1K_RANGE_MASK;
411 io_granularity = 0x400;
414 res = child->resource[0];
415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
417 base = (io_base_lo & io_mask) << 8;
418 limit = (io_limit_lo & io_mask) << 8;
420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
421 u16 io_base_hi, io_limit_hi;
423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
425 base |= ((unsigned long) io_base_hi << 16);
426 limit |= ((unsigned long) io_limit_hi << 16);
429 if (base <= limit) {
430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
431 region.start = base;
432 region.end = limit + io_granularity - 1;
433 pcibios_bus_to_resource(dev->bus, res, &region);
434 pci_info(dev, " bridge window %pR\n", res);
438 static void pci_read_bridge_mmio(struct pci_bus *child)
440 struct pci_dev *dev = child->self;
441 u16 mem_base_lo, mem_limit_lo;
442 unsigned long base, limit;
443 struct pci_bus_region region;
444 struct resource *res;
446 res = child->resource[1];
447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 if (base <= limit) {
452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
453 region.start = base;
454 region.end = limit + 0xfffff;
455 pcibios_bus_to_resource(dev->bus, res, &region);
456 pci_info(dev, " bridge window %pR\n", res);
460 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
462 struct pci_dev *dev = child->self;
463 u16 mem_base_lo, mem_limit_lo;
464 u64 base64, limit64;
465 pci_bus_addr_t base, limit;
466 struct pci_bus_region region;
467 struct resource *res;
469 res = child->resource[2];
470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
476 u32 mem_base_hi, mem_limit_hi;
478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
482 * Some bridges set the base > limit by default, and some
483 * (broken) BIOSes do not initialize them. If we find
484 * this, just assume they are not being used.
486 if (mem_base_hi <= mem_limit_hi) {
487 base64 |= (u64) mem_base_hi << 32;
488 limit64 |= (u64) mem_limit_hi << 32;
492 base = (pci_bus_addr_t) base64;
493 limit = (pci_bus_addr_t) limit64;
495 if (base != base64) {
496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
497 (unsigned long long) base64);
498 return;
501 if (base <= limit) {
502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
503 IORESOURCE_MEM | IORESOURCE_PREFETCH;
504 if (res->flags & PCI_PREF_RANGE_TYPE_64)
505 res->flags |= IORESOURCE_MEM_64;
506 region.start = base;
507 region.end = limit + 0xfffff;
508 pcibios_bus_to_resource(dev->bus, res, &region);
509 pci_info(dev, " bridge window %pR\n", res);
513 void pci_read_bridge_bases(struct pci_bus *child)
515 struct pci_dev *dev = child->self;
516 struct resource *res;
517 int i;
519 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
520 return;
522 pci_info(dev, "PCI bridge to %pR%s\n",
523 &child->busn_res,
524 dev->transparent ? " (subtractive decode)" : "");
526 pci_bus_remove_resources(child);
527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
530 pci_read_bridge_io(child);
531 pci_read_bridge_mmio(child);
532 pci_read_bridge_mmio_pref(child);
534 if (dev->transparent) {
535 pci_bus_for_each_resource(child->parent, res, i) {
536 if (res && res->flags) {
537 pci_bus_add_resource(child, res,
538 PCI_SUBTRACTIVE_DECODE);
539 pci_info(dev, " bridge window %pR (subtractive decode)\n",
540 res);
546 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
548 struct pci_bus *b;
550 b = kzalloc(sizeof(*b), GFP_KERNEL);
551 if (!b)
552 return NULL;
554 INIT_LIST_HEAD(&b->node);
555 INIT_LIST_HEAD(&b->children);
556 INIT_LIST_HEAD(&b->devices);
557 INIT_LIST_HEAD(&b->slots);
558 INIT_LIST_HEAD(&b->resources);
559 b->max_bus_speed = PCI_SPEED_UNKNOWN;
560 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
561 #ifdef CONFIG_PCI_DOMAINS_GENERIC
562 if (parent)
563 b->domain_nr = parent->domain_nr;
564 #endif
565 return b;
568 static void devm_pci_release_host_bridge_dev(struct device *dev)
570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
572 if (bridge->release_fn)
573 bridge->release_fn(bridge);
575 pci_free_resource_list(&bridge->windows);
576 pci_free_resource_list(&bridge->dma_ranges);
579 static void pci_release_host_bridge_dev(struct device *dev)
581 devm_pci_release_host_bridge_dev(dev);
582 kfree(to_pci_host_bridge(dev));
585 static void pci_init_host_bridge(struct pci_host_bridge *bridge)
587 INIT_LIST_HEAD(&bridge->windows);
588 INIT_LIST_HEAD(&bridge->dma_ranges);
591 * We assume we can manage these PCIe features. Some systems may
592 * reserve these for use by the platform itself, e.g., an ACPI BIOS
593 * may implement its own AER handling and use _OSC to prevent the
594 * OS from interfering.
596 bridge->native_aer = 1;
597 bridge->native_pcie_hotplug = 1;
598 bridge->native_shpc_hotplug = 1;
599 bridge->native_pme = 1;
600 bridge->native_ltr = 1;
601 bridge->native_dpc = 1;
604 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
606 struct pci_host_bridge *bridge;
608 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
609 if (!bridge)
610 return NULL;
612 pci_init_host_bridge(bridge);
613 bridge->dev.release = pci_release_host_bridge_dev;
615 return bridge;
617 EXPORT_SYMBOL(pci_alloc_host_bridge);
619 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
620 size_t priv)
622 struct pci_host_bridge *bridge;
624 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
625 if (!bridge)
626 return NULL;
628 pci_init_host_bridge(bridge);
629 bridge->dev.release = devm_pci_release_host_bridge_dev;
631 return bridge;
633 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
635 void pci_free_host_bridge(struct pci_host_bridge *bridge)
637 pci_free_resource_list(&bridge->windows);
638 pci_free_resource_list(&bridge->dma_ranges);
640 kfree(bridge);
642 EXPORT_SYMBOL(pci_free_host_bridge);
644 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
645 static const unsigned char pcix_bus_speed[] = {
646 PCI_SPEED_UNKNOWN, /* 0 */
647 PCI_SPEED_66MHz_PCIX, /* 1 */
648 PCI_SPEED_100MHz_PCIX, /* 2 */
649 PCI_SPEED_133MHz_PCIX, /* 3 */
650 PCI_SPEED_UNKNOWN, /* 4 */
651 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
652 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
653 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
654 PCI_SPEED_UNKNOWN, /* 8 */
655 PCI_SPEED_66MHz_PCIX_266, /* 9 */
656 PCI_SPEED_100MHz_PCIX_266, /* A */
657 PCI_SPEED_133MHz_PCIX_266, /* B */
658 PCI_SPEED_UNKNOWN, /* C */
659 PCI_SPEED_66MHz_PCIX_533, /* D */
660 PCI_SPEED_100MHz_PCIX_533, /* E */
661 PCI_SPEED_133MHz_PCIX_533 /* F */
664 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
665 const unsigned char pcie_link_speed[] = {
666 PCI_SPEED_UNKNOWN, /* 0 */
667 PCIE_SPEED_2_5GT, /* 1 */
668 PCIE_SPEED_5_0GT, /* 2 */
669 PCIE_SPEED_8_0GT, /* 3 */
670 PCIE_SPEED_16_0GT, /* 4 */
671 PCIE_SPEED_32_0GT, /* 5 */
672 PCI_SPEED_UNKNOWN, /* 6 */
673 PCI_SPEED_UNKNOWN, /* 7 */
674 PCI_SPEED_UNKNOWN, /* 8 */
675 PCI_SPEED_UNKNOWN, /* 9 */
676 PCI_SPEED_UNKNOWN, /* A */
677 PCI_SPEED_UNKNOWN, /* B */
678 PCI_SPEED_UNKNOWN, /* C */
679 PCI_SPEED_UNKNOWN, /* D */
680 PCI_SPEED_UNKNOWN, /* E */
681 PCI_SPEED_UNKNOWN /* F */
683 EXPORT_SYMBOL_GPL(pcie_link_speed);
685 const char *pci_speed_string(enum pci_bus_speed speed)
687 /* Indexed by the pci_bus_speed enum */
688 static const char *speed_strings[] = {
689 "33 MHz PCI", /* 0x00 */
690 "66 MHz PCI", /* 0x01 */
691 "66 MHz PCI-X", /* 0x02 */
692 "100 MHz PCI-X", /* 0x03 */
693 "133 MHz PCI-X", /* 0x04 */
694 NULL, /* 0x05 */
695 NULL, /* 0x06 */
696 NULL, /* 0x07 */
697 NULL, /* 0x08 */
698 "66 MHz PCI-X 266", /* 0x09 */
699 "100 MHz PCI-X 266", /* 0x0a */
700 "133 MHz PCI-X 266", /* 0x0b */
701 "Unknown AGP", /* 0x0c */
702 "1x AGP", /* 0x0d */
703 "2x AGP", /* 0x0e */
704 "4x AGP", /* 0x0f */
705 "8x AGP", /* 0x10 */
706 "66 MHz PCI-X 533", /* 0x11 */
707 "100 MHz PCI-X 533", /* 0x12 */
708 "133 MHz PCI-X 533", /* 0x13 */
709 "2.5 GT/s PCIe", /* 0x14 */
710 "5.0 GT/s PCIe", /* 0x15 */
711 "8.0 GT/s PCIe", /* 0x16 */
712 "16.0 GT/s PCIe", /* 0x17 */
713 "32.0 GT/s PCIe", /* 0x18 */
716 if (speed < ARRAY_SIZE(speed_strings))
717 return speed_strings[speed];
718 return "Unknown";
720 EXPORT_SYMBOL_GPL(pci_speed_string);
722 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
724 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
726 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
728 static unsigned char agp_speeds[] = {
729 AGP_UNKNOWN,
730 AGP_1X,
731 AGP_2X,
732 AGP_4X,
733 AGP_8X
736 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
738 int index = 0;
740 if (agpstat & 4)
741 index = 3;
742 else if (agpstat & 2)
743 index = 2;
744 else if (agpstat & 1)
745 index = 1;
746 else
747 goto out;
749 if (agp3) {
750 index += 2;
751 if (index == 5)
752 index = 0;
755 out:
756 return agp_speeds[index];
759 static void pci_set_bus_speed(struct pci_bus *bus)
761 struct pci_dev *bridge = bus->self;
762 int pos;
764 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
765 if (!pos)
766 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
767 if (pos) {
768 u32 agpstat, agpcmd;
770 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
771 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
773 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
774 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
777 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
778 if (pos) {
779 u16 status;
780 enum pci_bus_speed max;
782 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
783 &status);
785 if (status & PCI_X_SSTATUS_533MHZ) {
786 max = PCI_SPEED_133MHz_PCIX_533;
787 } else if (status & PCI_X_SSTATUS_266MHZ) {
788 max = PCI_SPEED_133MHz_PCIX_266;
789 } else if (status & PCI_X_SSTATUS_133MHZ) {
790 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
791 max = PCI_SPEED_133MHz_PCIX_ECC;
792 else
793 max = PCI_SPEED_133MHz_PCIX;
794 } else {
795 max = PCI_SPEED_66MHz_PCIX;
798 bus->max_bus_speed = max;
799 bus->cur_bus_speed = pcix_bus_speed[
800 (status & PCI_X_SSTATUS_FREQ) >> 6];
802 return;
805 if (pci_is_pcie(bridge)) {
806 u32 linkcap;
807 u16 linksta;
809 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
810 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
811 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
813 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
814 pcie_update_link_speed(bus, linksta);
818 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
820 struct irq_domain *d;
823 * Any firmware interface that can resolve the msi_domain
824 * should be called from here.
826 d = pci_host_bridge_of_msi_domain(bus);
827 if (!d)
828 d = pci_host_bridge_acpi_msi_domain(bus);
830 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
832 * If no IRQ domain was found via the OF tree, try looking it up
833 * directly through the fwnode_handle.
835 if (!d) {
836 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
838 if (fwnode)
839 d = irq_find_matching_fwnode(fwnode,
840 DOMAIN_BUS_PCI_MSI);
842 #endif
844 return d;
847 static void pci_set_bus_msi_domain(struct pci_bus *bus)
849 struct irq_domain *d;
850 struct pci_bus *b;
853 * The bus can be a root bus, a subordinate bus, or a virtual bus
854 * created by an SR-IOV device. Walk up to the first bridge device
855 * found or derive the domain from the host bridge.
857 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
858 if (b->self)
859 d = dev_get_msi_domain(&b->self->dev);
862 if (!d)
863 d = pci_host_bridge_msi_domain(b);
865 dev_set_msi_domain(&bus->dev, d);
868 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
870 struct device *parent = bridge->dev.parent;
871 struct resource_entry *window, *n;
872 struct pci_bus *bus, *b;
873 resource_size_t offset;
874 LIST_HEAD(resources);
875 struct resource *res;
876 char addr[64], *fmt;
877 const char *name;
878 int err;
880 bus = pci_alloc_bus(NULL);
881 if (!bus)
882 return -ENOMEM;
884 bridge->bus = bus;
886 /* Temporarily move resources off the list */
887 list_splice_init(&bridge->windows, &resources);
888 bus->sysdata = bridge->sysdata;
889 bus->msi = bridge->msi;
890 bus->ops = bridge->ops;
891 bus->number = bus->busn_res.start = bridge->busnr;
892 #ifdef CONFIG_PCI_DOMAINS_GENERIC
893 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
894 #endif
896 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
897 if (b) {
898 /* Ignore it if we already got here via a different bridge */
899 dev_dbg(&b->dev, "bus already known\n");
900 err = -EEXIST;
901 goto free;
904 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
905 bridge->busnr);
907 err = pcibios_root_bridge_prepare(bridge);
908 if (err)
909 goto free;
911 err = device_register(&bridge->dev);
912 if (err)
913 put_device(&bridge->dev);
915 bus->bridge = get_device(&bridge->dev);
916 device_enable_async_suspend(bus->bridge);
917 pci_set_bus_of_node(bus);
918 pci_set_bus_msi_domain(bus);
920 if (!parent)
921 set_dev_node(bus->bridge, pcibus_to_node(bus));
923 bus->dev.class = &pcibus_class;
924 bus->dev.parent = bus->bridge;
926 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
927 name = dev_name(&bus->dev);
929 err = device_register(&bus->dev);
930 if (err)
931 goto unregister;
933 pcibios_add_bus(bus);
935 /* Create legacy_io and legacy_mem files for this bus */
936 pci_create_legacy_files(bus);
938 if (parent)
939 dev_info(parent, "PCI host bridge to bus %s\n", name);
940 else
941 pr_info("PCI host bridge to bus %s\n", name);
943 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
944 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
946 /* Add initial resources to the bus */
947 resource_list_for_each_entry_safe(window, n, &resources) {
948 list_move_tail(&window->node, &bridge->windows);
949 offset = window->offset;
950 res = window->res;
952 if (res->flags & IORESOURCE_BUS)
953 pci_bus_insert_busn_res(bus, bus->number, res->end);
954 else
955 pci_bus_add_resource(bus, res, 0);
957 if (offset) {
958 if (resource_type(res) == IORESOURCE_IO)
959 fmt = " (bus address [%#06llx-%#06llx])";
960 else
961 fmt = " (bus address [%#010llx-%#010llx])";
963 snprintf(addr, sizeof(addr), fmt,
964 (unsigned long long)(res->start - offset),
965 (unsigned long long)(res->end - offset));
966 } else
967 addr[0] = '\0';
969 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
972 down_write(&pci_bus_sem);
973 list_add_tail(&bus->node, &pci_root_buses);
974 up_write(&pci_bus_sem);
976 return 0;
978 unregister:
979 put_device(&bridge->dev);
980 device_unregister(&bridge->dev);
982 free:
983 kfree(bus);
984 return err;
987 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
989 int pos;
990 u32 status;
993 * If extended config space isn't accessible on a bridge's primary
994 * bus, we certainly can't access it on the secondary bus.
996 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
997 return false;
1000 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1001 * extended config space is accessible on the primary, it's also
1002 * accessible on the secondary.
1004 if (pci_is_pcie(bridge) &&
1005 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1006 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1007 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1008 return true;
1011 * For the other bridge types:
1012 * - PCI-to-PCI bridges
1013 * - PCIe-to-PCI/PCI-X forward bridges
1014 * - PCI/PCI-X-to-PCIe reverse bridges
1015 * extended config space on the secondary side is only accessible
1016 * if the bridge supports PCI-X Mode 2.
1018 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1019 if (!pos)
1020 return false;
1022 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1023 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1026 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1027 struct pci_dev *bridge, int busnr)
1029 struct pci_bus *child;
1030 int i;
1031 int ret;
1033 /* Allocate a new bus and inherit stuff from the parent */
1034 child = pci_alloc_bus(parent);
1035 if (!child)
1036 return NULL;
1038 child->parent = parent;
1039 child->ops = parent->ops;
1040 child->msi = parent->msi;
1041 child->sysdata = parent->sysdata;
1042 child->bus_flags = parent->bus_flags;
1045 * Initialize some portions of the bus device, but don't register
1046 * it now as the parent is not properly set up yet.
1048 child->dev.class = &pcibus_class;
1049 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1051 /* Set up the primary, secondary and subordinate bus numbers */
1052 child->number = child->busn_res.start = busnr;
1053 child->primary = parent->busn_res.start;
1054 child->busn_res.end = 0xff;
1056 if (!bridge) {
1057 child->dev.parent = parent->bridge;
1058 goto add_dev;
1061 child->self = bridge;
1062 child->bridge = get_device(&bridge->dev);
1063 child->dev.parent = child->bridge;
1064 pci_set_bus_of_node(child);
1065 pci_set_bus_speed(child);
1068 * Check whether extended config space is accessible on the child
1069 * bus. Note that we currently assume it is always accessible on
1070 * the root bus.
1072 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1073 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1074 pci_info(child, "extended config space not accessible\n");
1077 /* Set up default resource pointers and names */
1078 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1079 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1080 child->resource[i]->name = child->name;
1082 bridge->subordinate = child;
1084 add_dev:
1085 pci_set_bus_msi_domain(child);
1086 ret = device_register(&child->dev);
1087 WARN_ON(ret < 0);
1089 pcibios_add_bus(child);
1091 if (child->ops->add_bus) {
1092 ret = child->ops->add_bus(child);
1093 if (WARN_ON(ret < 0))
1094 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1097 /* Create legacy_io and legacy_mem files for this bus */
1098 pci_create_legacy_files(child);
1100 return child;
1103 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1104 int busnr)
1106 struct pci_bus *child;
1108 child = pci_alloc_child_bus(parent, dev, busnr);
1109 if (child) {
1110 down_write(&pci_bus_sem);
1111 list_add_tail(&child->node, &parent->children);
1112 up_write(&pci_bus_sem);
1114 return child;
1116 EXPORT_SYMBOL(pci_add_new_bus);
1118 static void pci_enable_crs(struct pci_dev *pdev)
1120 u16 root_cap = 0;
1122 /* Enable CRS Software Visibility if supported */
1123 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1124 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1125 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1126 PCI_EXP_RTCTL_CRSSVE);
1129 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1130 unsigned int available_buses);
1132 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1133 * numbers from EA capability.
1134 * @dev: Bridge
1135 * @sec: updated with secondary bus number from EA
1136 * @sub: updated with subordinate bus number from EA
1138 * If @dev is a bridge with EA capability that specifies valid secondary
1139 * and subordinate bus numbers, return true with the bus numbers in @sec
1140 * and @sub. Otherwise return false.
1142 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1144 int ea, offset;
1145 u32 dw;
1146 u8 ea_sec, ea_sub;
1148 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1149 return false;
1151 /* find PCI EA capability in list */
1152 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1153 if (!ea)
1154 return false;
1156 offset = ea + PCI_EA_FIRST_ENT;
1157 pci_read_config_dword(dev, offset, &dw);
1158 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1159 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1160 if (ea_sec == 0 || ea_sub < ea_sec)
1161 return false;
1163 *sec = ea_sec;
1164 *sub = ea_sub;
1165 return true;
1169 * pci_scan_bridge_extend() - Scan buses behind a bridge
1170 * @bus: Parent bus the bridge is on
1171 * @dev: Bridge itself
1172 * @max: Starting subordinate number of buses behind this bridge
1173 * @available_buses: Total number of buses available for this bridge and
1174 * the devices below. After the minimal bus space has
1175 * been allocated the remaining buses will be
1176 * distributed equally between hotplug-capable bridges.
1177 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1178 * that need to be reconfigured.
1180 * If it's a bridge, configure it and scan the bus behind it.
1181 * For CardBus bridges, we don't scan behind as the devices will
1182 * be handled by the bridge driver itself.
1184 * We need to process bridges in two passes -- first we scan those
1185 * already configured by the BIOS and after we are done with all of
1186 * them, we proceed to assigning numbers to the remaining buses in
1187 * order to avoid overlaps between old and new bus numbers.
1189 * Return: New subordinate number covering all buses behind this bridge.
1191 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1192 int max, unsigned int available_buses,
1193 int pass)
1195 struct pci_bus *child;
1196 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1197 u32 buses, i, j = 0;
1198 u16 bctl;
1199 u8 primary, secondary, subordinate;
1200 int broken = 0;
1201 bool fixed_buses;
1202 u8 fixed_sec, fixed_sub;
1203 int next_busnr;
1206 * Make sure the bridge is powered on to be able to access config
1207 * space of devices below it.
1209 pm_runtime_get_sync(&dev->dev);
1211 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1212 primary = buses & 0xFF;
1213 secondary = (buses >> 8) & 0xFF;
1214 subordinate = (buses >> 16) & 0xFF;
1216 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1217 secondary, subordinate, pass);
1219 if (!primary && (primary != bus->number) && secondary && subordinate) {
1220 pci_warn(dev, "Primary bus is hard wired to 0\n");
1221 primary = bus->number;
1224 /* Check if setup is sensible at all */
1225 if (!pass &&
1226 (primary != bus->number || secondary <= bus->number ||
1227 secondary > subordinate)) {
1228 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1229 secondary, subordinate);
1230 broken = 1;
1234 * Disable Master-Abort Mode during probing to avoid reporting of
1235 * bus errors in some architectures.
1237 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1238 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1239 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1241 pci_enable_crs(dev);
1243 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1244 !is_cardbus && !broken) {
1245 unsigned int cmax;
1248 * Bus already configured by firmware, process it in the
1249 * first pass and just note the configuration.
1251 if (pass)
1252 goto out;
1255 * The bus might already exist for two reasons: Either we
1256 * are rescanning the bus or the bus is reachable through
1257 * more than one bridge. The second case can happen with
1258 * the i450NX chipset.
1260 child = pci_find_bus(pci_domain_nr(bus), secondary);
1261 if (!child) {
1262 child = pci_add_new_bus(bus, dev, secondary);
1263 if (!child)
1264 goto out;
1265 child->primary = primary;
1266 pci_bus_insert_busn_res(child, secondary, subordinate);
1267 child->bridge_ctl = bctl;
1270 cmax = pci_scan_child_bus(child);
1271 if (cmax > subordinate)
1272 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1273 subordinate, cmax);
1275 /* Subordinate should equal child->busn_res.end */
1276 if (subordinate > max)
1277 max = subordinate;
1278 } else {
1281 * We need to assign a number to this bus which we always
1282 * do in the second pass.
1284 if (!pass) {
1285 if (pcibios_assign_all_busses() || broken || is_cardbus)
1288 * Temporarily disable forwarding of the
1289 * configuration cycles on all bridges in
1290 * this bus segment to avoid possible
1291 * conflicts in the second pass between two
1292 * bridges programmed with overlapping bus
1293 * ranges.
1295 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1296 buses & ~0xffffff);
1297 goto out;
1300 /* Clear errors */
1301 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1303 /* Read bus numbers from EA Capability (if present) */
1304 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1305 if (fixed_buses)
1306 next_busnr = fixed_sec;
1307 else
1308 next_busnr = max + 1;
1311 * Prevent assigning a bus number that already exists.
1312 * This can happen when a bridge is hot-plugged, so in this
1313 * case we only re-scan this bus.
1315 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1316 if (!child) {
1317 child = pci_add_new_bus(bus, dev, next_busnr);
1318 if (!child)
1319 goto out;
1320 pci_bus_insert_busn_res(child, next_busnr,
1321 bus->busn_res.end);
1323 max++;
1324 if (available_buses)
1325 available_buses--;
1327 buses = (buses & 0xff000000)
1328 | ((unsigned int)(child->primary) << 0)
1329 | ((unsigned int)(child->busn_res.start) << 8)
1330 | ((unsigned int)(child->busn_res.end) << 16);
1333 * yenta.c forces a secondary latency timer of 176.
1334 * Copy that behaviour here.
1336 if (is_cardbus) {
1337 buses &= ~0xff000000;
1338 buses |= CARDBUS_LATENCY_TIMER << 24;
1341 /* We need to blast all three values with a single write */
1342 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1344 if (!is_cardbus) {
1345 child->bridge_ctl = bctl;
1346 max = pci_scan_child_bus_extend(child, available_buses);
1347 } else {
1350 * For CardBus bridges, we leave 4 bus numbers as
1351 * cards with a PCI-to-PCI bridge can be inserted
1352 * later.
1354 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1355 struct pci_bus *parent = bus;
1356 if (pci_find_bus(pci_domain_nr(bus),
1357 max+i+1))
1358 break;
1359 while (parent->parent) {
1360 if ((!pcibios_assign_all_busses()) &&
1361 (parent->busn_res.end > max) &&
1362 (parent->busn_res.end <= max+i)) {
1363 j = 1;
1365 parent = parent->parent;
1367 if (j) {
1370 * Often, there are two CardBus
1371 * bridges -- try to leave one
1372 * valid bus number for each one.
1374 i /= 2;
1375 break;
1378 max += i;
1382 * Set subordinate bus number to its real value.
1383 * If fixed subordinate bus number exists from EA
1384 * capability then use it.
1386 if (fixed_buses)
1387 max = fixed_sub;
1388 pci_bus_update_busn_res_end(child, max);
1389 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1392 sprintf(child->name,
1393 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1394 pci_domain_nr(bus), child->number);
1396 /* Check that all devices are accessible */
1397 while (bus->parent) {
1398 if ((child->busn_res.end > bus->busn_res.end) ||
1399 (child->number > bus->busn_res.end) ||
1400 (child->number < bus->number) ||
1401 (child->busn_res.end < bus->number)) {
1402 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1403 &child->busn_res);
1404 break;
1406 bus = bus->parent;
1409 out:
1410 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1412 pm_runtime_put(&dev->dev);
1414 return max;
1418 * pci_scan_bridge() - Scan buses behind a bridge
1419 * @bus: Parent bus the bridge is on
1420 * @dev: Bridge itself
1421 * @max: Starting subordinate number of buses behind this bridge
1422 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1423 * that need to be reconfigured.
1425 * If it's a bridge, configure it and scan the bus behind it.
1426 * For CardBus bridges, we don't scan behind as the devices will
1427 * be handled by the bridge driver itself.
1429 * We need to process bridges in two passes -- first we scan those
1430 * already configured by the BIOS and after we are done with all of
1431 * them, we proceed to assigning numbers to the remaining buses in
1432 * order to avoid overlaps between old and new bus numbers.
1434 * Return: New subordinate number covering all buses behind this bridge.
1436 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1438 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1440 EXPORT_SYMBOL(pci_scan_bridge);
1443 * Read interrupt line and base address registers.
1444 * The architecture-dependent code can tweak these, of course.
1446 static void pci_read_irq(struct pci_dev *dev)
1448 unsigned char irq;
1450 /* VFs are not allowed to use INTx, so skip the config reads */
1451 if (dev->is_virtfn) {
1452 dev->pin = 0;
1453 dev->irq = 0;
1454 return;
1457 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1458 dev->pin = irq;
1459 if (irq)
1460 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1461 dev->irq = irq;
1464 void set_pcie_port_type(struct pci_dev *pdev)
1466 int pos;
1467 u16 reg16;
1468 int type;
1469 struct pci_dev *parent;
1471 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1472 if (!pos)
1473 return;
1475 pdev->pcie_cap = pos;
1476 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1477 pdev->pcie_flags_reg = reg16;
1478 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1479 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1481 parent = pci_upstream_bridge(pdev);
1482 if (!parent)
1483 return;
1486 * Some systems do not identify their upstream/downstream ports
1487 * correctly so detect impossible configurations here and correct
1488 * the port type accordingly.
1490 type = pci_pcie_type(pdev);
1491 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1493 * If pdev claims to be downstream port but the parent
1494 * device is also downstream port assume pdev is actually
1495 * upstream port.
1497 if (pcie_downstream_port(parent)) {
1498 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1499 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1500 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1502 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1504 * If pdev claims to be upstream port but the parent
1505 * device is also upstream port assume pdev is actually
1506 * downstream port.
1508 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1509 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1510 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1511 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1516 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1518 u32 reg32;
1520 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1521 if (reg32 & PCI_EXP_SLTCAP_HPC)
1522 pdev->is_hotplug_bridge = 1;
1525 static void set_pcie_thunderbolt(struct pci_dev *dev)
1527 int vsec = 0;
1528 u32 header;
1530 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1531 PCI_EXT_CAP_ID_VNDR))) {
1532 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1534 /* Is the device part of a Thunderbolt controller? */
1535 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1536 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1537 dev->is_thunderbolt = 1;
1538 return;
1543 static void set_pcie_untrusted(struct pci_dev *dev)
1545 struct pci_dev *parent;
1548 * If the upstream bridge is untrusted we treat this device
1549 * untrusted as well.
1551 parent = pci_upstream_bridge(dev);
1552 if (parent && parent->untrusted)
1553 dev->untrusted = true;
1557 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1558 * @dev: PCI device
1560 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1561 * when forwarding a type1 configuration request the bridge must check that
1562 * the extended register address field is zero. The bridge is not permitted
1563 * to forward the transactions and must handle it as an Unsupported Request.
1564 * Some bridges do not follow this rule and simply drop the extended register
1565 * bits, resulting in the standard config space being aliased, every 256
1566 * bytes across the entire configuration space. Test for this condition by
1567 * comparing the first dword of each potential alias to the vendor/device ID.
1568 * Known offenders:
1569 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1570 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1572 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1574 #ifdef CONFIG_PCI_QUIRKS
1575 int pos;
1576 u32 header, tmp;
1578 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1580 for (pos = PCI_CFG_SPACE_SIZE;
1581 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1582 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1583 || header != tmp)
1584 return false;
1587 return true;
1588 #else
1589 return false;
1590 #endif
1594 * pci_cfg_space_size - Get the configuration space size of the PCI device
1595 * @dev: PCI device
1597 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1598 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1599 * access it. Maybe we don't have a way to generate extended config space
1600 * accesses, or the device is behind a reverse Express bridge. So we try
1601 * reading the dword at 0x100 which must either be 0 or a valid extended
1602 * capability header.
1604 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1606 u32 status;
1607 int pos = PCI_CFG_SPACE_SIZE;
1609 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1610 return PCI_CFG_SPACE_SIZE;
1611 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1612 return PCI_CFG_SPACE_SIZE;
1614 return PCI_CFG_SPACE_EXP_SIZE;
1617 int pci_cfg_space_size(struct pci_dev *dev)
1619 int pos;
1620 u32 status;
1621 u16 class;
1623 #ifdef CONFIG_PCI_IOV
1625 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1626 * implement a PCIe capability and therefore must implement extended
1627 * config space. We can skip the NO_EXTCFG test below and the
1628 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1629 * the fact that the SR-IOV capability on the PF resides in extended
1630 * config space and must be accessible and non-aliased to have enabled
1631 * support for this VF. This is a micro performance optimization for
1632 * systems supporting many VFs.
1634 if (dev->is_virtfn)
1635 return PCI_CFG_SPACE_EXP_SIZE;
1636 #endif
1638 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1639 return PCI_CFG_SPACE_SIZE;
1641 class = dev->class >> 8;
1642 if (class == PCI_CLASS_BRIDGE_HOST)
1643 return pci_cfg_space_size_ext(dev);
1645 if (pci_is_pcie(dev))
1646 return pci_cfg_space_size_ext(dev);
1648 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1649 if (!pos)
1650 return PCI_CFG_SPACE_SIZE;
1652 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1653 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1654 return pci_cfg_space_size_ext(dev);
1656 return PCI_CFG_SPACE_SIZE;
1659 static u32 pci_class(struct pci_dev *dev)
1661 u32 class;
1663 #ifdef CONFIG_PCI_IOV
1664 if (dev->is_virtfn)
1665 return dev->physfn->sriov->class;
1666 #endif
1667 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1668 return class;
1671 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1673 #ifdef CONFIG_PCI_IOV
1674 if (dev->is_virtfn) {
1675 *vendor = dev->physfn->sriov->subsystem_vendor;
1676 *device = dev->physfn->sriov->subsystem_device;
1677 return;
1679 #endif
1680 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1681 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1684 static u8 pci_hdr_type(struct pci_dev *dev)
1686 u8 hdr_type;
1688 #ifdef CONFIG_PCI_IOV
1689 if (dev->is_virtfn)
1690 return dev->physfn->sriov->hdr_type;
1691 #endif
1692 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1693 return hdr_type;
1696 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1698 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1701 * Disable the MSI hardware to avoid screaming interrupts
1702 * during boot. This is the power on reset default so
1703 * usually this should be a noop.
1705 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1706 if (dev->msi_cap)
1707 pci_msi_set_enable(dev, 0);
1709 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1710 if (dev->msix_cap)
1711 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1715 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1716 * @dev: PCI device
1718 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1719 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1721 static int pci_intx_mask_broken(struct pci_dev *dev)
1723 u16 orig, toggle, new;
1725 pci_read_config_word(dev, PCI_COMMAND, &orig);
1726 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1727 pci_write_config_word(dev, PCI_COMMAND, toggle);
1728 pci_read_config_word(dev, PCI_COMMAND, &new);
1730 pci_write_config_word(dev, PCI_COMMAND, orig);
1733 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1734 * r2.3, so strictly speaking, a device is not *broken* if it's not
1735 * writable. But we'll live with the misnomer for now.
1737 if (new != toggle)
1738 return 1;
1739 return 0;
1742 static void early_dump_pci_device(struct pci_dev *pdev)
1744 u32 value[256 / 4];
1745 int i;
1747 pci_info(pdev, "config space:\n");
1749 for (i = 0; i < 256; i += 4)
1750 pci_read_config_dword(pdev, i, &value[i / 4]);
1752 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1753 value, 256, false);
1757 * pci_setup_device - Fill in class and map information of a device
1758 * @dev: the device structure to fill
1760 * Initialize the device structure with information about the device's
1761 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1762 * Called at initialisation of the PCI subsystem and by CardBus services.
1763 * Returns 0 on success and negative if unknown type of device (not normal,
1764 * bridge or CardBus).
1766 int pci_setup_device(struct pci_dev *dev)
1768 u32 class;
1769 u16 cmd;
1770 u8 hdr_type;
1771 int pos = 0;
1772 struct pci_bus_region region;
1773 struct resource *res;
1775 hdr_type = pci_hdr_type(dev);
1777 dev->sysdata = dev->bus->sysdata;
1778 dev->dev.parent = dev->bus->bridge;
1779 dev->dev.bus = &pci_bus_type;
1780 dev->hdr_type = hdr_type & 0x7f;
1781 dev->multifunction = !!(hdr_type & 0x80);
1782 dev->error_state = pci_channel_io_normal;
1783 set_pcie_port_type(dev);
1785 pci_dev_assign_slot(dev);
1788 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1789 * set this higher, assuming the system even supports it.
1791 dev->dma_mask = 0xffffffff;
1793 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1794 dev->bus->number, PCI_SLOT(dev->devfn),
1795 PCI_FUNC(dev->devfn));
1797 class = pci_class(dev);
1799 dev->revision = class & 0xff;
1800 dev->class = class >> 8; /* upper 3 bytes */
1802 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1803 dev->vendor, dev->device, dev->hdr_type, dev->class);
1805 if (pci_early_dump)
1806 early_dump_pci_device(dev);
1808 /* Need to have dev->class ready */
1809 dev->cfg_size = pci_cfg_space_size(dev);
1811 /* Need to have dev->cfg_size ready */
1812 set_pcie_thunderbolt(dev);
1814 set_pcie_untrusted(dev);
1816 /* "Unknown power state" */
1817 dev->current_state = PCI_UNKNOWN;
1819 /* Early fixups, before probing the BARs */
1820 pci_fixup_device(pci_fixup_early, dev);
1822 /* Device class may be changed after fixup */
1823 class = dev->class >> 8;
1825 if (dev->non_compliant_bars) {
1826 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1827 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1828 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1829 cmd &= ~PCI_COMMAND_IO;
1830 cmd &= ~PCI_COMMAND_MEMORY;
1831 pci_write_config_word(dev, PCI_COMMAND, cmd);
1835 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1837 switch (dev->hdr_type) { /* header type */
1838 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1839 if (class == PCI_CLASS_BRIDGE_PCI)
1840 goto bad;
1841 pci_read_irq(dev);
1842 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1844 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1847 * Do the ugly legacy mode stuff here rather than broken chip
1848 * quirk code. Legacy mode ATA controllers have fixed
1849 * addresses. These are not always echoed in BAR0-3, and
1850 * BAR0-3 in a few cases contain junk!
1852 if (class == PCI_CLASS_STORAGE_IDE) {
1853 u8 progif;
1854 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1855 if ((progif & 1) == 0) {
1856 region.start = 0x1F0;
1857 region.end = 0x1F7;
1858 res = &dev->resource[0];
1859 res->flags = LEGACY_IO_RESOURCE;
1860 pcibios_bus_to_resource(dev->bus, res, &region);
1861 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1862 res);
1863 region.start = 0x3F6;
1864 region.end = 0x3F6;
1865 res = &dev->resource[1];
1866 res->flags = LEGACY_IO_RESOURCE;
1867 pcibios_bus_to_resource(dev->bus, res, &region);
1868 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1869 res);
1871 if ((progif & 4) == 0) {
1872 region.start = 0x170;
1873 region.end = 0x177;
1874 res = &dev->resource[2];
1875 res->flags = LEGACY_IO_RESOURCE;
1876 pcibios_bus_to_resource(dev->bus, res, &region);
1877 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1878 res);
1879 region.start = 0x376;
1880 region.end = 0x376;
1881 res = &dev->resource[3];
1882 res->flags = LEGACY_IO_RESOURCE;
1883 pcibios_bus_to_resource(dev->bus, res, &region);
1884 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1885 res);
1888 break;
1890 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1892 * The PCI-to-PCI bridge spec requires that subtractive
1893 * decoding (i.e. transparent) bridge must have programming
1894 * interface code of 0x01.
1896 pci_read_irq(dev);
1897 dev->transparent = ((dev->class & 0xff) == 1);
1898 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1899 pci_read_bridge_windows(dev);
1900 set_pcie_hotplug_bridge(dev);
1901 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1902 if (pos) {
1903 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1904 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1906 break;
1908 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1909 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1910 goto bad;
1911 pci_read_irq(dev);
1912 pci_read_bases(dev, 1, 0);
1913 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1914 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1915 break;
1917 default: /* unknown header */
1918 pci_err(dev, "unknown header type %02x, ignoring device\n",
1919 dev->hdr_type);
1920 return -EIO;
1922 bad:
1923 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1924 dev->class, dev->hdr_type);
1925 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1928 /* We found a fine healthy device, go go go... */
1929 return 0;
1932 static void pci_configure_mps(struct pci_dev *dev)
1934 struct pci_dev *bridge = pci_upstream_bridge(dev);
1935 int mps, mpss, p_mps, rc;
1937 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1938 return;
1940 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1941 if (dev->is_virtfn)
1942 return;
1944 mps = pcie_get_mps(dev);
1945 p_mps = pcie_get_mps(bridge);
1947 if (mps == p_mps)
1948 return;
1950 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1951 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1952 mps, pci_name(bridge), p_mps);
1953 return;
1957 * Fancier MPS configuration is done later by
1958 * pcie_bus_configure_settings()
1960 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1961 return;
1963 mpss = 128 << dev->pcie_mpss;
1964 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
1965 pcie_set_mps(bridge, mpss);
1966 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1967 mpss, p_mps, 128 << bridge->pcie_mpss);
1968 p_mps = pcie_get_mps(bridge);
1971 rc = pcie_set_mps(dev, p_mps);
1972 if (rc) {
1973 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1974 p_mps);
1975 return;
1978 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
1979 p_mps, mps, mpss);
1982 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1984 struct pci_host_bridge *host;
1985 u32 cap;
1986 u16 ctl;
1987 int ret;
1989 if (!pci_is_pcie(dev))
1990 return 0;
1992 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1993 if (ret)
1994 return 0;
1996 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1997 return 0;
1999 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2000 if (ret)
2001 return 0;
2003 host = pci_find_host_bridge(dev->bus);
2004 if (!host)
2005 return 0;
2008 * If some device in the hierarchy doesn't handle Extended Tags
2009 * correctly, make sure they're disabled.
2011 if (host->no_ext_tags) {
2012 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2013 pci_info(dev, "disabling Extended Tags\n");
2014 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2015 PCI_EXP_DEVCTL_EXT_TAG);
2017 return 0;
2020 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2021 pci_info(dev, "enabling Extended Tags\n");
2022 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2023 PCI_EXP_DEVCTL_EXT_TAG);
2025 return 0;
2029 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2030 * @dev: PCI device to query
2032 * Returns true if the device has enabled relaxed ordering attribute.
2034 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2036 u16 v;
2038 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2040 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2042 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2044 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2046 struct pci_dev *root;
2048 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2049 if (dev->is_virtfn)
2050 return;
2052 if (!pcie_relaxed_ordering_enabled(dev))
2053 return;
2056 * For now, we only deal with Relaxed Ordering issues with Root
2057 * Ports. Peer-to-Peer DMA is another can of worms.
2059 root = pci_find_pcie_root_port(dev);
2060 if (!root)
2061 return;
2063 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2064 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2065 PCI_EXP_DEVCTL_RELAX_EN);
2066 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2070 static void pci_configure_ltr(struct pci_dev *dev)
2072 #ifdef CONFIG_PCIEASPM
2073 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2074 struct pci_dev *bridge;
2075 u32 cap, ctl;
2077 if (!pci_is_pcie(dev))
2078 return;
2080 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2081 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2082 return;
2084 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2085 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2086 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2087 dev->ltr_path = 1;
2088 return;
2091 bridge = pci_upstream_bridge(dev);
2092 if (bridge && bridge->ltr_path)
2093 dev->ltr_path = 1;
2095 return;
2098 if (!host->native_ltr)
2099 return;
2102 * Software must not enable LTR in an Endpoint unless the Root
2103 * Complex and all intermediate Switches indicate support for LTR.
2104 * PCIe r4.0, sec 6.18.
2106 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2107 ((bridge = pci_upstream_bridge(dev)) &&
2108 bridge->ltr_path)) {
2109 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2110 PCI_EXP_DEVCTL2_LTR_EN);
2111 dev->ltr_path = 1;
2113 #endif
2116 static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2118 #ifdef CONFIG_PCI_PASID
2119 struct pci_dev *bridge;
2120 int pcie_type;
2121 u32 cap;
2123 if (!pci_is_pcie(dev))
2124 return;
2126 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2127 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2128 return;
2130 pcie_type = pci_pcie_type(dev);
2131 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2132 pcie_type == PCI_EXP_TYPE_RC_END)
2133 dev->eetlp_prefix_path = 1;
2134 else {
2135 bridge = pci_upstream_bridge(dev);
2136 if (bridge && bridge->eetlp_prefix_path)
2137 dev->eetlp_prefix_path = 1;
2139 #endif
2142 static void pci_configure_serr(struct pci_dev *dev)
2144 u16 control;
2146 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2149 * A bridge will not forward ERR_ messages coming from an
2150 * endpoint unless SERR# forwarding is enabled.
2152 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2153 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2154 control |= PCI_BRIDGE_CTL_SERR;
2155 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2160 static void pci_configure_device(struct pci_dev *dev)
2162 pci_configure_mps(dev);
2163 pci_configure_extended_tags(dev, NULL);
2164 pci_configure_relaxed_ordering(dev);
2165 pci_configure_ltr(dev);
2166 pci_configure_eetlp_prefix(dev);
2167 pci_configure_serr(dev);
2169 pci_acpi_program_hp_params(dev);
2172 static void pci_release_capabilities(struct pci_dev *dev)
2174 pci_aer_exit(dev);
2175 pci_vpd_release(dev);
2176 pci_iov_release(dev);
2177 pci_free_cap_save_buffers(dev);
2181 * pci_release_dev - Free a PCI device structure when all users of it are
2182 * finished
2183 * @dev: device that's been disconnected
2185 * Will be called only by the device core when all users of this PCI device are
2186 * done.
2188 static void pci_release_dev(struct device *dev)
2190 struct pci_dev *pci_dev;
2192 pci_dev = to_pci_dev(dev);
2193 pci_release_capabilities(pci_dev);
2194 pci_release_of_node(pci_dev);
2195 pcibios_release_device(pci_dev);
2196 pci_bus_put(pci_dev->bus);
2197 kfree(pci_dev->driver_override);
2198 bitmap_free(pci_dev->dma_alias_mask);
2199 kfree(pci_dev);
2202 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2204 struct pci_dev *dev;
2206 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2207 if (!dev)
2208 return NULL;
2210 INIT_LIST_HEAD(&dev->bus_list);
2211 dev->dev.type = &pci_dev_type;
2212 dev->bus = pci_bus_get(bus);
2214 return dev;
2216 EXPORT_SYMBOL(pci_alloc_dev);
2218 static bool pci_bus_crs_vendor_id(u32 l)
2220 return (l & 0xffff) == 0x0001;
2223 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2224 int timeout)
2226 int delay = 1;
2228 if (!pci_bus_crs_vendor_id(*l))
2229 return true; /* not a CRS completion */
2231 if (!timeout)
2232 return false; /* CRS, but caller doesn't want to wait */
2235 * We got the reserved Vendor ID that indicates a completion with
2236 * Configuration Request Retry Status (CRS). Retry until we get a
2237 * valid Vendor ID or we time out.
2239 while (pci_bus_crs_vendor_id(*l)) {
2240 if (delay > timeout) {
2241 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2242 pci_domain_nr(bus), bus->number,
2243 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2245 return false;
2247 if (delay >= 1000)
2248 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2249 pci_domain_nr(bus), bus->number,
2250 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2252 msleep(delay);
2253 delay *= 2;
2255 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2256 return false;
2259 if (delay >= 1000)
2260 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2261 pci_domain_nr(bus), bus->number,
2262 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2264 return true;
2267 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2268 int timeout)
2270 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2271 return false;
2273 /* Some broken boards return 0 or ~0 if a slot is empty: */
2274 if (*l == 0xffffffff || *l == 0x00000000 ||
2275 *l == 0x0000ffff || *l == 0xffff0000)
2276 return false;
2278 if (pci_bus_crs_vendor_id(*l))
2279 return pci_bus_wait_crs(bus, devfn, l, timeout);
2281 return true;
2284 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2285 int timeout)
2287 #ifdef CONFIG_PCI_QUIRKS
2288 struct pci_dev *bridge = bus->self;
2291 * Certain IDT switches have an issue where they improperly trigger
2292 * ACS Source Validation errors on completions for config reads.
2294 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2295 bridge->device == 0x80b5)
2296 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2297 #endif
2299 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2301 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2304 * Read the config data for a PCI device, sanity-check it,
2305 * and fill in the dev structure.
2307 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2309 struct pci_dev *dev;
2310 u32 l;
2312 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2313 return NULL;
2315 dev = pci_alloc_dev(bus);
2316 if (!dev)
2317 return NULL;
2319 dev->devfn = devfn;
2320 dev->vendor = l & 0xffff;
2321 dev->device = (l >> 16) & 0xffff;
2323 pci_set_of_node(dev);
2325 if (pci_setup_device(dev)) {
2326 pci_bus_put(dev->bus);
2327 kfree(dev);
2328 return NULL;
2331 return dev;
2334 void pcie_report_downtraining(struct pci_dev *dev)
2336 if (!pci_is_pcie(dev))
2337 return;
2339 /* Look from the device up to avoid downstream ports with no devices */
2340 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2341 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2342 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2343 return;
2345 /* Multi-function PCIe devices share the same link/status */
2346 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2347 return;
2349 /* Print link status only if the device is constrained by the fabric */
2350 __pcie_print_link_status(dev, false);
2353 static void pci_init_capabilities(struct pci_dev *dev)
2355 pci_ea_init(dev); /* Enhanced Allocation */
2357 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2358 pci_msi_setup_pci_dev(dev);
2360 /* Buffers for saving PCIe and PCI-X capabilities */
2361 pci_allocate_cap_save_buffers(dev);
2363 pci_pm_init(dev); /* Power Management */
2364 pci_vpd_init(dev); /* Vital Product Data */
2365 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2366 pci_iov_init(dev); /* Single Root I/O Virtualization */
2367 pci_ats_init(dev); /* Address Translation Services */
2368 pci_pri_init(dev); /* Page Request Interface */
2369 pci_pasid_init(dev); /* Process Address Space ID */
2370 pci_enable_acs(dev); /* Enable ACS P2P upstream forwarding */
2371 pci_ptm_init(dev); /* Precision Time Measurement */
2372 pci_aer_init(dev); /* Advanced Error Reporting */
2373 pci_dpc_init(dev); /* Downstream Port Containment */
2375 pcie_report_downtraining(dev);
2377 if (pci_probe_reset_function(dev) == 0)
2378 dev->reset_fn = 1;
2382 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2383 * devices. Firmware interfaces that can select the MSI domain on a
2384 * per-device basis should be called from here.
2386 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2388 struct irq_domain *d;
2391 * If a domain has been set through the pcibios_add_device()
2392 * callback, then this is the one (platform code knows best).
2394 d = dev_get_msi_domain(&dev->dev);
2395 if (d)
2396 return d;
2399 * Let's see if we have a firmware interface able to provide
2400 * the domain.
2402 d = pci_msi_get_device_domain(dev);
2403 if (d)
2404 return d;
2406 return NULL;
2409 static void pci_set_msi_domain(struct pci_dev *dev)
2411 struct irq_domain *d;
2414 * If the platform or firmware interfaces cannot supply a
2415 * device-specific MSI domain, then inherit the default domain
2416 * from the host bridge itself.
2418 d = pci_dev_msi_domain(dev);
2419 if (!d)
2420 d = dev_get_msi_domain(&dev->bus->dev);
2422 dev_set_msi_domain(&dev->dev, d);
2425 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2427 int ret;
2429 pci_configure_device(dev);
2431 device_initialize(&dev->dev);
2432 dev->dev.release = pci_release_dev;
2434 set_dev_node(&dev->dev, pcibus_to_node(bus));
2435 dev->dev.dma_mask = &dev->dma_mask;
2436 dev->dev.dma_parms = &dev->dma_parms;
2437 dev->dev.coherent_dma_mask = 0xffffffffull;
2439 dma_set_max_seg_size(&dev->dev, 65536);
2440 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2442 /* Fix up broken headers */
2443 pci_fixup_device(pci_fixup_header, dev);
2445 pci_reassigndev_resource_alignment(dev);
2447 dev->state_saved = false;
2449 pci_init_capabilities(dev);
2452 * Add the device to our list of discovered devices
2453 * and the bus list for fixup functions, etc.
2455 down_write(&pci_bus_sem);
2456 list_add_tail(&dev->bus_list, &bus->devices);
2457 up_write(&pci_bus_sem);
2459 ret = pcibios_add_device(dev);
2460 WARN_ON(ret < 0);
2462 /* Set up MSI IRQ domain */
2463 pci_set_msi_domain(dev);
2465 /* Notifier could use PCI capabilities */
2466 dev->match_driver = false;
2467 ret = device_add(&dev->dev);
2468 WARN_ON(ret < 0);
2471 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2473 struct pci_dev *dev;
2475 dev = pci_get_slot(bus, devfn);
2476 if (dev) {
2477 pci_dev_put(dev);
2478 return dev;
2481 dev = pci_scan_device(bus, devfn);
2482 if (!dev)
2483 return NULL;
2485 pci_device_add(dev, bus);
2487 return dev;
2489 EXPORT_SYMBOL(pci_scan_single_device);
2491 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2493 int pos;
2494 u16 cap = 0;
2495 unsigned next_fn;
2497 if (pci_ari_enabled(bus)) {
2498 if (!dev)
2499 return 0;
2500 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2501 if (!pos)
2502 return 0;
2504 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2505 next_fn = PCI_ARI_CAP_NFN(cap);
2506 if (next_fn <= fn)
2507 return 0; /* protect against malformed list */
2509 return next_fn;
2512 /* dev may be NULL for non-contiguous multifunction devices */
2513 if (!dev || dev->multifunction)
2514 return (fn + 1) % 8;
2516 return 0;
2519 static int only_one_child(struct pci_bus *bus)
2521 struct pci_dev *bridge = bus->self;
2524 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2525 * we scan for all possible devices, not just Device 0.
2527 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2528 return 0;
2531 * A PCIe Downstream Port normally leads to a Link with only Device
2532 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2533 * only for Device 0 in that situation.
2535 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2536 return 1;
2538 return 0;
2542 * pci_scan_slot - Scan a PCI slot on a bus for devices
2543 * @bus: PCI bus to scan
2544 * @devfn: slot number to scan (must have zero function)
2546 * Scan a PCI slot on the specified PCI bus for devices, adding
2547 * discovered devices to the @bus->devices list. New devices
2548 * will not have is_added set.
2550 * Returns the number of new devices found.
2552 int pci_scan_slot(struct pci_bus *bus, int devfn)
2554 unsigned fn, nr = 0;
2555 struct pci_dev *dev;
2557 if (only_one_child(bus) && (devfn > 0))
2558 return 0; /* Already scanned the entire slot */
2560 dev = pci_scan_single_device(bus, devfn);
2561 if (!dev)
2562 return 0;
2563 if (!pci_dev_is_added(dev))
2564 nr++;
2566 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2567 dev = pci_scan_single_device(bus, devfn + fn);
2568 if (dev) {
2569 if (!pci_dev_is_added(dev))
2570 nr++;
2571 dev->multifunction = 1;
2575 /* Only one slot has PCIe device */
2576 if (bus->self && nr)
2577 pcie_aspm_init_link_state(bus->self);
2579 return nr;
2581 EXPORT_SYMBOL(pci_scan_slot);
2583 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2585 u8 *smpss = data;
2587 if (!pci_is_pcie(dev))
2588 return 0;
2591 * We don't have a way to change MPS settings on devices that have
2592 * drivers attached. A hot-added device might support only the minimum
2593 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2594 * where devices may be hot-added, we limit the fabric MPS to 128 so
2595 * hot-added devices will work correctly.
2597 * However, if we hot-add a device to a slot directly below a Root
2598 * Port, it's impossible for there to be other existing devices below
2599 * the port. We don't limit the MPS in this case because we can
2600 * reconfigure MPS on both the Root Port and the hot-added device,
2601 * and there are no other devices involved.
2603 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2605 if (dev->is_hotplug_bridge &&
2606 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2607 *smpss = 0;
2609 if (*smpss > dev->pcie_mpss)
2610 *smpss = dev->pcie_mpss;
2612 return 0;
2615 static void pcie_write_mps(struct pci_dev *dev, int mps)
2617 int rc;
2619 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2620 mps = 128 << dev->pcie_mpss;
2622 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2623 dev->bus->self)
2626 * For "Performance", the assumption is made that
2627 * downstream communication will never be larger than
2628 * the MRRS. So, the MPS only needs to be configured
2629 * for the upstream communication. This being the case,
2630 * walk from the top down and set the MPS of the child
2631 * to that of the parent bus.
2633 * Configure the device MPS with the smaller of the
2634 * device MPSS or the bridge MPS (which is assumed to be
2635 * properly configured at this point to the largest
2636 * allowable MPS based on its parent bus).
2638 mps = min(mps, pcie_get_mps(dev->bus->self));
2641 rc = pcie_set_mps(dev, mps);
2642 if (rc)
2643 pci_err(dev, "Failed attempting to set the MPS\n");
2646 static void pcie_write_mrrs(struct pci_dev *dev)
2648 int rc, mrrs;
2651 * In the "safe" case, do not configure the MRRS. There appear to be
2652 * issues with setting MRRS to 0 on a number of devices.
2654 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2655 return;
2658 * For max performance, the MRRS must be set to the largest supported
2659 * value. However, it cannot be configured larger than the MPS the
2660 * device or the bus can support. This should already be properly
2661 * configured by a prior call to pcie_write_mps().
2663 mrrs = pcie_get_mps(dev);
2666 * MRRS is a R/W register. Invalid values can be written, but a
2667 * subsequent read will verify if the value is acceptable or not.
2668 * If the MRRS value provided is not acceptable (e.g., too large),
2669 * shrink the value until it is acceptable to the HW.
2671 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2672 rc = pcie_set_readrq(dev, mrrs);
2673 if (!rc)
2674 break;
2676 pci_warn(dev, "Failed attempting to set the MRRS\n");
2677 mrrs /= 2;
2680 if (mrrs < 128)
2681 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2684 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2686 int mps, orig_mps;
2688 if (!pci_is_pcie(dev))
2689 return 0;
2691 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2692 pcie_bus_config == PCIE_BUS_DEFAULT)
2693 return 0;
2695 mps = 128 << *(u8 *)data;
2696 orig_mps = pcie_get_mps(dev);
2698 pcie_write_mps(dev, mps);
2699 pcie_write_mrrs(dev);
2701 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2702 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2703 orig_mps, pcie_get_readrq(dev));
2705 return 0;
2709 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2710 * parents then children fashion. If this changes, then this code will not
2711 * work as designed.
2713 void pcie_bus_configure_settings(struct pci_bus *bus)
2715 u8 smpss = 0;
2717 if (!bus->self)
2718 return;
2720 if (!pci_is_pcie(bus->self))
2721 return;
2724 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2725 * to be aware of the MPS of the destination. To work around this,
2726 * simply force the MPS of the entire system to the smallest possible.
2728 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2729 smpss = 0;
2731 if (pcie_bus_config == PCIE_BUS_SAFE) {
2732 smpss = bus->self->pcie_mpss;
2734 pcie_find_smpss(bus->self, &smpss);
2735 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2738 pcie_bus_configure_set(bus->self, &smpss);
2739 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2741 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2744 * Called after each bus is probed, but before its children are examined. This
2745 * is marked as __weak because multiple architectures define it.
2747 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2749 /* nothing to do, expected to be removed in the future */
2753 * pci_scan_child_bus_extend() - Scan devices below a bus
2754 * @bus: Bus to scan for devices
2755 * @available_buses: Total number of buses available (%0 does not try to
2756 * extend beyond the minimal)
2758 * Scans devices below @bus including subordinate buses. Returns new
2759 * subordinate number including all the found devices. Passing
2760 * @available_buses causes the remaining bus space to be distributed
2761 * equally between hotplug-capable bridges to allow future extension of the
2762 * hierarchy.
2764 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2765 unsigned int available_buses)
2767 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2768 unsigned int start = bus->busn_res.start;
2769 unsigned int devfn, fn, cmax, max = start;
2770 struct pci_dev *dev;
2771 int nr_devs;
2773 dev_dbg(&bus->dev, "scanning bus\n");
2775 /* Go find them, Rover! */
2776 for (devfn = 0; devfn < 256; devfn += 8) {
2777 nr_devs = pci_scan_slot(bus, devfn);
2780 * The Jailhouse hypervisor may pass individual functions of a
2781 * multi-function device to a guest without passing function 0.
2782 * Look for them as well.
2784 if (jailhouse_paravirt() && nr_devs == 0) {
2785 for (fn = 1; fn < 8; fn++) {
2786 dev = pci_scan_single_device(bus, devfn + fn);
2787 if (dev)
2788 dev->multifunction = 1;
2793 /* Reserve buses for SR-IOV capability */
2794 used_buses = pci_iov_bus_range(bus);
2795 max += used_buses;
2798 * After performing arch-dependent fixup of the bus, look behind
2799 * all PCI-to-PCI bridges on this bus.
2801 if (!bus->is_added) {
2802 dev_dbg(&bus->dev, "fixups for bus\n");
2803 pcibios_fixup_bus(bus);
2804 bus->is_added = 1;
2808 * Calculate how many hotplug bridges and normal bridges there
2809 * are on this bus. We will distribute the additional available
2810 * buses between hotplug bridges.
2812 for_each_pci_bridge(dev, bus) {
2813 if (dev->is_hotplug_bridge)
2814 hotplug_bridges++;
2815 else
2816 normal_bridges++;
2820 * Scan bridges that are already configured. We don't touch them
2821 * unless they are misconfigured (which will be done in the second
2822 * scan below).
2824 for_each_pci_bridge(dev, bus) {
2825 cmax = max;
2826 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2829 * Reserve one bus for each bridge now to avoid extending
2830 * hotplug bridges too much during the second scan below.
2832 used_buses++;
2833 if (cmax - max > 1)
2834 used_buses += cmax - max - 1;
2837 /* Scan bridges that need to be reconfigured */
2838 for_each_pci_bridge(dev, bus) {
2839 unsigned int buses = 0;
2841 if (!hotplug_bridges && normal_bridges == 1) {
2844 * There is only one bridge on the bus (upstream
2845 * port) so it gets all available buses which it
2846 * can then distribute to the possible hotplug
2847 * bridges below.
2849 buses = available_buses;
2850 } else if (dev->is_hotplug_bridge) {
2853 * Distribute the extra buses between hotplug
2854 * bridges if any.
2856 buses = available_buses / hotplug_bridges;
2857 buses = min(buses, available_buses - used_buses + 1);
2860 cmax = max;
2861 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2862 /* One bus is already accounted so don't add it again */
2863 if (max - cmax > 1)
2864 used_buses += max - cmax - 1;
2868 * Make sure a hotplug bridge has at least the minimum requested
2869 * number of buses but allow it to grow up to the maximum available
2870 * bus number of there is room.
2872 if (bus->self && bus->self->is_hotplug_bridge) {
2873 used_buses = max_t(unsigned int, available_buses,
2874 pci_hotplug_bus_size - 1);
2875 if (max - start < used_buses) {
2876 max = start + used_buses;
2878 /* Do not allocate more buses than we have room left */
2879 if (max > bus->busn_res.end)
2880 max = bus->busn_res.end;
2882 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2883 &bus->busn_res, max - start);
2888 * We've scanned the bus and so we know all about what's on
2889 * the other side of any bridges that may be on this bus plus
2890 * any devices.
2892 * Return how far we've got finding sub-buses.
2894 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2895 return max;
2899 * pci_scan_child_bus() - Scan devices below a bus
2900 * @bus: Bus to scan for devices
2902 * Scans devices below @bus including subordinate buses. Returns new
2903 * subordinate number including all the found devices.
2905 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2907 return pci_scan_child_bus_extend(bus, 0);
2909 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2912 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2913 * @bridge: Host bridge to set up
2915 * Default empty implementation. Replace with an architecture-specific setup
2916 * routine, if necessary.
2918 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2920 return 0;
2923 void __weak pcibios_add_bus(struct pci_bus *bus)
2927 void __weak pcibios_remove_bus(struct pci_bus *bus)
2931 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2932 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2934 int error;
2935 struct pci_host_bridge *bridge;
2937 bridge = pci_alloc_host_bridge(0);
2938 if (!bridge)
2939 return NULL;
2941 bridge->dev.parent = parent;
2943 list_splice_init(resources, &bridge->windows);
2944 bridge->sysdata = sysdata;
2945 bridge->busnr = bus;
2946 bridge->ops = ops;
2948 error = pci_register_host_bridge(bridge);
2949 if (error < 0)
2950 goto err_out;
2952 return bridge->bus;
2954 err_out:
2955 kfree(bridge);
2956 return NULL;
2958 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2960 int pci_host_probe(struct pci_host_bridge *bridge)
2962 struct pci_bus *bus, *child;
2963 int ret;
2965 ret = pci_scan_root_bus_bridge(bridge);
2966 if (ret < 0) {
2967 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2968 return ret;
2971 bus = bridge->bus;
2974 * We insert PCI resources into the iomem_resource and
2975 * ioport_resource trees in either pci_bus_claim_resources()
2976 * or pci_bus_assign_resources().
2978 if (pci_has_flag(PCI_PROBE_ONLY)) {
2979 pci_bus_claim_resources(bus);
2980 } else {
2981 pci_bus_size_bridges(bus);
2982 pci_bus_assign_resources(bus);
2984 list_for_each_entry(child, &bus->children, node)
2985 pcie_bus_configure_settings(child);
2988 pci_bus_add_devices(bus);
2989 return 0;
2991 EXPORT_SYMBOL_GPL(pci_host_probe);
2993 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2995 struct resource *res = &b->busn_res;
2996 struct resource *parent_res, *conflict;
2998 res->start = bus;
2999 res->end = bus_max;
3000 res->flags = IORESOURCE_BUS;
3002 if (!pci_is_root_bus(b))
3003 parent_res = &b->parent->busn_res;
3004 else {
3005 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3006 res->flags |= IORESOURCE_PCI_FIXED;
3009 conflict = request_resource_conflict(parent_res, res);
3011 if (conflict)
3012 dev_info(&b->dev,
3013 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3014 res, pci_is_root_bus(b) ? "domain " : "",
3015 parent_res, conflict->name, conflict);
3017 return conflict == NULL;
3020 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3022 struct resource *res = &b->busn_res;
3023 struct resource old_res = *res;
3024 resource_size_t size;
3025 int ret;
3027 if (res->start > bus_max)
3028 return -EINVAL;
3030 size = bus_max - res->start + 1;
3031 ret = adjust_resource(res, res->start, size);
3032 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3033 &old_res, ret ? "can not be" : "is", bus_max);
3035 if (!ret && !res->parent)
3036 pci_bus_insert_busn_res(b, res->start, res->end);
3038 return ret;
3041 void pci_bus_release_busn_res(struct pci_bus *b)
3043 struct resource *res = &b->busn_res;
3044 int ret;
3046 if (!res->flags || !res->parent)
3047 return;
3049 ret = release_resource(res);
3050 dev_info(&b->dev, "busn_res: %pR %s released\n",
3051 res, ret ? "can not be" : "is");
3054 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3056 struct resource_entry *window;
3057 bool found = false;
3058 struct pci_bus *b;
3059 int max, bus, ret;
3061 if (!bridge)
3062 return -EINVAL;
3064 resource_list_for_each_entry(window, &bridge->windows)
3065 if (window->res->flags & IORESOURCE_BUS) {
3066 found = true;
3067 break;
3070 ret = pci_register_host_bridge(bridge);
3071 if (ret < 0)
3072 return ret;
3074 b = bridge->bus;
3075 bus = bridge->busnr;
3077 if (!found) {
3078 dev_info(&b->dev,
3079 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3080 bus);
3081 pci_bus_insert_busn_res(b, bus, 255);
3084 max = pci_scan_child_bus(b);
3086 if (!found)
3087 pci_bus_update_busn_res_end(b, max);
3089 return 0;
3091 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3093 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3094 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3096 struct resource_entry *window;
3097 bool found = false;
3098 struct pci_bus *b;
3099 int max;
3101 resource_list_for_each_entry(window, resources)
3102 if (window->res->flags & IORESOURCE_BUS) {
3103 found = true;
3104 break;
3107 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3108 if (!b)
3109 return NULL;
3111 if (!found) {
3112 dev_info(&b->dev,
3113 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3114 bus);
3115 pci_bus_insert_busn_res(b, bus, 255);
3118 max = pci_scan_child_bus(b);
3120 if (!found)
3121 pci_bus_update_busn_res_end(b, max);
3123 return b;
3125 EXPORT_SYMBOL(pci_scan_root_bus);
3127 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3128 void *sysdata)
3130 LIST_HEAD(resources);
3131 struct pci_bus *b;
3133 pci_add_resource(&resources, &ioport_resource);
3134 pci_add_resource(&resources, &iomem_resource);
3135 pci_add_resource(&resources, &busn_resource);
3136 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3137 if (b) {
3138 pci_scan_child_bus(b);
3139 } else {
3140 pci_free_resource_list(&resources);
3142 return b;
3144 EXPORT_SYMBOL(pci_scan_bus);
3147 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3148 * @bridge: PCI bridge for the bus to scan
3150 * Scan a PCI bus and child buses for new devices, add them,
3151 * and enable them, resizing bridge mmio/io resource if necessary
3152 * and possible. The caller must ensure the child devices are already
3153 * removed for resizing to occur.
3155 * Returns the max number of subordinate bus discovered.
3157 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3159 unsigned int max;
3160 struct pci_bus *bus = bridge->subordinate;
3162 max = pci_scan_child_bus(bus);
3164 pci_assign_unassigned_bridge_resources(bridge);
3166 pci_bus_add_devices(bus);
3168 return max;
3172 * pci_rescan_bus - Scan a PCI bus for devices
3173 * @bus: PCI bus to scan
3175 * Scan a PCI bus and child buses for new devices, add them,
3176 * and enable them.
3178 * Returns the max number of subordinate bus discovered.
3180 unsigned int pci_rescan_bus(struct pci_bus *bus)
3182 unsigned int max;
3184 max = pci_scan_child_bus(bus);
3185 pci_assign_unassigned_bus_resources(bus);
3186 pci_bus_add_devices(bus);
3188 return max;
3190 EXPORT_SYMBOL_GPL(pci_rescan_bus);
3193 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3194 * routines should always be executed under this mutex.
3196 static DEFINE_MUTEX(pci_rescan_remove_lock);
3198 void pci_lock_rescan_remove(void)
3200 mutex_lock(&pci_rescan_remove_lock);
3202 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3204 void pci_unlock_rescan_remove(void)
3206 mutex_unlock(&pci_rescan_remove_lock);
3208 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3210 static int __init pci_sort_bf_cmp(const struct device *d_a,
3211 const struct device *d_b)
3213 const struct pci_dev *a = to_pci_dev(d_a);
3214 const struct pci_dev *b = to_pci_dev(d_b);
3216 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3217 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3219 if (a->bus->number < b->bus->number) return -1;
3220 else if (a->bus->number > b->bus->number) return 1;
3222 if (a->devfn < b->devfn) return -1;
3223 else if (a->devfn > b->devfn) return 1;
3225 return 0;
3228 void __init pci_sort_breadthfirst(void)
3230 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3233 int pci_hp_add_bridge(struct pci_dev *dev)
3235 struct pci_bus *parent = dev->bus;
3236 int busnr, start = parent->busn_res.start;
3237 unsigned int available_buses = 0;
3238 int end = parent->busn_res.end;
3240 for (busnr = start; busnr <= end; busnr++) {
3241 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3242 break;
3244 if (busnr-- > end) {
3245 pci_err(dev, "No bus number available for hot-added bridge\n");
3246 return -1;
3249 /* Scan bridges that are already configured */
3250 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3253 * Distribute the available bus numbers between hotplug-capable
3254 * bridges to make extending the chain later possible.
3256 available_buses = end - busnr;
3258 /* Scan bridges that need to be reconfigured */
3259 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3261 if (!dev->subordinate)
3262 return -1;
3264 return 0;
3266 EXPORT_SYMBOL_GPL(pci_hp_add_bridge);