drivers/pcmcia/cirrus.h

   1 /*
   2  * cirrus.h 1.4 1999/10/25 20:03:34
   3  *
   4  * The contents of this file are subject to the Mozilla Public License
   5  * Version 1.1 (the "License"); you may not use this file except in
   6  * compliance with the License. You may obtain a copy of the License
   7  * at http://www.mozilla.org/MPL/
   8  *
   9  * Software distributed under the License is distributed on an "AS IS"
  10  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11  * the License for the specific language governing rights and
  12  * limitations under the License.
  13  *
  14  * The initial developer of the original code is David A. Hinds
  15  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
  16  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
  17  *
  18  * Alternatively, the contents of this file may be used under the
  19  * terms of the GNU General Public License version 2 (the "GPL"), in which
  20  * case the provisions of the GPL are applicable instead of the
  21  * above.  If you wish to allow the use of your version of this file
  22  * only under the terms of the GPL and not to allow others to use
  23  * your version of this file under the MPL, indicate your decision by
  24  * deleting the provisions above and replace them with the notice and
  25  * other provisions required by the GPL.  If you do not delete the
  26  * provisions above, a recipient may use your version of this file
  27  * under either the MPL or the GPL.
  28  */
  29
  30 #ifndef _LINUX_CIRRUS_H
  31 #define _LINUX_CIRRUS_H
  32
  33 #define PD67_MISC_CTL_1         0x16    /* Misc control 1 */
  34 #define PD67_FIFO_CTL           0x17    /* FIFO control */
  35 #define PD67_MISC_CTL_2         0x1E    /* Misc control 2 */
  36 #define PD67_CHIP_INFO          0x1f    /* Chip information */
  37 #define PD67_ATA_CTL            0x026   /* 6730: ATA control */
  38 #define PD67_EXT_INDEX          0x2e    /* Extension index */
  39 #define PD67_EXT_DATA           0x2f    /* Extension data */
  40
  41 /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
  42 #define PD67_DATA_MASK0         0x01    /* Data mask 0 */
  43 #define PD67_DATA_MASK1         0x02    /* Data mask 1 */
  44 #define PD67_DMA_CTL            0x03    /* DMA control */
  45
  46 /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
  47 #define PD67_EXT_CTL_1          0x03    /* Extension control 1 */
  48 #define PD67_MEM_PAGE(n)        ((n)+5) /* PCI window bits 31:24 */
  49 #define PD67_EXTERN_DATA        0x0a
  50 #define PD67_MISC_CTL_3         0x25
  51 #define PD67_SMB_PWR_CTL        0x26
  52
  53 /* I/O window address offset */
  54 #define PD67_IO_OFF(w)          (0x36+((w)<<1))
  55
  56 /* Timing register sets */
  57 #define PD67_TIME_SETUP(n)      (0x3a + 3*(n))
  58 #define PD67_TIME_CMD(n)        (0x3b + 3*(n))
  59 #define PD67_TIME_RECOV(n)      (0x3c + 3*(n))
  60
  61 /* Flags for PD67_MISC_CTL_1 */
  62 #define PD67_MC1_5V_DET         0x01    /* 5v detect */
  63 #define PD67_MC1_MEDIA_ENA      0x01    /* 6730: Multimedia enable */
  64 #define PD67_MC1_VCC_3V         0x02    /* 3.3v Vcc */
  65 #define PD67_MC1_PULSE_MGMT     0x04
  66 #define PD67_MC1_PULSE_IRQ      0x08
  67 #define PD67_MC1_SPKR_ENA       0x10
  68 #define PD67_MC1_INPACK_ENA     0x80
  69
  70 /* Flags for PD67_FIFO_CTL */
  71 #define PD67_FIFO_EMPTY         0x80
  72
  73 /* Flags for PD67_MISC_CTL_2 */
  74 #define PD67_MC2_FREQ_BYPASS    0x01
  75 #define PD67_MC2_DYNAMIC_MODE   0x02
  76 #define PD67_MC2_SUSPEND        0x04
  77 #define PD67_MC2_5V_CORE        0x08
  78 #define PD67_MC2_LED_ENA        0x10    /* IRQ 12 is LED enable */
  79 #define PD67_MC2_FAST_PCI       0x10    /* 6729: PCI bus > 25 MHz */
  80 #define PD67_MC2_3STATE_BIT7    0x20    /* Floppy change bit */
  81 #define PD67_MC2_DMA_MODE       0x40
  82 #define PD67_MC2_IRQ15_RI       0x80    /* IRQ 15 is ring enable */
  83
  84 /* Flags for PD67_CHIP_INFO */
  85 #define PD67_INFO_SLOTS         0x20    /* 0 = 1 slot, 1 = 2 slots */
  86 #define PD67_INFO_CHIP_ID       0xc0
  87 #define PD67_INFO_REV           0x1c
  88
  89 /* Fields in PD67_TIME_* registers */
  90 #define PD67_TIME_SCALE         0xc0
  91 #define PD67_TIME_SCALE_1       0x00
  92 #define PD67_TIME_SCALE_16      0x40
  93 #define PD67_TIME_SCALE_256     0x80
  94 #define PD67_TIME_SCALE_4096    0xc0
  95 #define PD67_TIME_MULT          0x3f
  96
  97 /* Fields in PD67_DMA_CTL */
  98 #define PD67_DMA_MODE           0xc0
  99 #define PD67_DMA_OFF            0x00
 100 #define PD67_DMA_DREQ_INPACK    0x40
 101 #define PD67_DMA_DREQ_WP        0x80
 102 #define PD67_DMA_DREQ_BVD2      0xc0
 103 #define PD67_DMA_PULLUP         0x20    /* Disable socket pullups? */
 104
 105 /* Fields in PD67_EXT_CTL_1 */
 106 #define PD67_EC1_VCC_PWR_LOCK   0x01
 107 #define PD67_EC1_AUTO_PWR_CLEAR 0x02
 108 #define PD67_EC1_LED_ENA        0x04
 109 #define PD67_EC1_INV_CARD_IRQ   0x08
 110 #define PD67_EC1_INV_MGMT_IRQ   0x10
 111 #define PD67_EC1_PULLUP_CTL     0x20
 112
 113 /* Fields in PD67_MISC_CTL_3 */
 114 #define PD67_MC3_IRQ_MASK       0x03
 115 #define PD67_MC3_IRQ_PCPCI      0x00
 116 #define PD67_MC3_IRQ_EXTERN     0x01
 117 #define PD67_MC3_IRQ_PCIWAY     0x02
 118 #define PD67_MC3_IRQ_PCI        0x03
 119 #define PD67_MC3_PWR_MASK       0x0c
 120 #define PD67_MC3_PWR_SERIAL     0x00
 121 #define PD67_MC3_PWR_TI2202     0x08
 122 #define PD67_MC3_PWR_SMB        0x0c
 123
 124 /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
 125
 126 /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
 127 #define PD68_EXT_CTL_2                  0x0b
 128 #define PD68_PCI_SPACE                  0x22
 129 #define PD68_PCCARD_SPACE               0x23
 130 #define PD68_WINDOW_TYPE                0x24
 131 #define PD68_EXT_CSC                    0x2e
 132 #define PD68_MISC_CTL_4                 0x2f
 133 #define PD68_MISC_CTL_5                 0x30
 134 #define PD68_MISC_CTL_6                 0x31
 135
 136 /* Extra flags in PD67_MISC_CTL_3 */
 137 #define PD68_MC3_HW_SUSP                0x10
 138 #define PD68_MC3_MM_EXPAND              0x40
 139 #define PD68_MC3_MM_ARM                 0x80
 140
 141 /* Bridge Control Register */
 142 #define  PD6832_BCR_MGMT_IRQ_ENA        0x0800
 143
 144 /* Socket Number Register */
 145 #define PD6832_SOCKET_NUMBER            0x004c  /* 8 bit */
 146
 147 #endif /* _LINUX_CIRRUS_H */