| blob | f86739e800c321adc1fce9d71f785e3b4bc3965e |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Copyright (C) 2019 IBM Corp. */
4 #ifndef ASPEED_PINMUX_H
5 #define ASPEED_PINMUX_H
7 #include <linux/regmap.h>
8 #include <stdbool.h>
10 /*
11 * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
12 * functions. The SoC function enabled on a pin is determined on a priority
13 * basis where a given pin can provide a number of different signal types.
14 *
15 * The signal active on a pin is described by both a priority level and
16 * compound logical expressions involving multiple operators, registers and
17 * bits. Some difficulty arises as the pin's function bit masks for each
18 * priority level are frequently not the same (i.e. cannot just flip a bit to
19 * change from a high to low priority signal), or even in the same register.
20 * Further, not all signals can be unmuxed, as some expressions depend on
21 * values in the hardware strapping register (which may be treated as
22 * read-only).
23 *
24 * SoC Multi-function Pin Expression Examples
25 * ------------------------------------------
26 *
27 * Here are some sample mux configurations from the AST2400 and AST2500
28 * datasheets to illustrate the corner cases, roughly in order of least to most
29 * corner. The signal priorities are in decending order from P0 (highest).
30 *
31 * D6 is a pin with a single function (beside GPIO); a high priority signal
32 * that participates in one function:
33 *
34 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
35 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
36 * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0
37 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
38 *
39 * C5 is a multi-signal pin (high and low priority signals). Here we touch
40 * different registers for the different functions that enable each signal:
41 *
42 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
43 * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4
44 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
45 *
46 * E19 is a single-signal pin with two functions that influence the active
47 * signal. In this case both bits have the same meaning - enable a dedicated
48 * LPC reset pin. However it's not always the case that the bits in the
49 * OR-relationship have the same meaning.
50 *
51 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
52 * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4
53 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
54 *
55 * For example, pin B19 has a low-priority signal that's enabled by two
56 * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
57 * bit in the STRAP register. The ACPI bit configures signals on pins in
58 * addition to B19. Both of the low priority functions as well as the high
59 * priority function must be disabled for GPIOF1 to be used.
60 *
61 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
62 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
63 * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1
64 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
65 *
66 * For pin E18, the SoC ANDs the expected state of three bits to determine the
67 * pin's active signal:
68 *
69 * * SCU3C[3]: Enable external SOC reset function
70 * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
71 * * SCU90[31]: Select SPI interface CS# output
72 *
73 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
74 * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7
75 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
76 *
77 * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
78 * selecting the signals on pin E18)
79 *
80 * Pin T5 is a multi-signal pin with a more complex configuration:
81 *
82 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
83 * -----+---------+-----------+------------------------------+-----------+---------------+----------
84 * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1
85 * -----+---------+-----------+------------------------------+-----------+---------------+----------
86 *
87 * The high priority signal configuration is best thought of in terms of its
88 * exploded form, with reference to the SCU90[5:4] bits:
89 *
90 * * SCU90[5:4]=00: disable
91 * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
92 * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
93 * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
94 *
95 * Re-writing:
96 *
97 * -----+---------+-----------+------------------------------+-----------+---------------+----------
98 * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1
99 * | (SCU90[5:4]=2 & SCU84[17]=1)
100 * | (SCU90[5:4]=3 & SCU84[17]=1)
101 * -----+---------+-----------+------------------------------+-----------+---------------+----------
102 *
103 * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
104 * function pin", where the signal itself is determined by whether SCU94[5:4]
105 * is disabled or in one of the 18, 24 or 30bit video modes.
106 *
107 * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
108 * W1 and U5:
109 *
110 * -----+---------+-----------+------------------------------+-----------+---------------+----------
111 * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6
112 * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7
113 * -----+---------+-----------+------------------------------+-----------+---------------+----------
114 *
115 * The examples of T5 and W1 are particularly fertile, as they also demonstrate
116 * that despite operating as part of the video input bus each signal needs to
117 * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
118 * register bit. This is a little crazy if the bus doesn't have optional
119 * signals, but is used to decent effect with some of the UARTs where not all
120 * signals are required. However, this isn't done consistently - UART1 is
121 * enabled on a per-pin basis, and by contrast, all signals for UART6 are
122 * enabled by a single bit.
123 *
124 * Further, the high and low priority signals listed in the table above share
125 * a configuration bit. The VPI signals should operate in concert in a single
126 * function, but the UART signals should retain the ability to be configured
127 * independently. This pushes the implementation down the path of tagging a
128 * signal's expressions with the function they participate in, rather than
129 * defining masks affecting multiple signals per function. The latter approach
130 * fails in this instance where applying the configuration for the UART pin of
131 * interest will stomp on the state of other UART signals when disabling the
132 * VPI functions on the current pin.
133 *
134 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
135 * -----+------------+-----------+---------------------------+-----------+---------------+------------
136 * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK
137 * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL
138 * -----+------------+-----------+---------------------------+-----------+---------------+------------
139 *
140 * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
141 * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
142 * should be treated like any other signal type with full function expression
143 * requirements, and not assumed to be the default case. Separately, GPIOT0 and
144 * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
145 * pins in the function's group to disable the higher-priority signals such
146 * that the signal for the function of interest is correctly enabled.
147 *
148 * Finally, three priority levels aren't always enough; the AST2500 brings with
149 * it 18 pins of five priority levels, however the 18 pins only use three of
150 * the five priority levels.
151 *
152 * Ultimately the requirement to control pins in the examples above drive the
153 * design:
154 *
155 * * Pins provide signals according to functions activated in the mux
156 * configuration
157 *
158 * * Pins provide up to five signal types in a priority order
159 *
160 * * For priorities levels defined on a pin, each priority provides one signal
161 *
162 * * Enabling lower priority signals requires higher priority signals be
163 * disabled
164 *
165 * * A function represents a set of signals; functions are distinct if they
166 * do not share a subset of signals (and may be distinct if they are a
167 * strict subset).
168 *
169 * * Signals participate in one or more functions or groups
170 *
171 * * A function is described by an expression of one or more signal
172 * descriptors, which compare bit values in a register
173 *
174 * * A signal expression is the smallest set of signal descriptors whose
175 * comparisons must evaluate 'true' for a signal to be enabled on a pin.
176 *
177 * * A signal participating in a function is active on a pin if evaluating all
178 * signal descriptors in the pin's signal expression for the function yields
179 * a 'true' result
180 *
181 * * A signal at a given priority on a given pin is active if any of the
182 * functions in which the signal participates are active, and no higher
183 * priority signal on the pin is active
184 *
185 * * GPIO is configured per-pin
186 *
187 * And so:
188 *
189 * * To disable a signal, any function(s) activating the signal must be
190 * disabled
191 *
192 * * Each pin must know the signal expressions of functions in which it
193 * participates, for the purpose of enabling the Other function. This is done
194 * by deactivating all functions that activate higher priority signals on the
195 * pin.
196 *
197 * As a concrete example:
198 *
199 * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
200 *
201 * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
202 *
203 * * The NDCD1 signal participates in just its own NDCD1 function
204 *
205 * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
206 * prioritised
207 *
208 * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
209 * and VPI30 functions all be disabled
210 *
211 * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
212 * to provide GPIOL6
213 *
214 * Considerations
215 * --------------
216 *
217 * If pinctrl allows us to allocate a pin we can configure a function without
218 * concern for the function of already allocated pins, if pin groups are
219 * created with respect to the SoC functions in which they participate. This is
220 * intuitive, but it did not feel obvious from the bit/pin relationships.
221 *
222 * Conversely, failing to allocate all pins in a group indicates some bits (as
223 * well as pins) required for the group's configuration will already be in use,
224 * likely in a way that's inconsistent with the requirements of the failed
225 * group.
226 *
227 * Implementation
228 * --------------
229 *
230 * Beyond the documentation below the various structures and helper macros that
231 * allow the implementation to hang together are defined. The macros are fairly
232 * dense, so below we walk through some raw examples of the configuration
233 * tables in an effort to clarify the concepts.
234 *
235 * The complexity of configuring the mux combined with the scale of the pins
236 * and functions was a concern, so the table design along with the macro jungle
237 * is an attempt to address it. The rough principles of the approach are:
238 *
239 * 1. Use a data-driven solution rather than embedding state into code
240 * 2. Minimise editing to the specifics of the given mux configuration
241 * 3. Detect as many errors as possible at compile time
242 *
243 * Addressing point 3 leads to naming of symbols in terms of the four
244 * properties associated with a given mux configuration: The pin, the signal,
245 * the group and the function. In this way copy/paste errors cause duplicate
246 * symbols to be defined, which prevents successful compilation. Failing to
247 * properly parent the tables leads to unused symbol warnings, and use of
248 * designated initialisers and additional warnings ensures that there are
249 * no override errors in the pin, group and function arrays.
250 *
251 * Addressing point 2 drives the development of the macro jungle, as it
252 * centralises the definition noise at the cost of taking some time to
253 * understand.
254 *
255 * Here's a complete, concrete "pre-processed" example of the table structures
256 * used to describe the D6 ball from the examples above:
257 *
258 * ```
259 * static const struct aspeed_sig_desc sig_descs_MAC1LINK_MAC1LINK[] = {
260 * {
261 * .ip = ASPEED_IP_SCU,
262 * .reg = 0x80,
263 * .mask = BIT(0),
264 * .enable = 1,
265 * .disable = 0
266 * },
267 * };
268 *
269 * static const struct aspeed_sig_expr sig_expr_MAC1LINK_MAC1LINK = {
270 * .signal = "MAC1LINK",
271 * .function = "MAC1LINK",
272 * .ndescs = ARRAY_SIZE(sig_descs_MAC1LINK_MAC1LINK),
273 * .descs = &(sig_descs_MAC1LINK_MAC1LINK)[0],
274 * };
275 *
276 * static const struct aspeed_sig_expr *sig_exprs_MAC1LINK_MAC1LINK[] = {
277 * &sig_expr_MAC1LINK_MAC1LINK,
278 * NULL,
279 * };
280 *
281 * static const struct aspeed_sig_desc sig_descs_GPIOA0_GPIOA0[] = { };
282 *
283 * static const struct aspeed_sig_expr sig_expr_GPIOA0_GPIOA0 = {
284 * .signal = "GPIOA0",
285 * .function = "GPIOA0",
286 * .ndescs = ARRAY_SIZE(sig_descs_GPIOA0_GPIOA0),
287 * .descs = &(sig_descs_GPIOA0_GPIOA0)[0],
288 * };
289 *
290 * static const struct aspeed_sig_expr *sig_exprs_GPIOA0_GPIOA0[] = {
291 * &sig_expr_GPIOA0_GPIOA0,
292 * NULL
293 * };
294 *
295 * static const struct aspeed_sig_expr **pin_exprs_0[] = {
296 * sig_exprs_MAC1LINK_MAC1LINK,
297 * sig_exprs_GPIOA0_GPIOA0,
298 * NULL
299 * };
300 *
301 * static const struct aspeed_pin_desc pin_0 = { "0", (&pin_exprs_0[0]) };
302 * static const int group_pins_MAC1LINK[] = { 0 };
303 * static const char *func_groups_MAC1LINK[] = { "MAC1LINK" };
304 *
305 * static struct pinctrl_pin_desc aspeed_g4_pins[] = {
306 * [0] = { .number = 0, .name = "D6", .drv_data = &pin_0 },
307 * };
308 *
309 * static const struct aspeed_pin_group aspeed_g4_groups[] = {
310 * {
311 * .name = "MAC1LINK",
312 * .pins = &(group_pins_MAC1LINK)[0],
313 * .npins = ARRAY_SIZE(group_pins_MAC1LINK),
314 * },
315 * };
316 *
317 * static const struct aspeed_pin_function aspeed_g4_functions[] = {
318 * {
319 * .name = "MAC1LINK",
320 * .groups = &func_groups_MAC1LINK[0],
321 * .ngroups = ARRAY_SIZE(func_groups_MAC1LINK),
322 * },
323 * };
324 * ```
325 *
326 * At the end of the day much of the above code is compressed into the
327 * following two lines:
328 *
329 * ```
330 * #define D6 0
331 * SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
332 * ```
333 *
334 * The two examples below show just the differences from the example above.
335 *
336 * Ball E18 demonstrates a function, EXTRST, that requires multiple descriptors
337 * be set for it to be muxed:
338 *
339 * ```
340 * static const struct aspeed_sig_desc sig_descs_EXTRST_EXTRST[] = {
341 * {
342 * .ip = ASPEED_IP_SCU,
343 * .reg = 0x3C,
344 * .mask = BIT(3),
345 * .enable = 1,
346 * .disable = 0
347 * },
348 * {
349 * .ip = ASPEED_IP_SCU,
350 * .reg = 0x80,
351 * .mask = BIT(15),
352 * .enable = 1,
353 * .disable = 0
354 * },
355 * {
356 * .ip = ASPEED_IP_SCU,
357 * .reg = 0x90,
358 * .mask = BIT(31),
359 * .enable = 0,
360 * .disable = 1
361 * },
362 * };
363 *
364 * static const struct aspeed_sig_expr sig_expr_EXTRST_EXTRST = {
365 * .signal = "EXTRST",
366 * .function = "EXTRST",
367 * .ndescs = ARRAY_SIZE(sig_descs_EXTRST_EXTRST),
368 * .descs = &(sig_descs_EXTRST_EXTRST)[0],
369 * };
370 * ...
371 * ```
372 *
373 * For ball E19, we have multiple functions enabling a single signal, LPCRST#.
374 * The data structures look like:
375 *
376 * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRST[] = {
377 * {
378 * .ip = ASPEED_IP_SCU,
379 * .reg = 0x80,
380 * .mask = BIT(12),
381 * .enable = 1,
382 * .disable = 0
383 * },
384 * };
385 *
386 * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRST = {
387 * .signal = "LPCRST",
388 * .function = "LPCRST",
389 * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRST),
390 * .descs = &(sig_descs_LPCRST_LPCRST)[0],
391 * };
392 *
393 * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRSTS[] = {
394 * {
395 * .ip = ASPEED_IP_SCU,
396 * .reg = 0x70,
397 * .mask = BIT(14),
398 * .enable = 1,
399 * .disable = 0
400 * },
401 * };
402 *
403 * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRSTS = {
404 * .signal = "LPCRST",
405 * .function = "LPCRSTS",
406 * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRSTS),
407 * .descs = &(sig_descs_LPCRST_LPCRSTS)[0],
408 * };
409 *
410 * static const struct aspeed_sig_expr *sig_exprs_LPCRST_LPCRST[] = {
411 * &sig_expr_LPCRST_LPCRST,
412 * &sig_expr_LPCRST_LPCRSTS,
413 * NULL,
414 * };
415 * ...
416 * ```
417 *
418 * Both expressions listed in the sig_exprs_LPCRST_LPCRST array need to be set
419 * to disabled for the associated GPIO to be muxed.
420 *
421 */
423 #define ASPEED_IP_SCU 0
424 #define ASPEED_IP_GFX 1
425 #define ASPEED_IP_LPC 2
426 #define ASPEED_NR_PINMUX_IPS 3
428 /**
429 * A signal descriptor, which describes the register, bits and the
430 * enable/disable values that should be compared or written.
431 *
432 * @ip: The IP block identifier, used as an index into the regmap array in
433 * struct aspeed_pinctrl_data
434 * @reg: The register offset with respect to the base address of the IP block
435 * @mask: The mask to apply to the register. The lowest set bit of the mask is
436 * used to derive the shift value.
437 * @enable: The value that enables the function. Value should be in the LSBs,
438 * not at the position of the mask.
439 * @disable: The value that disables the function. Value should be in the
440 * LSBs, not at the position of the mask.
441 */
445 u32 mask;
446 u32 enable;
447 u32 disable;
448 };
450 /**
451 * Describes a signal expression. The expression is evaluated by ANDing the
452 * evaluation of the descriptors.
453 *
454 * @signal: The signal name for the priority level on the pin. If the signal
455 * type is GPIO, then the signal name must begin with the string
456 * "GPIO", e.g. GPIOA0, GPIOT4 etc.
457 * @function: The name of the function the signal participates in for the
458 * associated expression
459 * @ndescs: The number of signal descriptors in the expression
460 * @descs: Pointer to an array of signal descriptors that comprise the
461 * function expression
462 */
468 };
470 /**
471 * A struct capturing the list of expressions enabling signals at each priority
472 * for a given pin. The signal configuration for a priority level is evaluated
473 * by ORing the evaluation of the signal expressions in the respective
474 * priority's list.
475 *
476 * @name: A name for the pin
477 * @prios: A pointer to an array of expression list pointers
478 *
479 */
483 };
485 /* Macro hell */
487 #define SIG_DESC_IP_BIT(ip, reg, idx, val) \
488 { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
490 /**
491 * Short-hand macro for describing an SCU descriptor enabled by the state of
492 * one bit. The disable value is derived.
493 *
494 * @reg: The signal's associated register, offset from base
495 * @idx: The signal's bit index in the register
496 * @val: The value (0 or 1) that enables the function
497 */
498 #define SIG_DESC_BIT(reg, idx, val) \
499 SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
501 #define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
503 /**
504 * A further short-hand macro expanding to an SCU descriptor enabled by a set
505 * bit.
506 *
507 * @reg: The register, offset from base
508 * @idx: The bit index in the register
509 */
510 #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
511 #define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 }
513 #define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
514 #define SIG_DESC_LIST_DECL(sig, group, ...) \
515 static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, group)[] = \
516 { __VA_ARGS__ }
518 #define SIG_EXPR_SYM(sig, group) sig_expr_ ## sig ## _ ## group
519 #define SIG_EXPR_DECL_(sig, group, func) \
520 static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, group) = \
521 { \
522 .signal = #sig, \
523 .function = #func, \
524 .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, group)), \
525 .descs = &(SIG_DESC_LIST_SYM(sig, group))[0], \
526 }
528 /**
529 * Declare a signal expression.
530 *
531 * @sig: A macro symbol name for the signal (is subjected to stringification
532 * and token pasting)
533 * @func: The function in which the signal is participating
534 * @...: Signal descriptors that define the signal expression
535 *
536 * For example, the following declares the ROMD8 signal for the ROM16 function:
537 *
538 * SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
539 *
540 * And with multiple signal descriptors:
541 *
542 * SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
543 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
544 */
545 #define SIG_EXPR_DECL(sig, group, func, ...) \
546 SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
547 SIG_EXPR_DECL_(sig, group, func)
549 /**
550 * Declare a pointer to a signal expression
551 *
552 * @sig: The macro symbol name for the signal (subjected to token pasting)
553 * @func: The macro symbol name for the function (subjected to token pasting)
554 */
555 #define SIG_EXPR_PTR(sig, group) (&SIG_EXPR_SYM(sig, group))
557 #define SIG_EXPR_LIST_SYM(sig, group) sig_exprs_ ## sig ## _ ## group
559 /**
560 * Declare a signal expression list for reference in a struct aspeed_pin_prio.
561 *
562 * @sig: A macro symbol name for the signal (is subjected to token pasting)
563 * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
564 *
565 * For example, the 16-bit ROM bus can be enabled by one of two possible signal
566 * expressions:
567 *
568 * SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
569 * SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
570 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
571 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
572 * SIG_EXPR_PTR(ROMD8, ROM16S));
573 */
574 #define SIG_EXPR_LIST_DECL(sig, group, ...) \
575 static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig, group)[] =\
576 { __VA_ARGS__, NULL }
578 #define stringify(x) #x
579 #define istringify(x) stringify(x)
581 /**
582 * Create an expression symbol alias from (signal, group) to (pin, signal).
583 *
584 * @pin: The pin number
585 * @sig: The signal name
586 * @group: The name of the group of which the pin is a member that is
587 * associated with the function's signal
588 *
589 * Using an alias in this way enables detection of copy/paste errors (defining
590 * the signal for a group multiple times) whilst enabling multiple pin groups
591 * to exist for a signal without intrusive side-effects on defining the list of
592 * signals available on a pin.
593 */
594 #define SIG_EXPR_LIST_ALIAS(pin, sig, group) \
595 static const struct aspeed_sig_expr *\
596 SIG_EXPR_LIST_SYM(pin, sig)[ARRAY_SIZE(SIG_EXPR_LIST_SYM(sig, group))] \
597 __attribute__((alias(istringify(SIG_EXPR_LIST_SYM(sig, group)))))
599 /**
600 * A short-hand macro for declaring a function expression and an expression
601 * list with a single expression (SE) and a single group (SG) of pins.
602 *
603 * @pin: The pin the signal will be routed to
604 * @sig: The signal that will be routed to the pin for the function
605 * @func: A macro symbol name for the function
606 * @...: Function descriptors that define the function expression
607 *
608 * For example, signal NCTS6 participates in its own function with one group:
609 *
610 * SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
611 */
612 #define SIG_EXPR_LIST_DECL_SESG(pin, sig, func, ...) \
613 SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
614 SIG_EXPR_DECL_(sig, func, func); \
615 SIG_EXPR_LIST_DECL(sig, func, SIG_EXPR_PTR(sig, func)); \
616 SIG_EXPR_LIST_ALIAS(pin, sig, func)
618 /**
619 * Similar to the above, but for pins with a single expression (SE) and
620 * multiple groups (MG) of pins.
621 *
622 * @pin: The pin the signal will be routed to
623 * @sig: The signal that will be routed to the pin for the function
624 * @group: The name of the function's pin group in which the pin participates
625 * @func: A macro symbol name for the function
626 * @...: Function descriptors that define the function expression
627 */
628 #define SIG_EXPR_LIST_DECL_SEMG(pin, sig, group, func, ...) \
629 SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
630 SIG_EXPR_DECL_(sig, group, func); \
631 SIG_EXPR_LIST_DECL(sig, group, SIG_EXPR_PTR(sig, group)); \
632 SIG_EXPR_LIST_ALIAS(pin, sig, group)
634 /**
635 * Similar to the above, but for pins with a dual expressions (DE) and
636 * and a single group (SG) of pins.
637 *
638 * @pin: The pin the signal will be routed to
639 * @sig: The signal that will be routed to the pin for the function
640 * @group: The name of the function's pin group in which the pin participates
641 * @func: A macro symbol name for the function
642 * @...: Function descriptors that define the function expression
643 */
644 #define SIG_EXPR_LIST_DECL_DESG(pin, sig, f0, f1) \
645 SIG_EXPR_LIST_DECL(sig, f0, \
646 SIG_EXPR_PTR(sig, f0), \
647 SIG_EXPR_PTR(sig, f1)); \
648 SIG_EXPR_LIST_ALIAS(pin, sig, f0)
650 #define SIG_EXPR_LIST_PTR(sig, group) SIG_EXPR_LIST_SYM(sig, group)
652 #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
653 #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
654 #define PIN_SYM(pin) pin_ ## pin
656 #define PIN_DECL_(pin, ...) \
657 static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
658 { __VA_ARGS__, NULL }; \
659 static const struct aspeed_pin_desc PIN_SYM(pin) = \
660 { #pin, PIN_EXPRS_PTR(pin) }
662 /**
663 * Declare a single signal pin
664 *
665 * @pin: The pin number
666 * @other: Macro name for "other" functionality (subjected to stringification)
667 * @sig: Macro name for the signal (subjected to stringification)
668 *
669 * For example:
670 *
671 * #define E3 80
672 * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
673 * PIN_DECL_1(E3, GPIOK0, SCL5);
674 */
675 #define PIN_DECL_1(pin, other, sig) \
676 SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
677 PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
678 SIG_EXPR_LIST_PTR(pin, other))
680 /**
681 * Single signal, single function pin declaration
682 *
683 * @pin: The pin number
684 * @other: Macro name for "other" functionality (subjected to stringification)
685 * @sig: Macro name for the signal (subjected to stringification)
686 * @...: Signal descriptors that define the function expression
687 *
688 * For example:
689 *
690 * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
691 */
692 #define SSSF_PIN_DECL(pin, other, sig, ...) \
693 SIG_EXPR_LIST_DECL_SESG(pin, sig, sig, __VA_ARGS__); \
694 SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
695 PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
696 SIG_EXPR_LIST_PTR(pin, other)); \
697 FUNC_GROUP_DECL(sig, pin)
698 /**
699 * Declare a two-signal pin
700 *
701 * @pin: The pin number
702 * @other: Macro name for "other" functionality (subjected to stringification)
703 * @high: Macro name for the highest priority signal functions
704 * @low: Macro name for the low signal functions
705 *
706 * For example:
707 *
708 * #define A8 56
709 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
710 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
711 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
712 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
713 * SIG_EXPR_PTR(ROMD8, ROM16S));
714 * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
715 * PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
716 */
717 #define PIN_DECL_2(pin, other, high, low) \
718 SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
719 PIN_DECL_(pin, \
720 SIG_EXPR_LIST_PTR(pin, high), \
721 SIG_EXPR_LIST_PTR(pin, low), \
722 SIG_EXPR_LIST_PTR(pin, other))
724 #define PIN_DECL_3(pin, other, high, medium, low) \
725 SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
726 PIN_DECL_(pin, \
727 SIG_EXPR_LIST_PTR(pin, high), \
728 SIG_EXPR_LIST_PTR(pin, medium), \
729 SIG_EXPR_LIST_PTR(pin, low), \
730 SIG_EXPR_LIST_PTR(pin, other))
732 #define GROUP_SYM(group) group_pins_ ## group
733 #define GROUP_DECL(group, ...) \
734 static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
736 #define FUNC_SYM(func) func_groups_ ## func
737 #define FUNC_DECL_(func, ...) \
738 static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
740 #define FUNC_DECL_1(func, group) FUNC_DECL_(func, #group)
741 #define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
742 #define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three)
744 #define FUNC_GROUP_DECL(func, ...) \
745 GROUP_DECL(func, __VA_ARGS__); \
746 FUNC_DECL_(func, #func)
749 #define GPIO_PIN_DECL(pin, gpio) \
750 SIG_EXPR_LIST_DECL_SESG(pin, gpio, gpio); \
751 PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, gpio))
757 };
759 #define ASPEED_PINCTRL_GROUP(name_) { \
760 .name = #name_, \
761 .pins = &(GROUP_SYM(name_))[0], \
762 .npins = ARRAY_SIZE(GROUP_SYM(name_)), \
763 }
769 };
771 #define ASPEED_PINCTRL_FUNC(name_, ...) { \
772 .name = #name_, \
773 .groups = &FUNC_SYM(name_)[0], \
774 .ngroups = ARRAY_SIZE(FUNC_SYM(name_)), \
775 }
784 };
797 };
808 {
810 }