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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / pinctrl / qcom / pinctrl-msm8998.c
bloba05f41fe2706bcea40d79a17b2eede757e4b1603
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/pinctrl/pinctrl.h>
10
11 #include "pinctrl-msm.h"
12
13 #define NORTH 0x500000
14 #define WEST 0x100000
15 #define EAST 0x900000
16
17 #define FUNCTION(fname) \
18 [msm_mux_##fname] = { \
19 .name = #fname, \
20 .groups = fname##_groups, \
21 .ngroups = ARRAY_SIZE(fname##_groups), \
22 }
23
24 #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
25 { \
26 .name = "gpio" #id, \
27 .pins = gpio##id##_pins, \
28 .npins = ARRAY_SIZE(gpio##id##_pins), \
29 .funcs = (int[]){ \
30 msm_mux_gpio, /* gpio mode */ \
31 msm_mux_##f1, \
32 msm_mux_##f2, \
33 msm_mux_##f3, \
34 msm_mux_##f4, \
35 msm_mux_##f5, \
36 msm_mux_##f6, \
37 msm_mux_##f7, \
38 msm_mux_##f8, \
39 msm_mux_##f9 \
40 }, \
41 .nfuncs = 10, \
42 .ctl_reg = base + 0x1000 * id, \
43 .io_reg = base + 0x4 + 0x1000 * id, \
44 .intr_cfg_reg = base + 0x8 + 0x1000 * id, \
45 .intr_status_reg = base + 0xc + 0x1000 * id, \
46 .intr_target_reg = base + 0x8 + 0x1000 * id, \
47 .mux_bit = 2, \
48 .pull_bit = 0, \
49 .drv_bit = 6, \
50 .oe_bit = 9, \
51 .in_bit = 0, \
52 .out_bit = 1, \
53 .intr_enable_bit = 0, \
54 .intr_status_bit = 0, \
55 .intr_target_bit = 5, \
56 .intr_target_kpss_val = 3, \
57 .intr_raw_status_bit = 4, \
58 .intr_polarity_bit = 1, \
59 .intr_detection_bit = 2, \
60 .intr_detection_width = 2, \
61 }
62
63 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
64 { \
65 .name = #pg_name, \
66 .pins = pg_name##_pins, \
67 .npins = ARRAY_SIZE(pg_name##_pins), \
68 .ctl_reg = ctl, \
69 .io_reg = 0, \
70 .intr_cfg_reg = 0, \
71 .intr_status_reg = 0, \
72 .intr_target_reg = 0, \
73 .mux_bit = -1, \
74 .pull_bit = pull, \
75 .drv_bit = drv, \
76 .oe_bit = -1, \
77 .in_bit = -1, \
78 .out_bit = -1, \
79 .intr_enable_bit = -1, \
80 .intr_status_bit = -1, \
81 .intr_target_bit = -1, \
82 .intr_raw_status_bit = -1, \
83 .intr_polarity_bit = -1, \
84 .intr_detection_bit = -1, \
85 .intr_detection_width = -1, \
86 }
87
88 #define UFS_RESET(pg_name, offset) \
89 { \
90 .name = #pg_name, \
91 .pins = pg_name##_pins, \
92 .npins = ARRAY_SIZE(pg_name##_pins), \
93 .ctl_reg = offset, \
94 .io_reg = offset + 0x4, \
95 .intr_cfg_reg = 0, \
96 .intr_status_reg = 0, \
97 .intr_target_reg = 0, \
98 .mux_bit = -1, \
99 .pull_bit = 3, \
100 .drv_bit = 0, \
101 .oe_bit = -1, \
102 .in_bit = -1, \
103 .out_bit = 0, \
104 .intr_enable_bit = -1, \
105 .intr_status_bit = -1, \
106 .intr_target_bit = -1, \
107 .intr_raw_status_bit = -1, \
108 .intr_polarity_bit = -1, \
109 .intr_detection_bit = -1, \
110 .intr_detection_width = -1, \
111 }
112
113 static const struct pinctrl_pin_desc msm8998_pins[] = {
114 PINCTRL_PIN(0, "GPIO_0"),
115 PINCTRL_PIN(1, "GPIO_1"),
116 PINCTRL_PIN(2, "GPIO_2"),
117 PINCTRL_PIN(3, "GPIO_3"),
118 PINCTRL_PIN(4, "GPIO_4"),
119 PINCTRL_PIN(5, "GPIO_5"),
120 PINCTRL_PIN(6, "GPIO_6"),
121 PINCTRL_PIN(7, "GPIO_7"),
122 PINCTRL_PIN(8, "GPIO_8"),
123 PINCTRL_PIN(9, "GPIO_9"),
124 PINCTRL_PIN(10, "GPIO_10"),
125 PINCTRL_PIN(11, "GPIO_11"),
126 PINCTRL_PIN(12, "GPIO_12"),
127 PINCTRL_PIN(13, "GPIO_13"),
128 PINCTRL_PIN(14, "GPIO_14"),
129 PINCTRL_PIN(15, "GPIO_15"),
130 PINCTRL_PIN(16, "GPIO_16"),
131 PINCTRL_PIN(17, "GPIO_17"),
132 PINCTRL_PIN(18, "GPIO_18"),
133 PINCTRL_PIN(19, "GPIO_19"),
134 PINCTRL_PIN(20, "GPIO_20"),
135 PINCTRL_PIN(21, "GPIO_21"),
136 PINCTRL_PIN(22, "GPIO_22"),
137 PINCTRL_PIN(23, "GPIO_23"),
138 PINCTRL_PIN(24, "GPIO_24"),
139 PINCTRL_PIN(25, "GPIO_25"),
140 PINCTRL_PIN(26, "GPIO_26"),
141 PINCTRL_PIN(27, "GPIO_27"),
142 PINCTRL_PIN(28, "GPIO_28"),
143 PINCTRL_PIN(29, "GPIO_29"),
144 PINCTRL_PIN(30, "GPIO_30"),
145 PINCTRL_PIN(31, "GPIO_31"),
146 PINCTRL_PIN(32, "GPIO_32"),
147 PINCTRL_PIN(33, "GPIO_33"),
148 PINCTRL_PIN(34, "GPIO_34"),
149 PINCTRL_PIN(35, "GPIO_35"),
150 PINCTRL_PIN(36, "GPIO_36"),
151 PINCTRL_PIN(37, "GPIO_37"),
152 PINCTRL_PIN(38, "GPIO_38"),
153 PINCTRL_PIN(39, "GPIO_39"),
154 PINCTRL_PIN(40, "GPIO_40"),
155 PINCTRL_PIN(41, "GPIO_41"),
156 PINCTRL_PIN(42, "GPIO_42"),
157 PINCTRL_PIN(43, "GPIO_43"),
158 PINCTRL_PIN(44, "GPIO_44"),
159 PINCTRL_PIN(45, "GPIO_45"),
160 PINCTRL_PIN(46, "GPIO_46"),
161 PINCTRL_PIN(47, "GPIO_47"),
162 PINCTRL_PIN(48, "GPIO_48"),
163 PINCTRL_PIN(49, "GPIO_49"),
164 PINCTRL_PIN(50, "GPIO_50"),
165 PINCTRL_PIN(51, "GPIO_51"),
166 PINCTRL_PIN(52, "GPIO_52"),
167 PINCTRL_PIN(53, "GPIO_53"),
168 PINCTRL_PIN(54, "GPIO_54"),
169 PINCTRL_PIN(55, "GPIO_55"),
170 PINCTRL_PIN(56, "GPIO_56"),
171 PINCTRL_PIN(57, "GPIO_57"),
172 PINCTRL_PIN(58, "GPIO_58"),
173 PINCTRL_PIN(59, "GPIO_59"),
174 PINCTRL_PIN(60, "GPIO_60"),
175 PINCTRL_PIN(61, "GPIO_61"),
176 PINCTRL_PIN(62, "GPIO_62"),
177 PINCTRL_PIN(63, "GPIO_63"),
178 PINCTRL_PIN(64, "GPIO_64"),
179 PINCTRL_PIN(65, "GPIO_65"),
180 PINCTRL_PIN(66, "GPIO_66"),
181 PINCTRL_PIN(67, "GPIO_67"),
182 PINCTRL_PIN(68, "GPIO_68"),
183 PINCTRL_PIN(69, "GPIO_69"),
184 PINCTRL_PIN(70, "GPIO_70"),
185 PINCTRL_PIN(71, "GPIO_71"),
186 PINCTRL_PIN(72, "GPIO_72"),
187 PINCTRL_PIN(73, "GPIO_73"),
188 PINCTRL_PIN(74, "GPIO_74"),
189 PINCTRL_PIN(75, "GPIO_75"),
190 PINCTRL_PIN(76, "GPIO_76"),
191 PINCTRL_PIN(77, "GPIO_77"),
192 PINCTRL_PIN(78, "GPIO_78"),
193 PINCTRL_PIN(79, "GPIO_79"),
194 PINCTRL_PIN(80, "GPIO_80"),
195 PINCTRL_PIN(81, "GPIO_81"),
196 PINCTRL_PIN(82, "GPIO_82"),
197 PINCTRL_PIN(83, "GPIO_83"),
198 PINCTRL_PIN(84, "GPIO_84"),
199 PINCTRL_PIN(85, "GPIO_85"),
200 PINCTRL_PIN(86, "GPIO_86"),
201 PINCTRL_PIN(87, "GPIO_87"),
202 PINCTRL_PIN(88, "GPIO_88"),
203 PINCTRL_PIN(89, "GPIO_89"),
204 PINCTRL_PIN(90, "GPIO_90"),
205 PINCTRL_PIN(91, "GPIO_91"),
206 PINCTRL_PIN(92, "GPIO_92"),
207 PINCTRL_PIN(93, "GPIO_93"),
208 PINCTRL_PIN(94, "GPIO_94"),
209 PINCTRL_PIN(95, "GPIO_95"),
210 PINCTRL_PIN(96, "GPIO_96"),
211 PINCTRL_PIN(97, "GPIO_97"),
212 PINCTRL_PIN(98, "GPIO_98"),
213 PINCTRL_PIN(99, "GPIO_99"),
214 PINCTRL_PIN(100, "GPIO_100"),
215 PINCTRL_PIN(101, "GPIO_101"),
216 PINCTRL_PIN(102, "GPIO_102"),
217 PINCTRL_PIN(103, "GPIO_103"),
218 PINCTRL_PIN(104, "GPIO_104"),
219 PINCTRL_PIN(105, "GPIO_105"),
220 PINCTRL_PIN(106, "GPIO_106"),
221 PINCTRL_PIN(107, "GPIO_107"),
222 PINCTRL_PIN(108, "GPIO_108"),
223 PINCTRL_PIN(109, "GPIO_109"),
224 PINCTRL_PIN(110, "GPIO_110"),
225 PINCTRL_PIN(111, "GPIO_111"),
226 PINCTRL_PIN(112, "GPIO_112"),
227 PINCTRL_PIN(113, "GPIO_113"),
228 PINCTRL_PIN(114, "GPIO_114"),
229 PINCTRL_PIN(115, "GPIO_115"),
230 PINCTRL_PIN(116, "GPIO_116"),
231 PINCTRL_PIN(117, "GPIO_117"),
232 PINCTRL_PIN(118, "GPIO_118"),
233 PINCTRL_PIN(119, "GPIO_119"),
234 PINCTRL_PIN(120, "GPIO_120"),
235 PINCTRL_PIN(121, "GPIO_121"),
236 PINCTRL_PIN(122, "GPIO_122"),
237 PINCTRL_PIN(123, "GPIO_123"),
238 PINCTRL_PIN(124, "GPIO_124"),
239 PINCTRL_PIN(125, "GPIO_125"),
240 PINCTRL_PIN(126, "GPIO_126"),
241 PINCTRL_PIN(127, "GPIO_127"),
242 PINCTRL_PIN(128, "GPIO_128"),
243 PINCTRL_PIN(129, "GPIO_129"),
244 PINCTRL_PIN(130, "GPIO_130"),
245 PINCTRL_PIN(131, "GPIO_131"),
246 PINCTRL_PIN(132, "GPIO_132"),
247 PINCTRL_PIN(133, "GPIO_133"),
248 PINCTRL_PIN(134, "GPIO_134"),
249 PINCTRL_PIN(135, "GPIO_135"),
250 PINCTRL_PIN(136, "GPIO_136"),
251 PINCTRL_PIN(137, "GPIO_137"),
252 PINCTRL_PIN(138, "GPIO_138"),
253 PINCTRL_PIN(139, "GPIO_139"),
254 PINCTRL_PIN(140, "GPIO_140"),
255 PINCTRL_PIN(141, "GPIO_141"),
256 PINCTRL_PIN(142, "GPIO_142"),
257 PINCTRL_PIN(143, "GPIO_143"),
258 PINCTRL_PIN(144, "GPIO_144"),
259 PINCTRL_PIN(145, "GPIO_145"),
260 PINCTRL_PIN(146, "GPIO_146"),
261 PINCTRL_PIN(147, "GPIO_147"),
262 PINCTRL_PIN(148, "GPIO_148"),
263 PINCTRL_PIN(149, "GPIO_149"),
264 PINCTRL_PIN(150, "SDC2_CLK"),
265 PINCTRL_PIN(151, "SDC2_CMD"),
266 PINCTRL_PIN(152, "SDC2_DATA"),
267 PINCTRL_PIN(153, "UFS_RESET"),
268 };
269
270 #define DECLARE_MSM_GPIO_PINS(pin) \
271 static const unsigned int gpio##pin##_pins[] = { pin }
272 DECLARE_MSM_GPIO_PINS(0);
273 DECLARE_MSM_GPIO_PINS(1);
274 DECLARE_MSM_GPIO_PINS(2);
275 DECLARE_MSM_GPIO_PINS(3);
276 DECLARE_MSM_GPIO_PINS(4);
277 DECLARE_MSM_GPIO_PINS(5);
278 DECLARE_MSM_GPIO_PINS(6);
279 DECLARE_MSM_GPIO_PINS(7);
280 DECLARE_MSM_GPIO_PINS(8);
281 DECLARE_MSM_GPIO_PINS(9);
282 DECLARE_MSM_GPIO_PINS(10);
283 DECLARE_MSM_GPIO_PINS(11);
284 DECLARE_MSM_GPIO_PINS(12);
285 DECLARE_MSM_GPIO_PINS(13);
286 DECLARE_MSM_GPIO_PINS(14);
287 DECLARE_MSM_GPIO_PINS(15);
288 DECLARE_MSM_GPIO_PINS(16);
289 DECLARE_MSM_GPIO_PINS(17);
290 DECLARE_MSM_GPIO_PINS(18);
291 DECLARE_MSM_GPIO_PINS(19);
292 DECLARE_MSM_GPIO_PINS(20);
293 DECLARE_MSM_GPIO_PINS(21);
294 DECLARE_MSM_GPIO_PINS(22);
295 DECLARE_MSM_GPIO_PINS(23);
296 DECLARE_MSM_GPIO_PINS(24);
297 DECLARE_MSM_GPIO_PINS(25);
298 DECLARE_MSM_GPIO_PINS(26);
299 DECLARE_MSM_GPIO_PINS(27);
300 DECLARE_MSM_GPIO_PINS(28);
301 DECLARE_MSM_GPIO_PINS(29);
302 DECLARE_MSM_GPIO_PINS(30);
303 DECLARE_MSM_GPIO_PINS(31);
304 DECLARE_MSM_GPIO_PINS(32);
305 DECLARE_MSM_GPIO_PINS(33);
306 DECLARE_MSM_GPIO_PINS(34);
307 DECLARE_MSM_GPIO_PINS(35);
308 DECLARE_MSM_GPIO_PINS(36);
309 DECLARE_MSM_GPIO_PINS(37);
310 DECLARE_MSM_GPIO_PINS(38);
311 DECLARE_MSM_GPIO_PINS(39);
312 DECLARE_MSM_GPIO_PINS(40);
313 DECLARE_MSM_GPIO_PINS(41);
314 DECLARE_MSM_GPIO_PINS(42);
315 DECLARE_MSM_GPIO_PINS(43);
316 DECLARE_MSM_GPIO_PINS(44);
317 DECLARE_MSM_GPIO_PINS(45);
318 DECLARE_MSM_GPIO_PINS(46);
319 DECLARE_MSM_GPIO_PINS(47);
320 DECLARE_MSM_GPIO_PINS(48);
321 DECLARE_MSM_GPIO_PINS(49);
322 DECLARE_MSM_GPIO_PINS(50);
323 DECLARE_MSM_GPIO_PINS(51);
324 DECLARE_MSM_GPIO_PINS(52);
325 DECLARE_MSM_GPIO_PINS(53);
326 DECLARE_MSM_GPIO_PINS(54);
327 DECLARE_MSM_GPIO_PINS(55);
328 DECLARE_MSM_GPIO_PINS(56);
329 DECLARE_MSM_GPIO_PINS(57);
330 DECLARE_MSM_GPIO_PINS(58);
331 DECLARE_MSM_GPIO_PINS(59);
332 DECLARE_MSM_GPIO_PINS(60);
333 DECLARE_MSM_GPIO_PINS(61);
334 DECLARE_MSM_GPIO_PINS(62);
335 DECLARE_MSM_GPIO_PINS(63);
336 DECLARE_MSM_GPIO_PINS(64);
337 DECLARE_MSM_GPIO_PINS(65);
338 DECLARE_MSM_GPIO_PINS(66);
339 DECLARE_MSM_GPIO_PINS(67);
340 DECLARE_MSM_GPIO_PINS(68);
341 DECLARE_MSM_GPIO_PINS(69);
342 DECLARE_MSM_GPIO_PINS(70);
343 DECLARE_MSM_GPIO_PINS(71);
344 DECLARE_MSM_GPIO_PINS(72);
345 DECLARE_MSM_GPIO_PINS(73);
346 DECLARE_MSM_GPIO_PINS(74);
347 DECLARE_MSM_GPIO_PINS(75);
348 DECLARE_MSM_GPIO_PINS(76);
349 DECLARE_MSM_GPIO_PINS(77);
350 DECLARE_MSM_GPIO_PINS(78);
351 DECLARE_MSM_GPIO_PINS(79);
352 DECLARE_MSM_GPIO_PINS(80);
353 DECLARE_MSM_GPIO_PINS(81);
354 DECLARE_MSM_GPIO_PINS(82);
355 DECLARE_MSM_GPIO_PINS(83);
356 DECLARE_MSM_GPIO_PINS(84);
357 DECLARE_MSM_GPIO_PINS(85);
358 DECLARE_MSM_GPIO_PINS(86);
359 DECLARE_MSM_GPIO_PINS(87);
360 DECLARE_MSM_GPIO_PINS(88);
361 DECLARE_MSM_GPIO_PINS(89);
362 DECLARE_MSM_GPIO_PINS(90);
363 DECLARE_MSM_GPIO_PINS(91);
364 DECLARE_MSM_GPIO_PINS(92);
365 DECLARE_MSM_GPIO_PINS(93);
366 DECLARE_MSM_GPIO_PINS(94);
367 DECLARE_MSM_GPIO_PINS(95);
368 DECLARE_MSM_GPIO_PINS(96);
369 DECLARE_MSM_GPIO_PINS(97);
370 DECLARE_MSM_GPIO_PINS(98);
371 DECLARE_MSM_GPIO_PINS(99);
372 DECLARE_MSM_GPIO_PINS(100);
373 DECLARE_MSM_GPIO_PINS(101);
374 DECLARE_MSM_GPIO_PINS(102);
375 DECLARE_MSM_GPIO_PINS(103);
376 DECLARE_MSM_GPIO_PINS(104);
377 DECLARE_MSM_GPIO_PINS(105);
378 DECLARE_MSM_GPIO_PINS(106);
379 DECLARE_MSM_GPIO_PINS(107);
380 DECLARE_MSM_GPIO_PINS(108);
381 DECLARE_MSM_GPIO_PINS(109);
382 DECLARE_MSM_GPIO_PINS(110);
383 DECLARE_MSM_GPIO_PINS(111);
384 DECLARE_MSM_GPIO_PINS(112);
385 DECLARE_MSM_GPIO_PINS(113);
386 DECLARE_MSM_GPIO_PINS(114);
387 DECLARE_MSM_GPIO_PINS(115);
388 DECLARE_MSM_GPIO_PINS(116);
389 DECLARE_MSM_GPIO_PINS(117);
390 DECLARE_MSM_GPIO_PINS(118);
391 DECLARE_MSM_GPIO_PINS(119);
392 DECLARE_MSM_GPIO_PINS(120);
393 DECLARE_MSM_GPIO_PINS(121);
394 DECLARE_MSM_GPIO_PINS(122);
395 DECLARE_MSM_GPIO_PINS(123);
396 DECLARE_MSM_GPIO_PINS(124);
397 DECLARE_MSM_GPIO_PINS(125);
398 DECLARE_MSM_GPIO_PINS(126);
399 DECLARE_MSM_GPIO_PINS(127);
400 DECLARE_MSM_GPIO_PINS(128);
401 DECLARE_MSM_GPIO_PINS(129);
402 DECLARE_MSM_GPIO_PINS(130);
403 DECLARE_MSM_GPIO_PINS(131);
404 DECLARE_MSM_GPIO_PINS(132);
405 DECLARE_MSM_GPIO_PINS(133);
406 DECLARE_MSM_GPIO_PINS(134);
407 DECLARE_MSM_GPIO_PINS(135);
408 DECLARE_MSM_GPIO_PINS(136);
409 DECLARE_MSM_GPIO_PINS(137);
410 DECLARE_MSM_GPIO_PINS(138);
411 DECLARE_MSM_GPIO_PINS(139);
412 DECLARE_MSM_GPIO_PINS(140);
413 DECLARE_MSM_GPIO_PINS(141);
414 DECLARE_MSM_GPIO_PINS(142);
415 DECLARE_MSM_GPIO_PINS(143);
416 DECLARE_MSM_GPIO_PINS(144);
417 DECLARE_MSM_GPIO_PINS(145);
418 DECLARE_MSM_GPIO_PINS(146);
419 DECLARE_MSM_GPIO_PINS(147);
420 DECLARE_MSM_GPIO_PINS(148);
421 DECLARE_MSM_GPIO_PINS(149);
422
423 static const unsigned int sdc2_clk_pins[] = { 150 };
424 static const unsigned int sdc2_cmd_pins[] = { 151 };
425 static const unsigned int sdc2_data_pins[] = { 152 };
426 static const unsigned int ufs_reset_pins[] = { 153 };
427
428 enum msm8998_functions {
429 msm_mux_adsp_ext,
430 msm_mux_agera_pll,
431 msm_mux_atest_char,
432 msm_mux_atest_gpsadc0,
433 msm_mux_atest_gpsadc1,
434 msm_mux_atest_tsens,
435 msm_mux_atest_tsens2,
436 msm_mux_atest_usb1,
437 msm_mux_atest_usb10,
438 msm_mux_atest_usb11,
439 msm_mux_atest_usb12,
440 msm_mux_atest_usb13,
441 msm_mux_audio_ref,
442 msm_mux_bimc_dte0,
443 msm_mux_bimc_dte1,
444 msm_mux_blsp10_spi,
445 msm_mux_blsp10_spi_a,
446 msm_mux_blsp10_spi_b,
447 msm_mux_blsp11_i2c,
448 msm_mux_blsp1_spi,
449 msm_mux_blsp1_spi_a,
450 msm_mux_blsp1_spi_b,
451 msm_mux_blsp2_spi,
452 msm_mux_blsp9_spi,
453 msm_mux_blsp_i2c1,
454 msm_mux_blsp_i2c10,
455 msm_mux_blsp_i2c11,
456 msm_mux_blsp_i2c12,
457 msm_mux_blsp_i2c2,
458 msm_mux_blsp_i2c3,
459 msm_mux_blsp_i2c4,
460 msm_mux_blsp_i2c5,
461 msm_mux_blsp_i2c6,
462 msm_mux_blsp_i2c7,
463 msm_mux_blsp_i2c8,
464 msm_mux_blsp_i2c9,
465 msm_mux_blsp_spi1,
466 msm_mux_blsp_spi10,
467 msm_mux_blsp_spi11,
468 msm_mux_blsp_spi12,
469 msm_mux_blsp_spi2,
470 msm_mux_blsp_spi3,
471 msm_mux_blsp_spi4,
472 msm_mux_blsp_spi5,
473 msm_mux_blsp_spi6,
474 msm_mux_blsp_spi7,
475 msm_mux_blsp_spi8,
476 msm_mux_blsp_spi9,
477 msm_mux_blsp_uart1_a,
478 msm_mux_blsp_uart1_b,
479 msm_mux_blsp_uart2_a,
480 msm_mux_blsp_uart2_b,
481 msm_mux_blsp_uart3_a,
482 msm_mux_blsp_uart3_b,
483 msm_mux_blsp_uart7_a,
484 msm_mux_blsp_uart7_b,
485 msm_mux_blsp_uart8,
486 msm_mux_blsp_uart8_a,
487 msm_mux_blsp_uart8_b,
488 msm_mux_blsp_uart9_a,
489 msm_mux_blsp_uart9_b,
490 msm_mux_blsp_uim1_a,
491 msm_mux_blsp_uim1_b,
492 msm_mux_blsp_uim2_a,
493 msm_mux_blsp_uim2_b,
494 msm_mux_blsp_uim3_a,
495 msm_mux_blsp_uim3_b,
496 msm_mux_blsp_uim7_a,
497 msm_mux_blsp_uim7_b,
498 msm_mux_blsp_uim8_a,
499 msm_mux_blsp_uim8_b,
500 msm_mux_blsp_uim9_a,
501 msm_mux_blsp_uim9_b,
502 msm_mux_bt_reset,
503 msm_mux_btfm_slimbus,
504 msm_mux_cam_mclk,
505 msm_mux_cci_async,
506 msm_mux_cci_i2c,
507 msm_mux_cci_timer0,
508 msm_mux_cci_timer1,
509 msm_mux_cci_timer2,
510 msm_mux_cci_timer3,
511 msm_mux_cci_timer4,
512 msm_mux_cri_trng,
513 msm_mux_cri_trng0,
514 msm_mux_cri_trng1,
515 msm_mux_dbg_out,
516 msm_mux_ddr_bist,
517 msm_mux_edp_hot,
518 msm_mux_edp_lcd,
519 msm_mux_gcc_gp1_a,
520 msm_mux_gcc_gp1_b,
521 msm_mux_gcc_gp2_a,
522 msm_mux_gcc_gp2_b,
523 msm_mux_gcc_gp3_a,
524 msm_mux_gcc_gp3_b,
525 msm_mux_gpio,
526 msm_mux_hdmi_cec,
527 msm_mux_hdmi_ddc,
528 msm_mux_hdmi_hot,
529 msm_mux_hdmi_rcv,
530 msm_mux_isense_dbg,
531 msm_mux_jitter_bist,
532 msm_mux_ldo_en,
533 msm_mux_ldo_update,
534 msm_mux_lpass_slimbus,
535 msm_mux_m_voc,
536 msm_mux_mdp_vsync,
537 msm_mux_mdp_vsync0,
538 msm_mux_mdp_vsync1,
539 msm_mux_mdp_vsync2,
540 msm_mux_mdp_vsync3,
541 msm_mux_mdp_vsync_a,
542 msm_mux_mdp_vsync_b,
543 msm_mux_modem_tsync,
544 msm_mux_mss_lte,
545 msm_mux_nav_dr,
546 msm_mux_nav_pps,
547 msm_mux_pa_indicator,
548 msm_mux_pci_e0,
549 msm_mux_phase_flag,
550 msm_mux_pll_bypassnl,
551 msm_mux_pll_reset,
552 msm_mux_pri_mi2s,
553 msm_mux_pri_mi2s_ws,
554 msm_mux_prng_rosc,
555 msm_mux_pwr_crypto,
556 msm_mux_pwr_modem,
557 msm_mux_pwr_nav,
558 msm_mux_qdss_cti0_a,
559 msm_mux_qdss_cti0_b,
560 msm_mux_qdss_cti1_a,
561 msm_mux_qdss_cti1_b,
562 msm_mux_qdss,
563 msm_mux_qlink_enable,
564 msm_mux_qlink_request,
565 msm_mux_qua_mi2s,
566 msm_mux_sd_card,
567 msm_mux_sd_write,
568 msm_mux_sdc40,
569 msm_mux_sdc41,
570 msm_mux_sdc42,
571 msm_mux_sdc43,
572 msm_mux_sdc4_clk,
573 msm_mux_sdc4_cmd,
574 msm_mux_sec_mi2s,
575 msm_mux_sp_cmu,
576 msm_mux_spkr_i2s,
577 msm_mux_ssbi1,
578 msm_mux_ssc_irq,
579 msm_mux_ter_mi2s,
580 msm_mux_tgu_ch0,
581 msm_mux_tgu_ch1,
582 msm_mux_tsense_pwm1,
583 msm_mux_tsense_pwm2,
584 msm_mux_tsif0,
585 msm_mux_tsif1,
586 msm_mux_uim1_clk,
587 msm_mux_uim1_data,
588 msm_mux_uim1_present,
589 msm_mux_uim1_reset,
590 msm_mux_uim2_clk,
591 msm_mux_uim2_data,
592 msm_mux_uim2_present,
593 msm_mux_uim2_reset,
594 msm_mux_uim_batt,
595 msm_mux_usb_phy,
596 msm_mux_vfr_1,
597 msm_mux_vsense_clkout,
598 msm_mux_vsense_data0,
599 msm_mux_vsense_data1,
600 msm_mux_vsense_mode,
601 msm_mux_wlan1_adc0,
602 msm_mux_wlan1_adc1,
603 msm_mux_wlan2_adc0,
604 msm_mux_wlan2_adc1,
605 msm_mux__,
606 };
607
608 static const char * const gpio_groups[] = {
609 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
610 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
611 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
612 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
613 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
614 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
615 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
616 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
617 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
618 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
619 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
620 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
621 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
622 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
623 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
624 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
625 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
626 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
627 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
628 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
629 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
630 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
631 "gpio147", "gpio148", "gpio149",
632 };
633 static const char * const blsp_spi1_groups[] = {
634 "gpio0", "gpio1", "gpio2", "gpio3",
635 };
636 static const char * const blsp_uim1_a_groups[] = {
637 "gpio0", "gpio1",
638 };
639 static const char * const blsp_uart1_a_groups[] = {
640 "gpio0", "gpio1", "gpio2", "gpio3",
641 };
642 static const char * const blsp_i2c1_groups[] = {
643 "gpio2", "gpio3",
644 };
645 static const char * const blsp_spi8_groups[] = {
646 "gpio4", "gpio5", "gpio6", "gpio7",
647 };
648 static const char * const blsp_uart8_a_groups[] = {
649 "gpio4", "gpio5", "gpio6", "gpio7",
650 };
651 static const char * const blsp_uim8_a_groups[] = {
652 "gpio4", "gpio5",
653 };
654 static const char * const qdss_cti0_b_groups[] = {
655 "gpio4", "gpio5",
656 };
657 static const char * const blsp_i2c8_groups[] = {
658 "gpio6", "gpio7",
659 };
660 static const char * const ddr_bist_groups[] = {
661 "gpio7", "gpio8", "gpio9", "gpio10",
662 };
663 static const char * const atest_tsens2_groups[] = {
664 "gpio7",
665 };
666 static const char * const atest_usb1_groups[] = {
667 "gpio7",
668 };
669 static const char * const blsp_spi4_groups[] = {
670 "gpio8", "gpio9", "gpio10", "gpio11",
671 };
672 static const char * const blsp_uart1_b_groups[] = {
673 "gpio8", "gpio9", "gpio10", "gpio11",
674 };
675 static const char * const blsp_uim1_b_groups[] = {
676 "gpio8", "gpio9",
677 };
678 static const char * const wlan1_adc1_groups[] = {
679 "gpio8",
680 };
681 static const char * const atest_usb13_groups[] = {
682 "gpio8",
683 };
684 static const char * const bimc_dte1_groups[] = {
685 "gpio8", "gpio10",
686 };
687 static const char * const wlan1_adc0_groups[] = {
688 "gpio9",
689 };
690 static const char * const atest_usb12_groups[] = {
691 "gpio9",
692 };
693 static const char * const bimc_dte0_groups[] = {
694 "gpio9", "gpio11",
695 };
696 static const char * const mdp_vsync_a_groups[] = {
697 "gpio10", "gpio11",
698 };
699 static const char * const blsp_i2c4_groups[] = {
700 "gpio10", "gpio11",
701 };
702 static const char * const atest_gpsadc1_groups[] = {
703 "gpio10",
704 };
705 static const char * const wlan2_adc1_groups[] = {
706 "gpio10",
707 };
708 static const char * const atest_usb11_groups[] = {
709 "gpio10",
710 };
711 static const char * const edp_lcd_groups[] = {
712 "gpio11",
713 };
714 static const char * const dbg_out_groups[] = {
715 "gpio11",
716 };
717 static const char * const atest_gpsadc0_groups[] = {
718 "gpio11",
719 };
720 static const char * const wlan2_adc0_groups[] = {
721 "gpio11",
722 };
723 static const char * const atest_usb10_groups[] = {
724 "gpio11",
725 };
726 static const char * const mdp_vsync_groups[] = {
727 "gpio12",
728 };
729 static const char * const m_voc_groups[] = {
730 "gpio12",
731 };
732 static const char * const cam_mclk_groups[] = {
733 "gpio13", "gpio14", "gpio15", "gpio16",
734 };
735 static const char * const pll_bypassnl_groups[] = {
736 "gpio13",
737 };
738 static const char * const qdss_groups[] = {
739 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
740 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
741 "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
742 "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
743 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
744 "gpio123", "gpio124",
745 };
746 static const char * const pll_reset_groups[] = {
747 "gpio14",
748 };
749 static const char * const cci_i2c_groups[] = {
750 "gpio17", "gpio18", "gpio19", "gpio20",
751 };
752 static const char * const phase_flag_groups[] = {
753 "gpio18", "gpio19", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
754 "gpio89", "gpio91", "gpio92", "gpio96", "gpio114", "gpio115",
755 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
756 "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio128",
757 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
758 };
759 static const char * const cci_timer4_groups[] = {
760 "gpio25",
761 };
762 static const char * const blsp2_spi_groups[] = {
763 "gpio25", "gpio29", "gpio30",
764 };
765 static const char * const cci_timer0_groups[] = {
766 "gpio21",
767 };
768 static const char * const vsense_data0_groups[] = {
769 "gpio21",
770 };
771 static const char * const cci_timer1_groups[] = {
772 "gpio22",
773 };
774 static const char * const vsense_data1_groups[] = {
775 "gpio22",
776 };
777 static const char * const cci_timer2_groups[] = {
778 "gpio23",
779 };
780 static const char * const blsp1_spi_b_groups[] = {
781 "gpio23", "gpio28",
782 };
783 static const char * const vsense_mode_groups[] = {
784 "gpio23",
785 };
786 static const char * const cci_timer3_groups[] = {
787 "gpio24",
788 };
789 static const char * const cci_async_groups[] = {
790 "gpio24", "gpio25", "gpio26",
791 };
792 static const char * const blsp1_spi_a_groups[] = {
793 "gpio24", "gpio27",
794 };
795 static const char * const vsense_clkout_groups[] = {
796 "gpio24",
797 };
798 static const char * const hdmi_rcv_groups[] = {
799 "gpio30",
800 };
801 static const char * const hdmi_cec_groups[] = {
802 "gpio31",
803 };
804 static const char * const blsp_spi2_groups[] = {
805 "gpio31", "gpio32", "gpio33", "gpio34",
806 };
807 static const char * const blsp_uart2_a_groups[] = {
808 "gpio31", "gpio32", "gpio33", "gpio34",
809 };
810 static const char * const blsp_uim2_a_groups[] = {
811 "gpio31", "gpio34",
812 };
813 static const char * const pwr_modem_groups[] = {
814 "gpio31",
815 };
816 static const char * const hdmi_ddc_groups[] = {
817 "gpio32", "gpio33",
818 };
819 static const char * const blsp_i2c2_groups[] = {
820 "gpio32", "gpio33",
821 };
822 static const char * const pwr_nav_groups[] = {
823 "gpio32",
824 };
825 static const char * const pwr_crypto_groups[] = {
826 "gpio33",
827 };
828 static const char * const hdmi_hot_groups[] = {
829 "gpio34",
830 };
831 static const char * const edp_hot_groups[] = {
832 "gpio34",
833 };
834 static const char * const pci_e0_groups[] = {
835 "gpio35", "gpio36", "gpio37",
836 };
837 static const char * const jitter_bist_groups[] = {
838 "gpio35",
839 };
840 static const char * const agera_pll_groups[] = {
841 "gpio36", "gpio37",
842 };
843 static const char * const atest_tsens_groups[] = {
844 "gpio36",
845 };
846 static const char * const usb_phy_groups[] = {
847 "gpio38",
848 };
849 static const char * const lpass_slimbus_groups[] = {
850 "gpio39", "gpio70", "gpio71", "gpio72",
851 };
852 static const char * const sd_write_groups[] = {
853 "gpio40",
854 };
855 static const char * const blsp_spi6_groups[] = {
856 "gpio41", "gpio42", "gpio43", "gpio44",
857 };
858 static const char * const blsp_uart3_b_groups[] = {
859 "gpio41", "gpio42", "gpio43", "gpio44",
860 };
861 static const char * const blsp_uim3_b_groups[] = {
862 "gpio41", "gpio42",
863 };
864 static const char * const blsp_i2c6_groups[] = {
865 "gpio43", "gpio44",
866 };
867 static const char * const bt_reset_groups[] = {
868 "gpio45",
869 };
870 static const char * const blsp_spi3_groups[] = {
871 "gpio45", "gpio46", "gpio47", "gpio48",
872 };
873 static const char * const blsp_uart3_a_groups[] = {
874 "gpio45", "gpio46", "gpio47", "gpio48",
875 };
876 static const char * const blsp_uim3_a_groups[] = {
877 "gpio45", "gpio46",
878 };
879 static const char * const blsp_i2c3_groups[] = {
880 "gpio47", "gpio48",
881 };
882 static const char * const blsp_spi9_groups[] = {
883 "gpio49", "gpio50", "gpio51", "gpio52",
884 };
885 static const char * const blsp_uart9_a_groups[] = {
886 "gpio49", "gpio50", "gpio51", "gpio52",
887 };
888 static const char * const blsp_uim9_a_groups[] = {
889 "gpio49", "gpio50",
890 };
891 static const char * const blsp10_spi_b_groups[] = {
892 "gpio49", "gpio50",
893 };
894 static const char * const qdss_cti0_a_groups[] = {
895 "gpio49", "gpio50",
896 };
897 static const char * const blsp_i2c9_groups[] = {
898 "gpio51", "gpio52",
899 };
900 static const char * const blsp10_spi_a_groups[] = {
901 "gpio51", "gpio52",
902 };
903 static const char * const blsp_spi7_groups[] = {
904 "gpio53", "gpio54", "gpio55", "gpio56",
905 };
906 static const char * const blsp_uart7_a_groups[] = {
907 "gpio53", "gpio54", "gpio55", "gpio56",
908 };
909 static const char * const blsp_uim7_a_groups[] = {
910 "gpio53", "gpio54",
911 };
912 static const char * const blsp_i2c7_groups[] = {
913 "gpio55", "gpio56",
914 };
915 static const char * const qua_mi2s_groups[] = {
916 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
917 };
918 static const char * const blsp10_spi_groups[] = {
919 "gpio57",
920 };
921 static const char * const gcc_gp1_a_groups[] = {
922 "gpio57",
923 };
924 static const char * const ssc_irq_groups[] = {
925 "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio78",
926 "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", "gpio120",
927 "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
928 };
929 static const char * const blsp_spi11_groups[] = {
930 "gpio58", "gpio59", "gpio60", "gpio61",
931 };
932 static const char * const blsp_uart8_b_groups[] = {
933 "gpio58", "gpio59", "gpio60", "gpio61",
934 };
935 static const char * const blsp_uim8_b_groups[] = {
936 "gpio58", "gpio59",
937 };
938 static const char * const gcc_gp2_a_groups[] = {
939 "gpio58",
940 };
941 static const char * const qdss_cti1_a_groups[] = {
942 "gpio58", "gpio59",
943 };
944 static const char * const gcc_gp3_a_groups[] = {
945 "gpio59",
946 };
947 static const char * const blsp_i2c11_groups[] = {
948 "gpio60", "gpio61",
949 };
950 static const char * const cri_trng0_groups[] = {
951 "gpio60",
952 };
953 static const char * const cri_trng1_groups[] = {
954 "gpio61",
955 };
956 static const char * const cri_trng_groups[] = {
957 "gpio62",
958 };
959 static const char * const pri_mi2s_groups[] = {
960 "gpio64", "gpio65", "gpio67", "gpio68",
961 };
962 static const char * const sp_cmu_groups[] = {
963 "gpio64",
964 };
965 static const char * const blsp_spi10_groups[] = {
966 "gpio65", "gpio66", "gpio67", "gpio68",
967 };
968 static const char * const blsp_uart7_b_groups[] = {
969 "gpio65", "gpio66", "gpio67", "gpio68",
970 };
971 static const char * const blsp_uim7_b_groups[] = {
972 "gpio65", "gpio66",
973 };
974 static const char * const pri_mi2s_ws_groups[] = {
975 "gpio66",
976 };
977 static const char * const blsp_i2c10_groups[] = {
978 "gpio67", "gpio68",
979 };
980 static const char * const spkr_i2s_groups[] = {
981 "gpio69", "gpio70", "gpio71", "gpio72",
982 };
983 static const char * const audio_ref_groups[] = {
984 "gpio69",
985 };
986 static const char * const blsp9_spi_groups[] = {
987 "gpio70", "gpio71", "gpio72",
988 };
989 static const char * const tsense_pwm1_groups[] = {
990 "gpio71",
991 };
992 static const char * const tsense_pwm2_groups[] = {
993 "gpio71",
994 };
995 static const char * const btfm_slimbus_groups[] = {
996 "gpio73", "gpio74",
997 };
998 static const char * const ter_mi2s_groups[] = {
999 "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
1000 };
1001 static const char * const gcc_gp1_b_groups[] = {
1002 "gpio78",
1003 };
1004 static const char * const sec_mi2s_groups[] = {
1005 "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
1006 };
1007 static const char * const blsp_spi12_groups[] = {
1008 "gpio81", "gpio82", "gpio83", "gpio84",
1009 };
1010 static const char * const blsp_uart9_b_groups[] = {
1011 "gpio81", "gpio82", "gpio83", "gpio84",
1012 };
1013 static const char * const blsp_uim9_b_groups[] = {
1014 "gpio81", "gpio82",
1015 };
1016 static const char * const gcc_gp2_b_groups[] = {
1017 "gpio81",
1018 };
1019 static const char * const gcc_gp3_b_groups[] = {
1020 "gpio82",
1021 };
1022 static const char * const blsp_i2c12_groups[] = {
1023 "gpio83", "gpio84",
1024 };
1025 static const char * const blsp_spi5_groups[] = {
1026 "gpio85", "gpio86", "gpio87", "gpio88",
1027 };
1028 static const char * const blsp_uart2_b_groups[] = {
1029 "gpio85", "gpio86", "gpio87", "gpio88",
1030 };
1031 static const char * const blsp_uim2_b_groups[] = {
1032 "gpio85", "gpio86",
1033 };
1034 static const char * const blsp_i2c5_groups[] = {
1035 "gpio87", "gpio88",
1036 };
1037 static const char * const tsif0_groups[] = {
1038 "gpio9", "gpio40", "gpio89", "gpio90", "gpio91",
1039 };
1040 static const char * const mdp_vsync0_groups[] = {
1041 "gpio90",
1042 };
1043 static const char * const mdp_vsync1_groups[] = {
1044 "gpio90",
1045 };
1046 static const char * const mdp_vsync2_groups[] = {
1047 "gpio90",
1048 };
1049 static const char * const mdp_vsync3_groups[] = {
1050 "gpio90",
1051 };
1052 static const char * const blsp1_spi_groups[] = {
1053 "gpio90",
1054 };
1055 static const char * const tgu_ch0_groups[] = {
1056 "gpio90",
1057 };
1058 static const char * const qdss_cti1_b_groups[] = {
1059 "gpio90", "gpio91",
1060 };
1061 static const char * const sdc4_cmd_groups[] = {
1062 "gpio91",
1063 };
1064 static const char * const tgu_ch1_groups[] = {
1065 "gpio91",
1066 };
1067 static const char * const tsif1_groups[] = {
1068 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
1069 };
1070 static const char * const sdc43_groups[] = {
1071 "gpio92",
1072 };
1073 static const char * const vfr_1_groups[] = {
1074 "gpio92",
1075 };
1076 static const char * const sdc4_clk_groups[] = {
1077 "gpio93",
1078 };
1079 static const char * const sdc42_groups[] = {
1080 "gpio94",
1081 };
1082 static const char * const sd_card_groups[] = {
1083 "gpio95",
1084 };
1085 static const char * const sdc41_groups[] = {
1086 "gpio95",
1087 };
1088 static const char * const sdc40_groups[] = {
1089 "gpio96",
1090 };
1091 static const char * const mdp_vsync_b_groups[] = {
1092 "gpio97", "gpio98",
1093 };
1094 static const char * const ldo_en_groups[] = {
1095 "gpio97",
1096 };
1097 static const char * const ldo_update_groups[] = {
1098 "gpio98",
1099 };
1100 static const char * const blsp_uart8_groups[] = {
1101 "gpio100", "gpio101",
1102 };
1103 static const char * const blsp11_i2c_groups[] = {
1104 "gpio102", "gpio103",
1105 };
1106 static const char * const prng_rosc_groups[] = {
1107 "gpio102",
1108 };
1109 static const char * const uim2_data_groups[] = {
1110 "gpio105",
1111 };
1112 static const char * const uim2_clk_groups[] = {
1113 "gpio106",
1114 };
1115 static const char * const uim2_reset_groups[] = {
1116 "gpio107",
1117 };
1118 static const char * const uim2_present_groups[] = {
1119 "gpio108",
1120 };
1121 static const char * const uim1_data_groups[] = {
1122 "gpio109",
1123 };
1124 static const char * const uim1_clk_groups[] = {
1125 "gpio110",
1126 };
1127 static const char * const uim1_reset_groups[] = {
1128 "gpio111",
1129 };
1130 static const char * const uim1_present_groups[] = {
1131 "gpio112",
1132 };
1133 static const char * const uim_batt_groups[] = {
1134 "gpio113",
1135 };
1136 static const char * const nav_dr_groups[] = {
1137 "gpio115",
1138 };
1139 static const char * const atest_char_groups[] = {
1140 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
1141 };
1142 static const char * const adsp_ext_groups[] = {
1143 "gpio118",
1144 };
1145 static const char * const modem_tsync_groups[] = {
1146 "gpio128",
1147 };
1148 static const char * const nav_pps_groups[] = {
1149 "gpio128",
1150 };
1151 static const char * const qlink_request_groups[] = {
1152 "gpio130",
1153 };
1154 static const char * const qlink_enable_groups[] = {
1155 "gpio131",
1156 };
1157 static const char * const pa_indicator_groups[] = {
1158 "gpio135",
1159 };
1160 static const char * const ssbi1_groups[] = {
1161 "gpio142",
1162 };
1163 static const char * const isense_dbg_groups[] = {
1164 "gpio143",
1165 };
1166 static const char * const mss_lte_groups[] = {
1167 "gpio144", "gpio145",
1168 };
1169
1170 static const struct msm_function msm8998_functions[] = {
1171 FUNCTION(gpio),
1172 FUNCTION(adsp_ext),
1173 FUNCTION(agera_pll),
1174 FUNCTION(atest_char),
1175 FUNCTION(atest_gpsadc0),
1176 FUNCTION(atest_gpsadc1),
1177 FUNCTION(atest_tsens),
1178 FUNCTION(atest_tsens2),
1179 FUNCTION(atest_usb1),
1180 FUNCTION(atest_usb10),
1181 FUNCTION(atest_usb11),
1182 FUNCTION(atest_usb12),
1183 FUNCTION(atest_usb13),
1184 FUNCTION(audio_ref),
1185 FUNCTION(bimc_dte0),
1186 FUNCTION(bimc_dte1),
1187 FUNCTION(blsp10_spi),
1188 FUNCTION(blsp10_spi_a),
1189 FUNCTION(blsp10_spi_b),
1190 FUNCTION(blsp11_i2c),
1191 FUNCTION(blsp1_spi),
1192 FUNCTION(blsp1_spi_a),
1193 FUNCTION(blsp1_spi_b),
1194 FUNCTION(blsp2_spi),
1195 FUNCTION(blsp9_spi),
1196 FUNCTION(blsp_i2c1),
1197 FUNCTION(blsp_i2c2),
1198 FUNCTION(blsp_i2c3),
1199 FUNCTION(blsp_i2c4),
1200 FUNCTION(blsp_i2c5),
1201 FUNCTION(blsp_i2c6),
1202 FUNCTION(blsp_i2c7),
1203 FUNCTION(blsp_i2c8),
1204 FUNCTION(blsp_i2c9),
1205 FUNCTION(blsp_i2c10),
1206 FUNCTION(blsp_i2c11),
1207 FUNCTION(blsp_i2c12),
1208 FUNCTION(blsp_spi1),
1209 FUNCTION(blsp_spi2),
1210 FUNCTION(blsp_spi3),
1211 FUNCTION(blsp_spi4),
1212 FUNCTION(blsp_spi5),
1213 FUNCTION(blsp_spi6),
1214 FUNCTION(blsp_spi7),
1215 FUNCTION(blsp_spi8),
1216 FUNCTION(blsp_spi9),
1217 FUNCTION(blsp_spi10),
1218 FUNCTION(blsp_spi11),
1219 FUNCTION(blsp_spi12),
1220 FUNCTION(blsp_uart1_a),
1221 FUNCTION(blsp_uart1_b),
1222 FUNCTION(blsp_uart2_a),
1223 FUNCTION(blsp_uart2_b),
1224 FUNCTION(blsp_uart3_a),
1225 FUNCTION(blsp_uart3_b),
1226 FUNCTION(blsp_uart7_a),
1227 FUNCTION(blsp_uart7_b),
1228 FUNCTION(blsp_uart8),
1229 FUNCTION(blsp_uart8_a),
1230 FUNCTION(blsp_uart8_b),
1231 FUNCTION(blsp_uart9_a),
1232 FUNCTION(blsp_uart9_b),
1233 FUNCTION(blsp_uim1_a),
1234 FUNCTION(blsp_uim1_b),
1235 FUNCTION(blsp_uim2_a),
1236 FUNCTION(blsp_uim2_b),
1237 FUNCTION(blsp_uim3_a),
1238 FUNCTION(blsp_uim3_b),
1239 FUNCTION(blsp_uim7_a),
1240 FUNCTION(blsp_uim7_b),
1241 FUNCTION(blsp_uim8_a),
1242 FUNCTION(blsp_uim8_b),
1243 FUNCTION(blsp_uim9_a),
1244 FUNCTION(blsp_uim9_b),
1245 FUNCTION(bt_reset),
1246 FUNCTION(btfm_slimbus),
1247 FUNCTION(cam_mclk),
1248 FUNCTION(cci_async),
1249 FUNCTION(cci_i2c),
1250 FUNCTION(cci_timer0),
1251 FUNCTION(cci_timer1),
1252 FUNCTION(cci_timer2),
1253 FUNCTION(cci_timer3),
1254 FUNCTION(cci_timer4),
1255 FUNCTION(cri_trng),
1256 FUNCTION(cri_trng0),
1257 FUNCTION(cri_trng1),
1258 FUNCTION(dbg_out),
1259 FUNCTION(ddr_bist),
1260 FUNCTION(edp_hot),
1261 FUNCTION(edp_lcd),
1262 FUNCTION(gcc_gp1_a),
1263 FUNCTION(gcc_gp1_b),
1264 FUNCTION(gcc_gp2_a),
1265 FUNCTION(gcc_gp2_b),
1266 FUNCTION(gcc_gp3_a),
1267 FUNCTION(gcc_gp3_b),
1268 FUNCTION(hdmi_cec),
1269 FUNCTION(hdmi_ddc),
1270 FUNCTION(hdmi_hot),
1271 FUNCTION(hdmi_rcv),
1272 FUNCTION(isense_dbg),
1273 FUNCTION(jitter_bist),
1274 FUNCTION(ldo_en),
1275 FUNCTION(ldo_update),
1276 FUNCTION(lpass_slimbus),
1277 FUNCTION(m_voc),
1278 FUNCTION(mdp_vsync),
1279 FUNCTION(mdp_vsync0),
1280 FUNCTION(mdp_vsync1),
1281 FUNCTION(mdp_vsync2),
1282 FUNCTION(mdp_vsync3),
1283 FUNCTION(mdp_vsync_a),
1284 FUNCTION(mdp_vsync_b),
1285 FUNCTION(modem_tsync),
1286 FUNCTION(mss_lte),
1287 FUNCTION(nav_dr),
1288 FUNCTION(nav_pps),
1289 FUNCTION(pa_indicator),
1290 FUNCTION(pci_e0),
1291 FUNCTION(phase_flag),
1292 FUNCTION(pll_bypassnl),
1293 FUNCTION(pll_reset),
1294 FUNCTION(pri_mi2s),
1295 FUNCTION(pri_mi2s_ws),
1296 FUNCTION(prng_rosc),
1297 FUNCTION(pwr_crypto),
1298 FUNCTION(pwr_modem),
1299 FUNCTION(pwr_nav),
1300 FUNCTION(qdss_cti0_a),
1301 FUNCTION(qdss_cti0_b),
1302 FUNCTION(qdss_cti1_a),
1303 FUNCTION(qdss_cti1_b),
1304 FUNCTION(qdss),
1305 FUNCTION(qlink_enable),
1306 FUNCTION(qlink_request),
1307 FUNCTION(qua_mi2s),
1308 FUNCTION(sd_card),
1309 FUNCTION(sd_write),
1310 FUNCTION(sdc40),
1311 FUNCTION(sdc41),
1312 FUNCTION(sdc42),
1313 FUNCTION(sdc43),
1314 FUNCTION(sdc4_clk),
1315 FUNCTION(sdc4_cmd),
1316 FUNCTION(sec_mi2s),
1317 FUNCTION(sp_cmu),
1318 FUNCTION(spkr_i2s),
1319 FUNCTION(ssbi1),
1320 FUNCTION(ssc_irq),
1321 FUNCTION(ter_mi2s),
1322 FUNCTION(tgu_ch0),
1323 FUNCTION(tgu_ch1),
1324 FUNCTION(tsense_pwm1),
1325 FUNCTION(tsense_pwm2),
1326 FUNCTION(tsif0),
1327 FUNCTION(tsif1),
1328 FUNCTION(uim1_clk),
1329 FUNCTION(uim1_data),
1330 FUNCTION(uim1_present),
1331 FUNCTION(uim1_reset),
1332 FUNCTION(uim2_clk),
1333 FUNCTION(uim2_data),
1334 FUNCTION(uim2_present),
1335 FUNCTION(uim2_reset),
1336 FUNCTION(uim_batt),
1337 FUNCTION(usb_phy),
1338 FUNCTION(vfr_1),
1339 FUNCTION(vsense_clkout),
1340 FUNCTION(vsense_data0),
1341 FUNCTION(vsense_data1),
1342 FUNCTION(vsense_mode),
1343 FUNCTION(wlan1_adc0),
1344 FUNCTION(wlan1_adc1),
1345 FUNCTION(wlan2_adc0),
1346 FUNCTION(wlan2_adc1),
1347 };
1348
1349 static const struct msm_pingroup msm8998_groups[] = {
1350 PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _),
1351 PINGROUP(1, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _),
1352 PINGROUP(2, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _),
1353 PINGROUP(3, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _),
1354 PINGROUP(4, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _),
1355 PINGROUP(5, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _),
1356 PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, _, _, _, _, _, _),
1357 PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, _, atest_tsens2, atest_usb1, _, _),
1358 PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, _, ddr_bist, _, wlan1_adc1, atest_usb13, bimc_dte1),
1359 PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif0, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
1360 PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1),
1361 PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10),
1362 PINGROUP(12, EAST, mdp_vsync, m_voc, _, _, _, _, _, _, _),
1363 PINGROUP(13, EAST, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),
1364 PINGROUP(14, EAST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
1365 PINGROUP(15, EAST, cam_mclk, qdss, _, _, _, _, _, _, _),
1366 PINGROUP(16, EAST, cam_mclk, qdss, _, _, _, _, _, _, _),
1367 PINGROUP(17, EAST, cci_i2c, qdss, _, _, _, _, _, _, _),
1368 PINGROUP(18, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _),
1369 PINGROUP(19, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _),
1370 PINGROUP(20, EAST, cci_i2c, qdss, _, _, _, _, _, _, _),
1371 PINGROUP(21, EAST, cci_timer0, _, qdss, vsense_data0, _, _, _, _, _),
1372 PINGROUP(22, EAST, cci_timer1, _, qdss, vsense_data1, _, _, _, _, _),
1373 PINGROUP(23, EAST, cci_timer2, blsp1_spi_b, qdss, vsense_mode, _, _, _, _, _),
1374 PINGROUP(24, EAST, cci_timer3, cci_async, blsp1_spi_a, _, qdss, vsense_clkout, _, _, _),
1375 PINGROUP(25, EAST, cci_timer4, cci_async, blsp2_spi, _, qdss, _, _, _, _),
1376 PINGROUP(26, EAST, cci_async, qdss, _, _, _, _, _, _, _),
1377 PINGROUP(27, EAST, blsp1_spi_a, qdss, _, _, _, _, _, _, _),
1378 PINGROUP(28, EAST, blsp1_spi_b, qdss, _, _, _, _, _, _, _),
1379 PINGROUP(29, EAST, blsp2_spi, _, qdss, _, _, _, _, _, _),
1380 PINGROUP(30, EAST, hdmi_rcv, blsp2_spi, qdss, _, _, _, _, _, _),
1381 PINGROUP(31, EAST, hdmi_cec, blsp_spi2, blsp_uart2_a, blsp_uim2_a, pwr_modem, _, _, _, _),
1382 PINGROUP(32, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_nav, _, _, _, _),
1383 PINGROUP(33, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_crypto, _, _, _, _),
1384 PINGROUP(34, EAST, hdmi_hot, edp_hot, blsp_spi2, blsp_uart2_a, blsp_uim2_a, _, _, _, _),
1385 PINGROUP(35, NORTH, pci_e0, jitter_bist, _, _, _, _, _, _, _),
1386 PINGROUP(36, NORTH, pci_e0, agera_pll, _, atest_tsens, _, _, _, _, _),
1387 PINGROUP(37, NORTH, agera_pll, _, _, _, _, _, _, _, _),
1388 PINGROUP(38, WEST, usb_phy, _, _, _, _, _, _, _, _),
1389 PINGROUP(39, WEST, lpass_slimbus, _, _, _, _, _, _, _, _),
1390 PINGROUP(40, EAST, sd_write, tsif0, _, _, _, _, _, _, _),
1391 PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
1392 PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
1393 PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
1394 PINGROUP(44, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
1395 PINGROUP(45, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _),
1396 PINGROUP(46, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _),
1397 PINGROUP(47, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _),
1398 PINGROUP(48, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _),
1399 PINGROUP(49, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _),
1400 PINGROUP(50, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _),
1401 PINGROUP(51, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _),
1402 PINGROUP(52, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _),
1403 PINGROUP(53, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _),
1404 PINGROUP(54, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _),
1405 PINGROUP(55, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _),
1406 PINGROUP(56, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _),
1407 PINGROUP(57, WEST, qua_mi2s, blsp10_spi, gcc_gp1_a, _, _, _, _, _, _),
1408 PINGROUP(58, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp2_a, _, qdss_cti1_a, _, _),
1409 PINGROUP(59, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp3_a, _, qdss_cti1_a, _, _),
1410 PINGROUP(60, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng0, _, _, _, _),
1411 PINGROUP(61, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng1, _, _, _, _),
1412 PINGROUP(62, WEST, qua_mi2s, cri_trng, _, _, _, _, _, _, _),
1413 PINGROUP(63, WEST, qua_mi2s, _, _, _, _, _, _, _, _),
1414 PINGROUP(64, WEST, pri_mi2s, sp_cmu, _, _, _, _, _, _, _),
1415 PINGROUP(65, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _),
1416 PINGROUP(66, WEST, pri_mi2s_ws, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _),
1417 PINGROUP(67, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _),
1418 PINGROUP(68, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _),
1419 PINGROUP(69, WEST, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
1420 PINGROUP(70, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _),
1421 PINGROUP(71, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, tsense_pwm1, tsense_pwm2, _, _, _, _),
1422 PINGROUP(72, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _),
1423 PINGROUP(73, WEST, btfm_slimbus, phase_flag, _, _, _, _, _, _, _),
1424 PINGROUP(74, WEST, btfm_slimbus, ter_mi2s, phase_flag, _, _, _, _, _, _),
1425 PINGROUP(75, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
1426 PINGROUP(76, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
1427 PINGROUP(77, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
1428 PINGROUP(78, WEST, ter_mi2s, gcc_gp1_b, _, _, _, _, _, _, _),
1429 PINGROUP(79, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _),
1430 PINGROUP(80, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _),
1431 PINGROUP(81, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp2_b, _, _, _, _),
1432 PINGROUP(82, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp3_b, _, _, _, _),
1433 PINGROUP(83, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _),
1434 PINGROUP(84, WEST, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _, _),
1435 PINGROUP(85, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
1436 PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
1437 PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
1438 PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
1439 PINGROUP(89, EAST, tsif0, phase_flag, _, _, _, _, _, _, _),
1440 PINGROUP(90, EAST, tsif0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
1441 PINGROUP(91, EAST, tsif0, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
1442 PINGROUP(92, EAST, tsif1, sdc43, vfr_1, phase_flag, _, _, _, _, _),
1443 PINGROUP(93, EAST, tsif1, sdc4_clk, _, qdss, _, _, _, _, _),
1444 PINGROUP(94, EAST, tsif1, sdc42, _, _, _, _, _, _, _),
1445 PINGROUP(95, EAST, tsif1, sdc41, _, _, _, _, _, _, _),
1446 PINGROUP(96, EAST, tsif1, sdc40, phase_flag, _, _, _, _, _, _),
1447 PINGROUP(97, WEST, _, mdp_vsync_b, ldo_en, _, _, _, _, _, _),
1448 PINGROUP(98, WEST, _, mdp_vsync_b, ldo_update, _, _, _, _, _, _),
1449 PINGROUP(99, WEST, _, _, _, _, _, _, _, _, _),
1450 PINGROUP(100, WEST, _, _, blsp_uart8, _, _, _, _, _, _),
1451 PINGROUP(101, WEST, _, blsp_uart8, _, _, _, _, _, _, _),
1452 PINGROUP(102, WEST, _, blsp11_i2c, prng_rosc, _, _, _, _, _, _),
1453 PINGROUP(103, WEST, _, blsp11_i2c, phase_flag, _, _, _, _, _, _),
1454 PINGROUP(104, WEST, _, _, _, _, _, _, _, _, _),
1455 PINGROUP(105, NORTH, uim2_data, _, _, _, _, _, _, _, _),
1456 PINGROUP(106, NORTH, uim2_clk, _, _, _, _, _, _, _, _),
1457 PINGROUP(107, NORTH, uim2_reset, _, _, _, _, _, _, _, _),
1458 PINGROUP(108, NORTH, uim2_present, _, _, _, _, _, _, _, _),
1459 PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _),
1460 PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _),
1461 PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _),
1462 PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _),
1463 PINGROUP(113, NORTH, uim_batt, _, _, _, _, _, _, _, _),
1464 PINGROUP(114, WEST, _, _, phase_flag, _, _, _, _, _, _),
1465 PINGROUP(115, WEST, _, nav_dr, phase_flag, _, _, _, _, _, _),
1466 PINGROUP(116, WEST, phase_flag, _, _, _, _, _, _, _, _),
1467 PINGROUP(117, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1468 PINGROUP(118, EAST, adsp_ext, phase_flag, qdss, atest_char, _, _, _, _, _),
1469 PINGROUP(119, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1470 PINGROUP(120, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1471 PINGROUP(121, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1472 PINGROUP(122, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
1473 PINGROUP(123, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
1474 PINGROUP(124, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
1475 PINGROUP(125, EAST, phase_flag, _, _, _, _, _, _, _, _),
1476 PINGROUP(126, EAST, phase_flag, _, _, _, _, _, _, _, _),
1477 PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _),
1478 PINGROUP(128, WEST, modem_tsync, nav_pps, phase_flag, _, _, _, _, _, _),
1479 PINGROUP(129, WEST, phase_flag, _, _, _, _, _, _, _, _),
1480 PINGROUP(130, NORTH, qlink_request, phase_flag, _, _, _, _, _, _, _),
1481 PINGROUP(131, NORTH, qlink_enable, phase_flag, _, _, _, _, _, _, _),
1482 PINGROUP(132, WEST, _, phase_flag, _, _, _, _, _, _, _),
1483 PINGROUP(133, WEST, phase_flag, _, _, _, _, _, _, _, _),
1484 PINGROUP(134, WEST, phase_flag, _, _, _, _, _, _, _, _),
1485 PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _),
1486 PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _),
1487 PINGROUP(137, WEST, _, _, _, _, _, _, _, _, _),
1488 PINGROUP(138, WEST, _, _, _, _, _, _, _, _, _),
1489 PINGROUP(139, WEST, _, _, _, _, _, _, _, _, _),
1490 PINGROUP(140, WEST, _, _, _, _, _, _, _, _, _),
1491 PINGROUP(141, WEST, _, _, _, _, _, _, _, _, _),
1492 PINGROUP(142, WEST, _, ssbi1, _, _, _, _, _, _, _),
1493 PINGROUP(143, WEST, isense_dbg, _, _, _, _, _, _, _, _),
1494 PINGROUP(144, WEST, mss_lte, _, _, _, _, _, _, _, _),
1495 PINGROUP(145, WEST, mss_lte, _, _, _, _, _, _, _, _),
1496 PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
1497 PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
1498 PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
1499 PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
1500 SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6),
1501 SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3),
1502 SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0),
1503 UFS_RESET(ufs_reset, 0x19d000),
1504 };
1505
1506 static const struct msm_pinctrl_soc_data msm8998_pinctrl = {
1507 .pins = msm8998_pins,
1508 .npins = ARRAY_SIZE(msm8998_pins),
1509 .functions = msm8998_functions,
1510 .nfunctions = ARRAY_SIZE(msm8998_functions),
1511 .groups = msm8998_groups,
1512 .ngroups = ARRAY_SIZE(msm8998_groups),
1513 .ngpios = 150,
1514 };
1515
1516 static int msm8998_pinctrl_probe(struct platform_device *pdev)
1517 {
1518 return msm_pinctrl_probe(pdev, &msm8998_pinctrl);
1519 }
1520
1521 static const struct of_device_id msm8998_pinctrl_of_match[] = {
1522 { .compatible = "qcom,msm8998-pinctrl", },
1523 { },
1524 };
1525
1526 static struct platform_driver msm8998_pinctrl_driver = {
1527 .driver = {
1528 .name = "msm8998-pinctrl",
1529 .of_match_table = msm8998_pinctrl_of_match,
1530 },
1531 .probe = msm8998_pinctrl_probe,
1532 .remove = msm_pinctrl_remove,
1533 };
1534
1535 static int __init msm8998_pinctrl_init(void)
1536 {
1537 return platform_driver_register(&msm8998_pinctrl_driver);
1538 }
1539 arch_initcall(msm8998_pinctrl_init);
1540
1541 static void __exit msm8998_pinctrl_exit(void)
1542 {
1543 platform_driver_unregister(&msm8998_pinctrl_driver);
1544 }
1545 module_exit(msm8998_pinctrl_exit);
1546
1547 MODULE_DESCRIPTION("QTI msm8998 pinctrl driver");
1548 MODULE_LICENSE("GPL v2");
1549 MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match);
Linux with added FPC-III support