drivers/spi/spi-geni-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4 #include <linux/clk.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/io.h>
   7 #include <linux/log2.h>
   8 #include <linux/module.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/qcom-geni-se.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/spinlock.h>
  14
  15 /* SPI SE specific registers and respective register fields */
  16 #define SE_SPI_CPHA             0x224
  17 #define CPHA                    BIT(0)
  18
  19 #define SE_SPI_LOOPBACK         0x22c
  20 #define LOOPBACK_ENABLE         0x1
  21 #define NORMAL_MODE             0x0
  22 #define LOOPBACK_MSK            GENMASK(1, 0)
  23
  24 #define SE_SPI_CPOL             0x230
  25 #define CPOL                    BIT(2)
  26
  27 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c
  28 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
  29
  30 #define SE_SPI_DEMUX_SEL        0x250
  31 #define CS_DEMUX_OUTPUT_SEL     GENMASK(3, 0)
  32
  33 #define SE_SPI_TRANS_CFG        0x25c
  34 #define CS_TOGGLE               BIT(0)
  35
  36 #define SE_SPI_WORD_LEN         0x268
  37 #define WORD_LEN_MSK            GENMASK(9, 0)
  38 #define MIN_WORD_LEN            4
  39
  40 #define SE_SPI_TX_TRANS_LEN     0x26c
  41 #define SE_SPI_RX_TRANS_LEN     0x270
  42 #define TRANS_LEN_MSK           GENMASK(23, 0)
  43
  44 #define SE_SPI_PRE_POST_CMD_DLY 0x274
  45
  46 #define SE_SPI_DELAY_COUNTERS   0x278
  47 #define SPI_INTER_WORDS_DELAY_MSK       GENMASK(9, 0)
  48 #define SPI_CS_CLK_DELAY_MSK            GENMASK(19, 10)
  49 #define SPI_CS_CLK_DELAY_SHFT           10
  50
  51 /* M_CMD OP codes for SPI */
  52 #define SPI_TX_ONLY             1
  53 #define SPI_RX_ONLY             2
  54 #define SPI_FULL_DUPLEX         3
  55 #define SPI_TX_RX               7
  56 #define SPI_CS_ASSERT           8
  57 #define SPI_CS_DEASSERT         9
  58 #define SPI_SCK_ONLY            10
  59 /* M_CMD params for SPI */
  60 #define SPI_PRE_CMD_DELAY       BIT(0)
  61 #define TIMESTAMP_BEFORE        BIT(1)
  62 #define FRAGMENTATION           BIT(2)
  63 #define TIMESTAMP_AFTER         BIT(3)
  64 #define POST_CMD_DELAY          BIT(4)
  65
  66 enum spi_m_cmd_opcode {
  67         CMD_NONE,
  68         CMD_XFER,
  69         CMD_CS,
  70         CMD_CANCEL,
  71 };
  72
  73 struct spi_geni_master {
  74         struct geni_se se;
  75         struct device *dev;
  76         u32 tx_fifo_depth;
  77         u32 fifo_width_bits;
  78         u32 tx_wm;
  79         unsigned long cur_speed_hz;
  80         unsigned int cur_bits_per_word;
  81         unsigned int tx_rem_bytes;
  82         unsigned int rx_rem_bytes;
  83         const struct spi_transfer *cur_xfer;
  84         struct completion xfer_done;
  85         unsigned int oversampling;
  86         spinlock_t lock;
  87         enum spi_m_cmd_opcode cur_mcmd;
  88         int irq;
  89 };
  90
  91 static int get_spi_clk_cfg(unsigned int speed_hz,
  92                         struct spi_geni_master *mas,
  93                         unsigned int *clk_idx,
  94                         unsigned int *clk_div)
  95 {
  96         unsigned long sclk_freq;
  97         unsigned int actual_hz;
  98         struct geni_se *se = &mas->se;
  99         int ret;
 100
 101         ret = geni_se_clk_freq_match(&mas->se,
 102                                 speed_hz * mas->oversampling,
 103                                 clk_idx, &sclk_freq, false);
 104         if (ret) {
 105                 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
 106                                                         ret, speed_hz);
 107                 return ret;
 108         }
 109
 110         *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
 111         actual_hz = sclk_freq / (mas->oversampling * *clk_div);
 112
 113         dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
 114                                 actual_hz, sclk_freq, *clk_idx, *clk_div);
 115         ret = clk_set_rate(se->clk, sclk_freq);
 116         if (ret)
 117                 dev_err(mas->dev, "clk_set_rate failed %d\n", ret);
 118         return ret;
 119 }
 120
 121 static void handle_fifo_timeout(struct spi_master *spi,
 122                                 struct spi_message *msg)
 123 {
 124         struct spi_geni_master *mas = spi_master_get_devdata(spi);
 125         unsigned long time_left, flags;
 126         struct geni_se *se = &mas->se;
 127
 128         spin_lock_irqsave(&mas->lock, flags);
 129         reinit_completion(&mas->xfer_done);
 130         mas->cur_mcmd = CMD_CANCEL;
 131         geni_se_cancel_m_cmd(se);
 132         writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
 133         spin_unlock_irqrestore(&mas->lock, flags);
 134         time_left = wait_for_completion_timeout(&mas->xfer_done, HZ);
 135         if (time_left)
 136                 return;
 137
 138         spin_lock_irqsave(&mas->lock, flags);
 139         reinit_completion(&mas->xfer_done);
 140         geni_se_abort_m_cmd(se);
 141         spin_unlock_irqrestore(&mas->lock, flags);
 142         time_left = wait_for_completion_timeout(&mas->xfer_done, HZ);
 143         if (!time_left)
 144                 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
 145 }
 146
 147 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
 148 {
 149         struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
 150         struct spi_master *spi = dev_get_drvdata(mas->dev);
 151         struct geni_se *se = &mas->se;
 152         unsigned long time_left;
 153
 154         reinit_completion(&mas->xfer_done);
 155         pm_runtime_get_sync(mas->dev);
 156         if (!(slv->mode & SPI_CS_HIGH))
 157                 set_flag = !set_flag;
 158
 159         mas->cur_mcmd = CMD_CS;
 160         if (set_flag)
 161                 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
 162         else
 163                 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
 164
 165         time_left = wait_for_completion_timeout(&mas->xfer_done, HZ);
 166         if (!time_left)
 167                 handle_fifo_timeout(spi, NULL);
 168
 169         pm_runtime_put(mas->dev);
 170 }
 171
 172 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
 173                                         unsigned int bits_per_word)
 174 {
 175         unsigned int pack_words;
 176         bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
 177         struct geni_se *se = &mas->se;
 178         u32 word_len;
 179
 180         word_len = readl(se->base + SE_SPI_WORD_LEN);
 181
 182         /*
 183          * If bits_per_word isn't a byte aligned value, set the packing to be
 184          * 1 SPI word per FIFO word.
 185          */
 186         if (!(mas->fifo_width_bits % bits_per_word))
 187                 pack_words = mas->fifo_width_bits / bits_per_word;
 188         else
 189                 pack_words = 1;
 190         word_len &= ~WORD_LEN_MSK;
 191         word_len |= ((bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK);
 192         geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
 193                                                                 true, true);
 194         writel(word_len, se->base + SE_SPI_WORD_LEN);
 195 }
 196
 197 static int setup_fifo_params(struct spi_device *spi_slv,
 198                                         struct spi_master *spi)
 199 {
 200         struct spi_geni_master *mas = spi_master_get_devdata(spi);
 201         struct geni_se *se = &mas->se;
 202         u32 loopback_cfg, cpol, cpha, demux_output_inv;
 203         u32 demux_sel, clk_sel, m_clk_cfg, idx, div;
 204         int ret;
 205
 206         loopback_cfg = readl(se->base + SE_SPI_LOOPBACK);
 207         cpol = readl(se->base + SE_SPI_CPOL);
 208         cpha = readl(se->base + SE_SPI_CPHA);
 209         demux_output_inv = 0;
 210         loopback_cfg &= ~LOOPBACK_MSK;
 211         cpol &= ~CPOL;
 212         cpha &= ~CPHA;
 213
 214         if (spi_slv->mode & SPI_LOOP)
 215                 loopback_cfg |= LOOPBACK_ENABLE;
 216
 217         if (spi_slv->mode & SPI_CPOL)
 218                 cpol |= CPOL;
 219
 220         if (spi_slv->mode & SPI_CPHA)
 221                 cpha |= CPHA;
 222
 223         if (spi_slv->mode & SPI_CS_HIGH)
 224                 demux_output_inv = BIT(spi_slv->chip_select);
 225
 226         demux_sel = spi_slv->chip_select;
 227         mas->cur_speed_hz = spi_slv->max_speed_hz;
 228         mas->cur_bits_per_word = spi_slv->bits_per_word;
 229
 230         ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, &idx, &div);
 231         if (ret) {
 232                 dev_err(mas->dev, "Err setting clks ret(%d) for %ld\n",
 233                                                         ret, mas->cur_speed_hz);
 234                 return ret;
 235         }
 236
 237         clk_sel = idx & CLK_SEL_MSK;
 238         m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
 239         spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
 240         writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
 241         writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
 242         writel(cpha, se->base + SE_SPI_CPHA);
 243         writel(cpol, se->base + SE_SPI_CPOL);
 244         writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
 245         writel(clk_sel, se->base + SE_GENI_CLK_SEL);
 246         writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
 247         return 0;
 248 }
 249
 250 static int spi_geni_prepare_message(struct spi_master *spi,
 251                                         struct spi_message *spi_msg)
 252 {
 253         int ret;
 254         struct spi_geni_master *mas = spi_master_get_devdata(spi);
 255         struct geni_se *se = &mas->se;
 256
 257         geni_se_select_mode(se, GENI_SE_FIFO);
 258         ret = setup_fifo_params(spi_msg->spi, spi);
 259         if (ret)
 260                 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
 261         return ret;
 262 }
 263
 264 static int spi_geni_init(struct spi_geni_master *mas)
 265 {
 266         struct geni_se *se = &mas->se;
 267         unsigned int proto, major, minor, ver;
 268
 269         pm_runtime_get_sync(mas->dev);
 270
 271         proto = geni_se_read_proto(se);
 272         if (proto != GENI_SE_SPI) {
 273                 dev_err(mas->dev, "Invalid proto %d\n", proto);
 274                 pm_runtime_put(mas->dev);
 275                 return -ENXIO;
 276         }
 277         mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
 278
 279         /* Width of Tx and Rx FIFO is same */
 280         mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
 281
 282         /*
 283          * Hardware programming guide suggests to configure
 284          * RX FIFO RFR level to fifo_depth-2.
 285          */
 286         geni_se_init(se, 0x0, mas->tx_fifo_depth - 2);
 287         /* Transmit an entire FIFO worth of data per IRQ */
 288         mas->tx_wm = 1;
 289         ver = geni_se_get_qup_hw_version(se);
 290         major = GENI_SE_VERSION_MAJOR(ver);
 291         minor = GENI_SE_VERSION_MINOR(ver);
 292
 293         if (major == 1 && minor == 0)
 294                 mas->oversampling = 2;
 295         else
 296                 mas->oversampling = 1;
 297
 298         pm_runtime_put(mas->dev);
 299         return 0;
 300 }
 301
 302 static void setup_fifo_xfer(struct spi_transfer *xfer,
 303                                 struct spi_geni_master *mas,
 304                                 u16 mode, struct spi_master *spi)
 305 {
 306         u32 m_cmd = 0;
 307         u32 spi_tx_cfg, len;
 308         struct geni_se *se = &mas->se;
 309
 310         spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
 311         if (xfer->bits_per_word != mas->cur_bits_per_word) {
 312                 spi_setup_word_len(mas, mode, xfer->bits_per_word);
 313                 mas->cur_bits_per_word = xfer->bits_per_word;
 314         }
 315
 316         /* Speed and bits per word can be overridden per transfer */
 317         if (xfer->speed_hz != mas->cur_speed_hz) {
 318                 int ret;
 319                 u32 clk_sel, m_clk_cfg;
 320                 unsigned int idx, div;
 321
 322                 ret = get_spi_clk_cfg(xfer->speed_hz, mas, &idx, &div);
 323                 if (ret) {
 324                         dev_err(mas->dev, "Err setting clks:%d\n", ret);
 325                         return;
 326                 }
 327                 /*
 328                  * SPI core clock gets configured with the requested frequency
 329                  * or the frequency closer to the requested frequency.
 330                  * For that reason requested frequency is stored in the
 331                  * cur_speed_hz and referred in the consecutive transfer instead
 332                  * of calling clk_get_rate() API.
 333                  */
 334                 mas->cur_speed_hz = xfer->speed_hz;
 335                 clk_sel = idx & CLK_SEL_MSK;
 336                 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
 337                 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
 338                 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
 339         }
 340
 341         mas->tx_rem_bytes = 0;
 342         mas->rx_rem_bytes = 0;
 343         if (xfer->tx_buf && xfer->rx_buf)
 344                 m_cmd = SPI_FULL_DUPLEX;
 345         else if (xfer->tx_buf)
 346                 m_cmd = SPI_TX_ONLY;
 347         else if (xfer->rx_buf)
 348                 m_cmd = SPI_RX_ONLY;
 349
 350         spi_tx_cfg &= ~CS_TOGGLE;
 351
 352         if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
 353                 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
 354         else
 355                 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
 356         len &= TRANS_LEN_MSK;
 357
 358         mas->cur_xfer = xfer;
 359         if (m_cmd & SPI_TX_ONLY) {
 360                 mas->tx_rem_bytes = xfer->len;
 361                 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
 362         }
 363
 364         if (m_cmd & SPI_RX_ONLY) {
 365                 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
 366                 mas->rx_rem_bytes = xfer->len;
 367         }
 368         writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
 369         mas->cur_mcmd = CMD_XFER;
 370         geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
 371
 372         /*
 373          * TX_WATERMARK_REG should be set after SPI configuration and
 374          * setting up GENI SE engine, as driver starts data transfer
 375          * for the watermark interrupt.
 376          */
 377         if (m_cmd & SPI_TX_ONLY)
 378                 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
 379 }
 380
 381 static int spi_geni_transfer_one(struct spi_master *spi,
 382                                 struct spi_device *slv,
 383                                 struct spi_transfer *xfer)
 384 {
 385         struct spi_geni_master *mas = spi_master_get_devdata(spi);
 386
 387         /* Terminate and return success for 0 byte length transfer */
 388         if (!xfer->len)
 389                 return 0;
 390
 391         setup_fifo_xfer(xfer, mas, slv->mode, spi);
 392         return 1;
 393 }
 394
 395 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
 396 {
 397         /*
 398          * Calculate how many bytes we'll put in each FIFO word.  If the
 399          * transfer words don't pack cleanly into a FIFO word we'll just put
 400          * one transfer word in each FIFO word.  If they do pack we'll pack 'em.
 401          */
 402         if (mas->fifo_width_bits % mas->cur_bits_per_word)
 403                 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
 404                                                        BITS_PER_BYTE));
 405
 406         return mas->fifo_width_bits / BITS_PER_BYTE;
 407 }
 408
 409 static void geni_spi_handle_tx(struct spi_geni_master *mas)
 410 {
 411         struct geni_se *se = &mas->se;
 412         unsigned int max_bytes;
 413         const u8 *tx_buf;
 414         unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
 415         unsigned int i = 0;
 416
 417         max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
 418         if (mas->tx_rem_bytes < max_bytes)
 419                 max_bytes = mas->tx_rem_bytes;
 420
 421         tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
 422         while (i < max_bytes) {
 423                 unsigned int j;
 424                 unsigned int bytes_to_write;
 425                 u32 fifo_word = 0;
 426                 u8 *fifo_byte = (u8 *)&fifo_word;
 427
 428                 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
 429                 for (j = 0; j < bytes_to_write; j++)
 430                         fifo_byte[j] = tx_buf[i++];
 431                 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
 432         }
 433         mas->tx_rem_bytes -= max_bytes;
 434         if (!mas->tx_rem_bytes)
 435                 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
 436 }
 437
 438 static void geni_spi_handle_rx(struct spi_geni_master *mas)
 439 {
 440         struct geni_se *se = &mas->se;
 441         u32 rx_fifo_status;
 442         unsigned int rx_bytes;
 443         unsigned int rx_last_byte_valid;
 444         u8 *rx_buf;
 445         unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
 446         unsigned int i = 0;
 447
 448         rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
 449         rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
 450         if (rx_fifo_status & RX_LAST) {
 451                 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
 452                 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
 453                 if (rx_last_byte_valid && rx_last_byte_valid < 4)
 454                         rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
 455         }
 456         if (mas->rx_rem_bytes < rx_bytes)
 457                 rx_bytes = mas->rx_rem_bytes;
 458
 459         rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
 460         while (i < rx_bytes) {
 461                 u32 fifo_word = 0;
 462                 u8 *fifo_byte = (u8 *)&fifo_word;
 463                 unsigned int bytes_to_read;
 464                 unsigned int j;
 465
 466                 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
 467                 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
 468                 for (j = 0; j < bytes_to_read; j++)
 469                         rx_buf[i++] = fifo_byte[j];
 470         }
 471         mas->rx_rem_bytes -= rx_bytes;
 472 }
 473
 474 static irqreturn_t geni_spi_isr(int irq, void *data)
 475 {
 476         struct spi_master *spi = data;
 477         struct spi_geni_master *mas = spi_master_get_devdata(spi);
 478         struct geni_se *se = &mas->se;
 479         u32 m_irq;
 480         unsigned long flags;
 481
 482         if (mas->cur_mcmd == CMD_NONE)
 483                 return IRQ_NONE;
 484
 485         spin_lock_irqsave(&mas->lock, flags);
 486         m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
 487
 488         if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
 489                 geni_spi_handle_rx(mas);
 490
 491         if (m_irq & M_TX_FIFO_WATERMARK_EN)
 492                 geni_spi_handle_tx(mas);
 493
 494         if (m_irq & M_CMD_DONE_EN) {
 495                 if (mas->cur_mcmd == CMD_XFER)
 496                         spi_finalize_current_transfer(spi);
 497                 else if (mas->cur_mcmd == CMD_CS)
 498                         complete(&mas->xfer_done);
 499                 mas->cur_mcmd = CMD_NONE;
 500                 /*
 501                  * If this happens, then a CMD_DONE came before all the Tx
 502                  * buffer bytes were sent out. This is unusual, log this
 503                  * condition and disable the WM interrupt to prevent the
 504                  * system from stalling due an interrupt storm.
 505                  * If this happens when all Rx bytes haven't been received, log
 506                  * the condition.
 507                  * The only known time this can happen is if bits_per_word != 8
 508                  * and some registers that expect xfer lengths in num spi_words
 509                  * weren't written correctly.
 510                  */
 511                 if (mas->tx_rem_bytes) {
 512                         writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
 513                         dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
 514                                 mas->tx_rem_bytes, mas->cur_bits_per_word);
 515                 }
 516                 if (mas->rx_rem_bytes)
 517                         dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
 518                                 mas->rx_rem_bytes, mas->cur_bits_per_word);
 519         }
 520
 521         if ((m_irq & M_CMD_CANCEL_EN) || (m_irq & M_CMD_ABORT_EN)) {
 522                 mas->cur_mcmd = CMD_NONE;
 523                 complete(&mas->xfer_done);
 524         }
 525
 526         writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
 527         spin_unlock_irqrestore(&mas->lock, flags);
 528         return IRQ_HANDLED;
 529 }
 530
 531 static int spi_geni_probe(struct platform_device *pdev)
 532 {
 533         int ret, irq;
 534         struct spi_master *spi;
 535         struct spi_geni_master *mas;
 536         void __iomem *base;
 537         struct clk *clk;
 538         struct device *dev = &pdev->dev;
 539
 540         irq = platform_get_irq(pdev, 0);
 541         if (irq < 0)
 542                 return irq;
 543
 544         base = devm_platform_ioremap_resource(pdev, 0);
 545         if (IS_ERR(base))
 546                 return PTR_ERR(base);
 547
 548         clk = devm_clk_get(dev, "se");
 549         if (IS_ERR(clk))
 550                 return PTR_ERR(clk);
 551
 552         spi = spi_alloc_master(dev, sizeof(*mas));
 553         if (!spi)
 554                 return -ENOMEM;
 555
 556         platform_set_drvdata(pdev, spi);
 557         mas = spi_master_get_devdata(spi);
 558         mas->irq = irq;
 559         mas->dev = dev;
 560         mas->se.dev = dev;
 561         mas->se.wrapper = dev_get_drvdata(dev->parent);
 562         mas->se.base = base;
 563         mas->se.clk = clk;
 564
 565         spi->bus_num = -1;
 566         spi->dev.of_node = dev->of_node;
 567         spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
 568         spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
 569         spi->num_chipselect = 4;
 570         spi->max_speed_hz = 50000000;
 571         spi->prepare_message = spi_geni_prepare_message;
 572         spi->transfer_one = spi_geni_transfer_one;
 573         spi->auto_runtime_pm = true;
 574         spi->handle_err = handle_fifo_timeout;
 575         spi->set_cs = spi_geni_set_cs;
 576
 577         init_completion(&mas->xfer_done);
 578         spin_lock_init(&mas->lock);
 579         pm_runtime_enable(dev);
 580
 581         ret = spi_geni_init(mas);
 582         if (ret)
 583                 goto spi_geni_probe_runtime_disable;
 584
 585         ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
 586         if (ret)
 587                 goto spi_geni_probe_runtime_disable;
 588
 589         ret = spi_register_master(spi);
 590         if (ret)
 591                 goto spi_geni_probe_free_irq;
 592
 593         return 0;
 594 spi_geni_probe_free_irq:
 595         free_irq(mas->irq, spi);
 596 spi_geni_probe_runtime_disable:
 597         pm_runtime_disable(dev);
 598         spi_master_put(spi);
 599         return ret;
 600 }
 601
 602 static int spi_geni_remove(struct platform_device *pdev)
 603 {
 604         struct spi_master *spi = platform_get_drvdata(pdev);
 605         struct spi_geni_master *mas = spi_master_get_devdata(spi);
 606
 607         /* Unregister _before_ disabling pm_runtime() so we stop transfers */
 608         spi_unregister_master(spi);
 609
 610         free_irq(mas->irq, spi);
 611         pm_runtime_disable(&pdev->dev);
 612         return 0;
 613 }
 614
 615 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
 616 {
 617         struct spi_master *spi = dev_get_drvdata(dev);
 618         struct spi_geni_master *mas = spi_master_get_devdata(spi);
 619
 620         return geni_se_resources_off(&mas->se);
 621 }
 622
 623 static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
 624 {
 625         struct spi_master *spi = dev_get_drvdata(dev);
 626         struct spi_geni_master *mas = spi_master_get_devdata(spi);
 627
 628         return geni_se_resources_on(&mas->se);
 629 }
 630
 631 static int __maybe_unused spi_geni_suspend(struct device *dev)
 632 {
 633         struct spi_master *spi = dev_get_drvdata(dev);
 634         int ret;
 635
 636         ret = spi_master_suspend(spi);
 637         if (ret)
 638                 return ret;
 639
 640         ret = pm_runtime_force_suspend(dev);
 641         if (ret)
 642                 spi_master_resume(spi);
 643
 644         return ret;
 645 }
 646
 647 static int __maybe_unused spi_geni_resume(struct device *dev)
 648 {
 649         struct spi_master *spi = dev_get_drvdata(dev);
 650         int ret;
 651
 652         ret = pm_runtime_force_resume(dev);
 653         if (ret)
 654                 return ret;
 655
 656         ret = spi_master_resume(spi);
 657         if (ret)
 658                 pm_runtime_force_suspend(dev);
 659
 660         return ret;
 661 }
 662
 663 static const struct dev_pm_ops spi_geni_pm_ops = {
 664         SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
 665                                         spi_geni_runtime_resume, NULL)
 666         SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
 667 };
 668
 669 static const struct of_device_id spi_geni_dt_match[] = {
 670         { .compatible = "qcom,geni-spi" },
 671         {}
 672 };
 673 MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
 674
 675 static struct platform_driver spi_geni_driver = {
 676         .probe  = spi_geni_probe,
 677         .remove = spi_geni_remove,
 678         .driver = {
 679                 .name = "geni_spi",
 680                 .pm = &spi_geni_pm_ops,
 681                 .of_match_table = spi_geni_dt_match,
 682         },
 683 };
 684 module_platform_driver(spi_geni_driver);
 685
 686 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
 687 MODULE_LICENSE("GPL v2");