drivers/edac/x38_edac.c

   1 /*
   2  * Intel X38 Memory Controller kernel module
   3  * Copyright (C) 2008 Cluster Computing, Inc.
   4  *
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * This file is based on i3200_edac.c
   9  *
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/pci_ids.h>
  16 #include <linux/edac.h>
  17 #include "edac_core.h"
  18
  19 #define X38_REVISION            "1.1"
  20
  21 #define EDAC_MOD_STR            "x38_edac"
  22
  23 #define PCI_DEVICE_ID_INTEL_X38_HB      0x29e0
  24
  25 #define X38_RANKS               8
  26 #define X38_RANKS_PER_CHANNEL   4
  27 #define X38_CHANNELS            2
  28
  29 /* Intel X38 register addresses - device 0 function 0 - DRAM Controller */
  30
  31 #define X38_MCHBAR_LOW  0x48    /* MCH Memory Mapped Register BAR */
  32 #define X38_MCHBAR_HIGH 0x4c
  33 #define X38_MCHBAR_MASK 0xfffffc000ULL  /* bits 35:14 */
  34 #define X38_MMR_WINDOW_SIZE     16384
  35
  36 #define X38_TOM 0xa0    /* Top of Memory (16b)
  37                                  *
  38                                  * 15:10 reserved
  39                                  *  9:0  total populated physical memory
  40                                  */
  41 #define X38_TOM_MASK    0x3ff   /* bits 9:0 */
  42 #define X38_TOM_SHIFT 26        /* 64MiB grain */
  43
  44 #define X38_ERRSTS      0xc8    /* Error Status Register (16b)
  45                                  *
  46                                  * 15    reserved
  47                                  * 14    Isochronous TBWRR Run Behind FIFO Full
  48                                  *       (ITCV)
  49                                  * 13    Isochronous TBWRR Run Behind FIFO Put
  50                                  *       (ITSTV)
  51                                  * 12    reserved
  52                                  * 11    MCH Thermal Sensor Event
  53                                  *       for SMI/SCI/SERR (GTSE)
  54                                  * 10    reserved
  55                                  *  9    LOCK to non-DRAM Memory Flag (LCKF)
  56                                  *  8    reserved
  57                                  *  7    DRAM Throttle Flag (DTF)
  58                                  *  6:2  reserved
  59                                  *  1    Multi-bit DRAM ECC Error Flag (DMERR)
  60                                  *  0    Single-bit DRAM ECC Error Flag (DSERR)
  61                                  */
  62 #define X38_ERRSTS_UE           0x0002
  63 #define X38_ERRSTS_CE           0x0001
  64 #define X38_ERRSTS_BITS (X38_ERRSTS_UE | X38_ERRSTS_CE)
  65
  66
  67 /* Intel  MMIO register space - device 0 function 0 - MMR space */
  68
  69 #define X38_C0DRB       0x200   /* Channel 0 DRAM Rank Boundary (16b x 4)
  70                                  *
  71                                  * 15:10 reserved
  72                                  *  9:0  Channel 0 DRAM Rank Boundary Address
  73                                  */
  74 #define X38_C1DRB       0x600   /* Channel 1 DRAM Rank Boundary (16b x 4) */
  75 #define X38_DRB_MASK    0x3ff   /* bits 9:0 */
  76 #define X38_DRB_SHIFT 26        /* 64MiB grain */
  77
  78 #define X38_C0ECCERRLOG 0x280   /* Channel 0 ECC Error Log (64b)
  79                                  *
  80                                  * 63:48 Error Column Address (ERRCOL)
  81                                  * 47:32 Error Row Address (ERRROW)
  82                                  * 31:29 Error Bank Address (ERRBANK)
  83                                  * 28:27 Error Rank Address (ERRRANK)
  84                                  * 26:24 reserved
  85                                  * 23:16 Error Syndrome (ERRSYND)
  86                                  * 15: 2 reserved
  87                                  *    1  Multiple Bit Error Status (MERRSTS)
  88                                  *    0  Correctable Error Status (CERRSTS)
  89                                  */
  90 #define X38_C1ECCERRLOG 0x680   /* Channel 1 ECC Error Log (64b) */
  91 #define X38_ECCERRLOG_CE        0x1
  92 #define X38_ECCERRLOG_UE        0x2
  93 #define X38_ECCERRLOG_RANK_BITS 0x18000000
  94 #define X38_ECCERRLOG_SYNDROME_BITS     0xff0000
  95
  96 #define X38_CAPID0 0xe0 /* see P.94 of spec for details */
  97
  98 static int x38_channel_num;
  99
 100 static int how_many_channel(struct pci_dev *pdev)
 101 {
 102         unsigned char capid0_8b; /* 8th byte of CAPID0 */
 103
 104         pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b);
 105         if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
 106                 debugf0("In single channel mode.\n");
 107                 x38_channel_num = 1;
 108         } else {
 109                 debugf0("In dual channel mode.\n");
 110                 x38_channel_num = 2;
 111         }
 112
 113         return x38_channel_num;
 114 }
 115
 116 static unsigned long eccerrlog_syndrome(u64 log)
 117 {
 118         return (log & X38_ECCERRLOG_SYNDROME_BITS) >> 16;
 119 }
 120
 121 static int eccerrlog_row(int channel, u64 log)
 122 {
 123         return ((log & X38_ECCERRLOG_RANK_BITS) >> 27) |
 124                 (channel * X38_RANKS_PER_CHANNEL);
 125 }
 126
 127 enum x38_chips {
 128         X38 = 0,
 129 };
 130
 131 struct x38_dev_info {
 132         const char *ctl_name;
 133 };
 134
 135 struct x38_error_info {
 136         u16 errsts;
 137         u16 errsts2;
 138         u64 eccerrlog[X38_CHANNELS];
 139 };
 140
 141 static const struct x38_dev_info x38_devs[] = {
 142         [X38] = {
 143                 .ctl_name = "x38"},
 144 };
 145
 146 static struct pci_dev *mci_pdev;
 147 static int x38_registered = 1;
 148
 149
 150 static void x38_clear_error_info(struct mem_ctl_info *mci)
 151 {
 152         struct pci_dev *pdev;
 153
 154         pdev = to_pci_dev(mci->dev);
 155
 156         /*
 157          * Clear any error bits.
 158          * (Yes, we really clear bits by writing 1 to them.)
 159          */
 160         pci_write_bits16(pdev, X38_ERRSTS, X38_ERRSTS_BITS,
 161                          X38_ERRSTS_BITS);
 162 }
 163
 164 static u64 x38_readq(const void __iomem *addr)
 165 {
 166         return readl(addr) | (((u64)readl(addr + 4)) << 32);
 167 }
 168
 169 static void x38_get_and_clear_error_info(struct mem_ctl_info *mci,
 170                                  struct x38_error_info *info)
 171 {
 172         struct pci_dev *pdev;
 173         void __iomem *window = mci->pvt_info;
 174
 175         pdev = to_pci_dev(mci->dev);
 176
 177         /*
 178          * This is a mess because there is no atomic way to read all the
 179          * registers at once and the registers can transition from CE being
 180          * overwritten by UE.
 181          */
 182         pci_read_config_word(pdev, X38_ERRSTS, &info->errsts);
 183         if (!(info->errsts & X38_ERRSTS_BITS))
 184                 return;
 185
 186         info->eccerrlog[0] = x38_readq(window + X38_C0ECCERRLOG);
 187         if (x38_channel_num == 2)
 188                 info->eccerrlog[1] = x38_readq(window + X38_C1ECCERRLOG);
 189
 190         pci_read_config_word(pdev, X38_ERRSTS, &info->errsts2);
 191
 192         /*
 193          * If the error is the same for both reads then the first set
 194          * of reads is valid.  If there is a change then there is a CE
 195          * with no info and the second set of reads is valid and
 196          * should be UE info.
 197          */
 198         if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
 199                 info->eccerrlog[0] = x38_readq(window + X38_C0ECCERRLOG);
 200                 if (x38_channel_num == 2)
 201                         info->eccerrlog[1] =
 202                                 x38_readq(window + X38_C1ECCERRLOG);
 203         }
 204
 205         x38_clear_error_info(mci);
 206 }
 207
 208 static void x38_process_error_info(struct mem_ctl_info *mci,
 209                                 struct x38_error_info *info)
 210 {
 211         int channel;
 212         u64 log;
 213
 214         if (!(info->errsts & X38_ERRSTS_BITS))
 215                 return;
 216
 217         if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
 218                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
 219                 info->errsts = info->errsts2;
 220         }
 221
 222         for (channel = 0; channel < x38_channel_num; channel++) {
 223                 log = info->eccerrlog[channel];
 224                 if (log & X38_ECCERRLOG_UE) {
 225                         edac_mc_handle_ue(mci, 0, 0,
 226                                 eccerrlog_row(channel, log), "x38 UE");
 227                 } else if (log & X38_ECCERRLOG_CE) {
 228                         edac_mc_handle_ce(mci, 0, 0,
 229                                 eccerrlog_syndrome(log),
 230                                 eccerrlog_row(channel, log), 0, "x38 CE");
 231                 }
 232         }
 233 }
 234
 235 static void x38_check(struct mem_ctl_info *mci)
 236 {
 237         struct x38_error_info info;
 238
 239         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 240         x38_get_and_clear_error_info(mci, &info);
 241         x38_process_error_info(mci, &info);
 242 }
 243
 244
 245 void __iomem *x38_map_mchbar(struct pci_dev *pdev)
 246 {
 247         union {
 248                 u64 mchbar;
 249                 struct {
 250                         u32 mchbar_low;
 251                         u32 mchbar_high;
 252                 };
 253         } u;
 254         void __iomem *window;
 255
 256         pci_read_config_dword(pdev, X38_MCHBAR_LOW, &u.mchbar_low);
 257         pci_write_config_dword(pdev, X38_MCHBAR_LOW, u.mchbar_low | 0x1);
 258         pci_read_config_dword(pdev, X38_MCHBAR_HIGH, &u.mchbar_high);
 259         u.mchbar &= X38_MCHBAR_MASK;
 260
 261         if (u.mchbar != (resource_size_t)u.mchbar) {
 262                 printk(KERN_ERR
 263                         "x38: mmio space beyond accessible range (0x%llx)\n",
 264                         (unsigned long long)u.mchbar);
 265                 return NULL;
 266         }
 267
 268         window = ioremap_nocache(u.mchbar, X38_MMR_WINDOW_SIZE);
 269         if (!window)
 270                 printk(KERN_ERR "x38: cannot map mmio space at 0x%llx\n",
 271                         (unsigned long long)u.mchbar);
 272
 273         return window;
 274 }
 275
 276
 277 static void x38_get_drbs(void __iomem *window,
 278                         u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
 279 {
 280         int i;
 281
 282         for (i = 0; i < X38_RANKS_PER_CHANNEL; i++) {
 283                 drbs[0][i] = readw(window + X38_C0DRB + 2*i) & X38_DRB_MASK;
 284                 drbs[1][i] = readw(window + X38_C1DRB + 2*i) & X38_DRB_MASK;
 285         }
 286 }
 287
 288 static bool x38_is_stacked(struct pci_dev *pdev,
 289                         u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
 290 {
 291         u16 tom;
 292
 293         pci_read_config_word(pdev, X38_TOM, &tom);
 294         tom &= X38_TOM_MASK;
 295
 296         return drbs[X38_CHANNELS - 1][X38_RANKS_PER_CHANNEL - 1] == tom;
 297 }
 298
 299 static unsigned long drb_to_nr_pages(
 300                         u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL],
 301                         bool stacked, int channel, int rank)
 302 {
 303         int n;
 304
 305         n = drbs[channel][rank];
 306         if (rank > 0)
 307                 n -= drbs[channel][rank - 1];
 308         if (stacked && (channel == 1) && drbs[channel][rank] ==
 309                                 drbs[channel][X38_RANKS_PER_CHANNEL - 1]) {
 310                 n -= drbs[0][X38_RANKS_PER_CHANNEL - 1];
 311         }
 312
 313         n <<= (X38_DRB_SHIFT - PAGE_SHIFT);
 314         return n;
 315 }
 316
 317 static int x38_probe1(struct pci_dev *pdev, int dev_idx)
 318 {
 319         int rc;
 320         int i;
 321         struct mem_ctl_info *mci = NULL;
 322         unsigned long last_page;
 323         u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL];
 324         bool stacked;
 325         void __iomem *window;
 326
 327         debugf0("MC: %s()\n", __func__);
 328
 329         window = x38_map_mchbar(pdev);
 330         if (!window)
 331                 return -ENODEV;
 332
 333         x38_get_drbs(window, drbs);
 334
 335         how_many_channel(pdev);
 336
 337         /* FIXME: unconventional pvt_info usage */
 338         mci = edac_mc_alloc(0, X38_RANKS, x38_channel_num, 0);
 339         if (!mci)
 340                 return -ENOMEM;
 341
 342         debugf3("MC: %s(): init mci\n", __func__);
 343
 344         mci->dev = &pdev->dev;
 345         mci->mtype_cap = MEM_FLAG_DDR2;
 346
 347         mci->edac_ctl_cap = EDAC_FLAG_SECDED;
 348         mci->edac_cap = EDAC_FLAG_SECDED;
 349
 350         mci->mod_name = EDAC_MOD_STR;
 351         mci->mod_ver = X38_REVISION;
 352         mci->ctl_name = x38_devs[dev_idx].ctl_name;
 353         mci->dev_name = pci_name(pdev);
 354         mci->edac_check = x38_check;
 355         mci->ctl_page_to_phys = NULL;
 356         mci->pvt_info = window;
 357
 358         stacked = x38_is_stacked(pdev, drbs);
 359
 360         /*
 361          * The dram rank boundary (DRB) reg values are boundary addresses
 362          * for each DRAM rank with a granularity of 64MB.  DRB regs are
 363          * cumulative; the last one will contain the total memory
 364          * contained in all ranks.
 365          */
 366         last_page = -1UL;
 367         for (i = 0; i < mci->nr_csrows; i++) {
 368                 unsigned long nr_pages;
 369                 struct csrow_info *csrow = &mci->csrows[i];
 370
 371                 nr_pages = drb_to_nr_pages(drbs, stacked,
 372                         i / X38_RANKS_PER_CHANNEL,
 373                         i % X38_RANKS_PER_CHANNEL);
 374
 375                 if (nr_pages == 0) {
 376                         csrow->mtype = MEM_EMPTY;
 377                         continue;
 378                 }
 379
 380                 csrow->first_page = last_page + 1;
 381                 last_page += nr_pages;
 382                 csrow->last_page = last_page;
 383                 csrow->nr_pages = nr_pages;
 384
 385                 csrow->grain = nr_pages << PAGE_SHIFT;
 386                 csrow->mtype = MEM_DDR2;
 387                 csrow->dtype = DEV_UNKNOWN;
 388                 csrow->edac_mode = EDAC_UNKNOWN;
 389         }
 390
 391         x38_clear_error_info(mci);
 392
 393         rc = -ENODEV;
 394         if (edac_mc_add_mc(mci)) {
 395                 debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
 396                 goto fail;
 397         }
 398
 399         /* get this far and it's successful */
 400         debugf3("MC: %s(): success\n", __func__);
 401         return 0;
 402
 403 fail:
 404         iounmap(window);
 405         if (mci)
 406                 edac_mc_free(mci);
 407
 408         return rc;
 409 }
 410
 411 static int __devinit x38_init_one(struct pci_dev *pdev,
 412                                 const struct pci_device_id *ent)
 413 {
 414         int rc;
 415
 416         debugf0("MC: %s()\n", __func__);
 417
 418         if (pci_enable_device(pdev) < 0)
 419                 return -EIO;
 420
 421         rc = x38_probe1(pdev, ent->driver_data);
 422         if (!mci_pdev)
 423                 mci_pdev = pci_dev_get(pdev);
 424
 425         return rc;
 426 }
 427
 428 static void __devexit x38_remove_one(struct pci_dev *pdev)
 429 {
 430         struct mem_ctl_info *mci;
 431
 432         debugf0("%s()\n", __func__);
 433
 434         mci = edac_mc_del_mc(&pdev->dev);
 435         if (!mci)
 436                 return;
 437
 438         iounmap(mci->pvt_info);
 439
 440         edac_mc_free(mci);
 441 }
 442
 443 static DEFINE_PCI_DEVICE_TABLE(x38_pci_tbl) = {
 444         {
 445          PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 446          X38},
 447         {
 448          0,
 449          }                      /* 0 terminated list. */
 450 };
 451
 452 MODULE_DEVICE_TABLE(pci, x38_pci_tbl);
 453
 454 static struct pci_driver x38_driver = {
 455         .name = EDAC_MOD_STR,
 456         .probe = x38_init_one,
 457         .remove = __devexit_p(x38_remove_one),
 458         .id_table = x38_pci_tbl,
 459 };
 460
 461 static int __init x38_init(void)
 462 {
 463         int pci_rc;
 464
 465         debugf3("MC: %s()\n", __func__);
 466
 467         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
 468         opstate_init();
 469
 470         pci_rc = pci_register_driver(&x38_driver);
 471         if (pci_rc < 0)
 472                 goto fail0;
 473
 474         if (!mci_pdev) {
 475                 x38_registered = 0;
 476                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 477                                         PCI_DEVICE_ID_INTEL_X38_HB, NULL);
 478                 if (!mci_pdev) {
 479                         debugf0("x38 pci_get_device fail\n");
 480                         pci_rc = -ENODEV;
 481                         goto fail1;
 482                 }
 483
 484                 pci_rc = x38_init_one(mci_pdev, x38_pci_tbl);
 485                 if (pci_rc < 0) {
 486                         debugf0("x38 init fail\n");
 487                         pci_rc = -ENODEV;
 488                         goto fail1;
 489                 }
 490         }
 491
 492         return 0;
 493
 494 fail1:
 495         pci_unregister_driver(&x38_driver);
 496
 497 fail0:
 498         if (mci_pdev)
 499                 pci_dev_put(mci_pdev);
 500
 501         return pci_rc;
 502 }
 503
 504 static void __exit x38_exit(void)
 505 {
 506         debugf3("MC: %s()\n", __func__);
 507
 508         pci_unregister_driver(&x38_driver);
 509         if (!x38_registered) {
 510                 x38_remove_one(mci_pdev);
 511                 pci_dev_put(mci_pdev);
 512         }
 513 }
 514
 515 module_init(x38_init);
 516 module_exit(x38_exit);
 517
 518 MODULE_LICENSE("GPL");
 519 MODULE_AUTHOR("Cluster Computing, Inc. Hitoshi Mitake");
 520 MODULE_DESCRIPTION("MC support for Intel X38 memory hub controllers");
 521
 522 module_param(edac_op_state, int, 0444);
 523 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");