arch/arm/mach-kirkwood/include/mach/kirkwood.h

   1 /*
   2  * arch/arm/mach-kirkwood/include/mach/kirkwood.h
   3  *
   4  * Generic definitions for Marvell Kirkwood SoC flavors:
   5  *  88F6180, 88F6192 and 88F6281.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2.  This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #ifndef __ASM_ARCH_KIRKWOOD_H
  13 #define __ASM_ARCH_KIRKWOOD_H
  14
  15 /*
  16  * Marvell Kirkwood address maps.
  17  *
  18  * phys
  19  * e0000000     PCIe #0 Memory space
  20  * e8000000     PCIe #1 Memory space
  21  * f1000000     on-chip peripheral registers
  22  * f2000000     PCIe #0 I/O space
  23  * f3000000     PCIe #1 I/O space
  24  * f4000000     NAND controller address window
  25  * f5000000     Security Accelerator SRAM
  26  *
  27  * virt         phys            size
  28  * fed00000     f1000000        1M      on-chip peripheral registers
  29  * fee00000     f2000000        1M      PCIe #0 I/O space
  30  * fef00000     f3000000        1M      PCIe #1 I/O space
  31  */
  32
  33 #define KIRKWOOD_SRAM_PHYS_BASE         0xf5000000
  34 #define KIRKWOOD_SRAM_SIZE              SZ_2K
  35
  36 #define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf4000000
  37 #define KIRKWOOD_NAND_MEM_SIZE          SZ_1K
  38
  39 #define KIRKWOOD_PCIE1_IO_PHYS_BASE     0xf3000000
  40 #define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00010000
  41 #define KIRKWOOD_PCIE1_IO_SIZE          SZ_64K
  42
  43 #define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
  44 #define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
  45 #define KIRKWOOD_PCIE_IO_SIZE           SZ_64K
  46
  47 #define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
  48 #define KIRKWOOD_REGS_VIRT_BASE         IOMEM(0xfed00000)
  49 #define KIRKWOOD_REGS_SIZE              SZ_1M
  50
  51 #define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
  52 #define KIRKWOOD_PCIE_MEM_BUS_BASE      0xe0000000
  53 #define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
  54
  55 #define KIRKWOOD_PCIE1_MEM_PHYS_BASE    0xe8000000
  56 #define KIRKWOOD_PCIE1_MEM_BUS_BASE     0xe8000000
  57 #define KIRKWOOD_PCIE1_MEM_SIZE         SZ_128M
  58
  59 /*
  60  * Register Map
  61  */
  62 #define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
  63 #define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE + 0x1500)
  64 #define DDR_OPERATION_BASE      (DDR_VIRT_BASE + 0x1418)
  65
  66 #define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
  67 #define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
  68 #define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE + 0x0030)
  69 #define  DEVICE_ID              (DEV_BUS_VIRT_BASE + 0x0034)
  70 #define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE + 0x0100)
  71 #define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x0140)
  72 #define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0300)
  73 #define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0600)
  74 #define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x1000)
  75 #define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
  76 #define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
  77 #define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
  78 #define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
  79
  80 #define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
  81 #define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
  82
  83 #define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
  84
  85 #define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
  86 #define PCIE_LINK_CTRL          (PCIE_VIRT_BASE + 0x70)
  87 #define PCIE_STATUS             (PCIE_VIRT_BASE + 0x1a04)
  88 #define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
  89 #define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE + 0x70)
  90 #define PCIE1_STATUS            (PCIE1_VIRT_BASE + 0x1a04)
  91
  92 #define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
  93
  94 #define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
  95 #define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
  96 #define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
  97 #define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
  98 #define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
  99 #define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
 100 #define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
 101 #define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
 102
 103 #define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
 104 #define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
 105
 106 #define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
 107 #define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
 108 #define SATA0_IF_CTRL           (SATA_VIRT_BASE + 0x2050)
 109 #define SATA0_PHY_MODE_2        (SATA_VIRT_BASE + 0x2330)
 110 #define SATA1_IF_CTRL           (SATA_VIRT_BASE + 0x4050)
 111 #define SATA1_PHY_MODE_2        (SATA_VIRT_BASE + 0x4330)
 112
 113 #define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
 114
 115 #define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
 116 #define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
 117
 118 /*
 119  * Supported devices and revisions.
 120  */
 121 #define MV88F6281_DEV_ID        0x6281
 122 #define MV88F6281_REV_Z0        0
 123 #define MV88F6281_REV_A0        2
 124 #define MV88F6281_REV_A1        3
 125
 126 #define MV88F6192_DEV_ID        0x6192
 127 #define MV88F6192_REV_Z0        0
 128 #define MV88F6192_REV_A0        2
 129 #define MV88F6192_REV_A1        3
 130
 131 #define MV88F6180_DEV_ID        0x6180
 132 #define MV88F6180_REV_A0        2
 133 #define MV88F6180_REV_A1        3
 134
 135 #define MV88F6282_DEV_ID        0x6282
 136 #define MV88F6282_REV_A0        0
 137 #define MV88F6282_REV_A1        1
 138 #endif