arch/blackfin/mach-bf609/ints-priority.c

   1 /*
   2  * Copyright 2007-2008 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  *
   6  * Set up the interrupt priorities
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/irq.h>
  11 #include <asm/blackfin.h>
  12
  13 u8 sec_int_priority[] = {
  14         255,    /* IRQ_SEC_ERR */
  15         255,    /* IRQ_CGU_EVT */
  16         254,    /* IRQ_WATCH0 */
  17         254,    /* IRQ_WATCH1 */
  18         253,    /* IRQ_L2CTL0_ECC_ERR */
  19         253,    /* IRQ_L2CTL0_ECC_WARN */
  20         253,    /* IRQ_C0_DBL_FAULT */
  21         253,    /* IRQ_C1_DBL_FAULT */
  22         252,    /* IRQ_C0_HW_ERR */
  23         252,    /* IRQ_C1_HW_ERR */
  24         255,    /* IRQ_C0_NMI_L1_PARITY_ERR */
  25         255,    /* IRQ_C1_NMI_L1_PARITY_ERR */
  26
  27         50,     /* IRQ_TIMER0 */
  28         50,     /* IRQ_TIMER1 */
  29         50,     /* IRQ_TIMER2 */
  30         50,     /* IRQ_TIMER3 */
  31         50,     /* IRQ_TIMER4 */
  32         50,     /* IRQ_TIMER5 */
  33         50,     /* IRQ_TIMER6 */
  34         50,     /* IRQ_TIMER7 */
  35         50,     /* IRQ_TIMER_STAT */
  36         0,      /* IRQ_PINT0 */
  37         0,      /* IRQ_PINT1 */
  38         0,      /* IRQ_PINT2 */
  39         0,      /* IRQ_PINT3 */
  40         0,      /* IRQ_PINT4 */
  41         0,      /* IRQ_PINT5 */
  42         0,      /* IRQ_CNT */
  43         50,     /* RQ_PWM0_TRIP */
  44         50,     /* IRQ_PWM0_SYNC */
  45         50,     /* IRQ_PWM1_TRIP */
  46         50,     /* IRQ_PWM1_SYNC */
  47         0,      /* IRQ_TWI0 */
  48         0,      /* IRQ_TWI1 */
  49         10,     /* IRQ_SOFT0 */
  50         10,     /* IRQ_SOFT1 */
  51         10,     /* IRQ_SOFT2 */
  52         10,     /* IRQ_SOFT3 */
  53         0,      /* IRQ_ACM_EVT_MISS */
  54         0,      /* IRQ_ACM_EVT_COMPLETE */
  55         0,      /* IRQ_CAN0_RX */
  56         0,      /* IRQ_CAN0_TX */
  57         0,      /* IRQ_CAN0_STAT */
  58         100,    /* IRQ_SPORT0_TX */
  59         100,    /* IRQ_SPORT0_TX_STAT */
  60         100,    /* IRQ_SPORT0_RX */
  61         100,    /* IRQ_SPORT0_RX_STAT */
  62         100,    /* IRQ_SPORT1_TX */
  63         100,    /* IRQ_SPORT1_TX_STAT */
  64         100,    /* IRQ_SPORT1_RX */
  65         100,    /* IRQ_SPORT1_RX_STAT */
  66         100,    /* IRQ_SPORT2_TX */
  67         100,    /* IRQ_SPORT2_TX_STAT */
  68         100,    /* IRQ_SPORT2_RX */
  69         100,    /* IRQ_SPORT2_RX_STAT */
  70         0,      /* IRQ_SPI0_TX */
  71         0,      /* IRQ_SPI0_RX */
  72         0,      /* IRQ_SPI0_STAT */
  73         0,      /* IRQ_SPI1_TX */
  74         0,      /* IRQ_SPI1_RX */
  75         0,      /* IRQ_SPI1_STAT */
  76         0,      /* IRQ_RSI */
  77         0,      /* IRQ_RSI_INT0 */
  78         0,      /* IRQ_RSI_INT1 */
  79         0,      /* DMA11 Data (SDU) */
  80         0,      /* DMA12 Data (Reserved) */
  81         0,      /* Reserved */
  82         0,      /* Reserved */
  83         30,     /* IRQ_EMAC0_STAT */
  84         0,      /* EMAC0 Power (Reserved) */
  85         30,     /* IRQ_EMAC1_STAT */
  86         0,      /* EMAC1 Power (Reserved) */
  87         0,      /* IRQ_LP0 */
  88         0,      /* IRQ_LP0_STAT */
  89         0,      /* IRQ_LP1 */
  90         0,      /* IRQ_LP1_STAT */
  91         0,      /* IRQ_LP2 */
  92         0,      /* IRQ_LP2_STAT */
  93         0,      /* IRQ_LP3 */
  94         0,      /* IRQ_LP3_STAT */
  95         0,      /* IRQ_UART0_TX */
  96         0,      /* IRQ_UART0_RX */
  97         0,      /* IRQ_UART0_STAT */
  98         0,      /* IRQ_UART1_TX */
  99         0,      /* IRQ_UART1_RX */
 100         0,      /* IRQ_UART1_STAT */
 101         0,      /* IRQ_MDMA0_SRC_CRC0 */
 102         0,      /* IRQ_MDMA0_DEST_CRC0 */
 103         0,      /* IRQ_CRC0_DCNTEXP */
 104         0,      /* IRQ_CRC0_ERR */
 105         0,      /* IRQ_MDMA1_SRC_CRC1 */
 106         0,      /* IRQ_MDMA1_DEST_CRC1 */
 107         0,      /* IRQ_CRC1_DCNTEXP */
 108         0,      /* IRQ_CRC1_ERR */
 109         0,      /* IRQ_MDMA2_SRC */
 110         0,      /* IRQ_MDMA2_DEST */
 111         0,      /* IRQ_MDMA3_SRC */
 112         0,      /* IRQ_MDMA3_DEST */
 113         120,    /* IRQ_EPPI0_CH0 */
 114         120,    /* IRQ_EPPI0_CH1 */
 115         120,    /* IRQ_EPPI0_STAT */
 116         120,    /* IRQ_EPPI2_CH0 */
 117         120,    /* IRQ_EPPI2_CH1 */
 118         120,    /* IRQ_EPPI2_STAT */
 119         120,    /* IRQ_EPPI1_CH0 */
 120         120,    /* IRQ_EPPI1_CH1 */
 121         120,    /* IRQ_EPPI1_STAT */
 122         120,    /* IRQ_PIXC_CH0 */
 123         120,    /* IRQ_PIXC_CH1 */
 124         120,    /* IRQ_PIXC_CH2 */
 125         120,    /* IRQ_PIXC_STAT */
 126         120,    /* IRQ_PVP_CPDOB */
 127         120,    /* IRQ_PVP_CPDOC */
 128         120,    /* IRQ_PVP_CPSTAT */
 129         120,    /* IRQ_PVP_CPCI */
 130         120,    /* IRQ_PVP_STAT0 */
 131         120,    /* IRQ_PVP_MPDO */
 132         120,    /* IRQ_PVP_MPDI */
 133         120,    /* IRQ_PVP_MPSTAT */
 134         120,    /* IRQ_PVP_MPCI */
 135         120,    /* IRQ_PVP_CPDOA */
 136         120,    /* IRQ_PVP_STAT1 */
 137         0,      /* IRQ_USB_STAT */
 138         0,      /* IRQ_USB_DMA */
 139         0,      /* IRQ_TRU_INT0 */
 140         0,      /* IRQ_TRU_INT1 */
 141         0,      /* IRQ_TRU_INT2 */
 142         0,      /* IRQ_TRU_INT3 */
 143         0,      /* IRQ_DMAC0_ERROR */
 144         0,      /* IRQ_CGU0_ERROR */
 145         0,      /* Reserved */
 146         0,      /* IRQ_DPM */
 147         0,      /* Reserved */
 148         0,      /* IRQ_SWU0 */
 149         0,      /* IRQ_SWU1 */
 150         0,      /* IRQ_SWU2 */
 151         0,      /* IRQ_SWU3 */
 152         0,      /* IRQ_SWU4 */
 153         0,      /* IRQ_SWU4 */
 154         0,      /* IRQ_SWU6 */
 155 };
 156