2 * cpu.h: Values of the PRId register used to match up
3 * various MIPS cpu types.
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 2004 Maciej W. Rozycki
11 /* Assigned Company values for bits 23:16 of the PRId Register
12 (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
13 MTI, the PRId register is defined in this (backwards compatible)
16 +----------------+----------------+----------------+----------------+
17 | Company Options| Company ID | Processor ID | Revision |
18 +----------------+----------------+----------------+----------------+
21 I don't have docs for all the previous processors, but my impression is
22 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
26 #define PRID_COMP_LEGACY 0x000000
27 #define PRID_COMP_MIPS 0x010000
28 #define PRID_COMP_BROADCOM 0x020000
29 #define PRID_COMP_ALCHEMY 0x030000
30 #define PRID_COMP_SIBYTE 0x040000
31 #define PRID_COMP_SANDCRAFT 0x050000
32 #define PRID_COMP_NXP 0x060000
33 #define PRID_COMP_TOSHIBA 0x070000
34 #define PRID_COMP_LSI 0x080000
35 #define PRID_COMP_LEXRA 0x0b0000
36 #define PRID_COMP_NETLOGIC 0x0c0000
37 #define PRID_COMP_CAVIUM 0x0d0000
38 #define PRID_COMP_INGENIC 0xd00000
41 * Assigned values for the product ID register. In order to detect a
42 * certain CPU type exactly eventually additional registers may need to
43 * be examined. These are valid when 23:16 == PRID_COMP_LEGACY
45 #define PRID_IMP_R2000 0x0100
46 #define PRID_IMP_AU1_REV1 0x0100
47 #define PRID_IMP_AU1_REV2 0x0200
48 #define PRID_IMP_R3000 0x0200 /* Same as R2000A */
49 #define PRID_IMP_R6000 0x0300 /* Same as R3000A */
50 #define PRID_IMP_R4000 0x0400
51 #define PRID_IMP_R6000A 0x0600
52 #define PRID_IMP_R10000 0x0900
53 #define PRID_IMP_R4300 0x0b00
54 #define PRID_IMP_VR41XX 0x0c00
55 #define PRID_IMP_R12000 0x0e00
56 #define PRID_IMP_R14000 0x0f00
57 #define PRID_IMP_R8000 0x1000
58 #define PRID_IMP_PR4450 0x1200
59 #define PRID_IMP_R4600 0x2000
60 #define PRID_IMP_R4700 0x2100
61 #define PRID_IMP_TX39 0x2200
62 #define PRID_IMP_R4640 0x2200
63 #define PRID_IMP_R4650 0x2200 /* Same as R4640 */
64 #define PRID_IMP_R5000 0x2300
65 #define PRID_IMP_TX49 0x2d00
66 #define PRID_IMP_SONIC 0x2400
67 #define PRID_IMP_MAGIC 0x2500
68 #define PRID_IMP_RM7000 0x2700
69 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
70 #define PRID_IMP_RM9000 0x3400
71 #define PRID_IMP_LOONGSON1 0x4200
72 #define PRID_IMP_R5432 0x5400
73 #define PRID_IMP_R5500 0x5500
74 #define PRID_IMP_LOONGSON2 0x6300
76 #define PRID_IMP_UNKNOWN 0xff00
79 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
82 #define PRID_IMP_4KC 0x8000
83 #define PRID_IMP_5KC 0x8100
84 #define PRID_IMP_20KC 0x8200
85 #define PRID_IMP_4KEC 0x8400
86 #define PRID_IMP_4KSC 0x8600
87 #define PRID_IMP_25KF 0x8800
88 #define PRID_IMP_5KE 0x8900
89 #define PRID_IMP_4KECR2 0x9000
90 #define PRID_IMP_4KEMPR2 0x9100
91 #define PRID_IMP_4KSD 0x9200
92 #define PRID_IMP_24K 0x9300
93 #define PRID_IMP_34K 0x9500
94 #define PRID_IMP_24KE 0x9600
95 #define PRID_IMP_74K 0x9700
96 #define PRID_IMP_1004K 0x9900
97 #define PRID_IMP_1074K 0x9a00
98 #define PRID_IMP_M14KC 0x9c00
101 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
104 #define PRID_IMP_SB1 0x0100
105 #define PRID_IMP_SB1A 0x1100
108 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
111 #define PRID_IMP_SR71000 0x0400
114 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
117 #define PRID_IMP_BMIPS32_REV4 0x4000
118 #define PRID_IMP_BMIPS32_REV8 0x8000
119 #define PRID_IMP_BMIPS3300 0x9000
120 #define PRID_IMP_BMIPS3300_ALT 0x9100
121 #define PRID_IMP_BMIPS3300_BUG 0x0000
122 #define PRID_IMP_BMIPS43XX 0xa000
123 #define PRID_IMP_BMIPS5000 0x5a00
125 #define PRID_REV_BMIPS4380_LO 0x0040
126 #define PRID_REV_BMIPS4380_HI 0x006f
129 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
132 #define PRID_IMP_CAVIUM_CN38XX 0x0000
133 #define PRID_IMP_CAVIUM_CN31XX 0x0100
134 #define PRID_IMP_CAVIUM_CN30XX 0x0200
135 #define PRID_IMP_CAVIUM_CN58XX 0x0300
136 #define PRID_IMP_CAVIUM_CN56XX 0x0400
137 #define PRID_IMP_CAVIUM_CN50XX 0x0600
138 #define PRID_IMP_CAVIUM_CN52XX 0x0700
139 #define PRID_IMP_CAVIUM_CN63XX 0x9000
140 #define PRID_IMP_CAVIUM_CN68XX 0x9100
141 #define PRID_IMP_CAVIUM_CN66XX 0x9200
142 #define PRID_IMP_CAVIUM_CN61XX 0x9300
145 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
148 #define PRID_IMP_JZRISC 0x0200
151 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
153 #define PRID_IMP_NETLOGIC_XLR732 0x0000
154 #define PRID_IMP_NETLOGIC_XLR716 0x0200
155 #define PRID_IMP_NETLOGIC_XLR532 0x0900
156 #define PRID_IMP_NETLOGIC_XLR308 0x0600
157 #define PRID_IMP_NETLOGIC_XLR532C 0x0800
158 #define PRID_IMP_NETLOGIC_XLR516C 0x0a00
159 #define PRID_IMP_NETLOGIC_XLR508C 0x0b00
160 #define PRID_IMP_NETLOGIC_XLR308C 0x0f00
161 #define PRID_IMP_NETLOGIC_XLS608 0x8000
162 #define PRID_IMP_NETLOGIC_XLS408 0x8800
163 #define PRID_IMP_NETLOGIC_XLS404 0x8c00
164 #define PRID_IMP_NETLOGIC_XLS208 0x8e00
165 #define PRID_IMP_NETLOGIC_XLS204 0x8f00
166 #define PRID_IMP_NETLOGIC_XLS108 0xce00
167 #define PRID_IMP_NETLOGIC_XLS104 0xcf00
168 #define PRID_IMP_NETLOGIC_XLS616B 0x4000
169 #define PRID_IMP_NETLOGIC_XLS608B 0x4a00
170 #define PRID_IMP_NETLOGIC_XLS416B 0x4400
171 #define PRID_IMP_NETLOGIC_XLS412B 0x4c00
172 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00
173 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00
174 #define PRID_IMP_NETLOGIC_AU13XX 0x8000
176 #define PRID_IMP_NETLOGIC_XLP8XX 0x1000
177 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100
180 * Definitions for 7:0 on legacy processors
183 #define PRID_REV_MASK 0x00ff
185 #define PRID_REV_TX4927 0x0022
186 #define PRID_REV_TX4937 0x0030
187 #define PRID_REV_R4400 0x0040
188 #define PRID_REV_R3000A 0x0030
189 #define PRID_REV_R3000 0x0020
190 #define PRID_REV_R2000A 0x0010
191 #define PRID_REV_TX3912 0x0010
192 #define PRID_REV_TX3922 0x0030
193 #define PRID_REV_TX3927 0x0040
194 #define PRID_REV_VR4111 0x0050
195 #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
196 #define PRID_REV_VR4121 0x0060
197 #define PRID_REV_VR4122 0x0070
198 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
199 #define PRID_REV_VR4130 0x0080
200 #define PRID_REV_34K_V1_0_2 0x0022
201 #define PRID_REV_LOONGSON1B 0x0020
202 #define PRID_REV_LOONGSON2E 0x0002
203 #define PRID_REV_LOONGSON2F 0x0003
206 * Older processors used to encode processor version and revision in two
207 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
208 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
209 * the patch number. *ARGH*
211 #define PRID_REV_ENCODE_44(ver, rev) \
213 #define PRID_REV_ENCODE_332(ver, rev, patch) \
214 ((ver) << 5 | (rev) << 2 | (patch))
217 * FPU implementation/revision register (CP1 control register 0).
219 * +---------------------------------+----------------+----------------+
220 * | 0 | Implementation | Revision |
221 * +---------------------------------+----------------+----------------+
225 #define FPIR_IMP_NONE 0x0000
231 * R2000 class processors
233 CPU_R2000
, CPU_R3000
, CPU_R3000A
, CPU_R3041
, CPU_R3051
, CPU_R3052
,
234 CPU_R3081
, CPU_R3081E
,
237 * R6000 class processors
239 CPU_R6000
, CPU_R6000A
,
242 * R4000 class processors
244 CPU_R4000PC
, CPU_R4000SC
, CPU_R4000MC
, CPU_R4200
, CPU_R4300
, CPU_R4310
,
245 CPU_R4400PC
, CPU_R4400SC
, CPU_R4400MC
, CPU_R4600
, CPU_R4640
, CPU_R4650
,
246 CPU_R4700
, CPU_R5000
, CPU_R5500
, CPU_NEVADA
, CPU_R5432
, CPU_R10000
,
247 CPU_R12000
, CPU_R14000
, CPU_VR41XX
, CPU_VR4111
, CPU_VR4121
, CPU_VR4122
,
248 CPU_VR4131
, CPU_VR4133
, CPU_VR4181
, CPU_VR4181A
, CPU_RM7000
,
249 CPU_SR71000
, CPU_RM9000
, CPU_TX49XX
,
252 * R8000 class processors
257 * TX3900 class processors
259 CPU_TX3912
, CPU_TX3922
, CPU_TX3927
,
262 * MIPS32 class processors
264 CPU_4KC
, CPU_4KEC
, CPU_4KSC
, CPU_24K
, CPU_34K
, CPU_1004K
, CPU_74K
,
265 CPU_ALCHEMY
, CPU_PR4450
, CPU_BMIPS32
, CPU_BMIPS3300
, CPU_BMIPS4350
,
266 CPU_BMIPS4380
, CPU_BMIPS5000
, CPU_JZRISC
, CPU_LOONGSON1
, CPU_M14KC
,
269 * MIPS64 class processors
271 CPU_5KC
, CPU_5KE
, CPU_20KC
, CPU_25KF
, CPU_SB1
, CPU_SB1A
, CPU_LOONGSON2
,
272 CPU_CAVIUM_OCTEON
, CPU_CAVIUM_OCTEON_PLUS
, CPU_CAVIUM_OCTEON2
,
280 * ISA Level encodings
283 #define MIPS_CPU_ISA_I 0x00000001
284 #define MIPS_CPU_ISA_II 0x00000002
285 #define MIPS_CPU_ISA_III 0x00000004
286 #define MIPS_CPU_ISA_IV 0x00000008
287 #define MIPS_CPU_ISA_V 0x00000010
288 #define MIPS_CPU_ISA_M32R1 0x00000020
289 #define MIPS_CPU_ISA_M32R2 0x00000040
290 #define MIPS_CPU_ISA_M64R1 0x00000080
291 #define MIPS_CPU_ISA_M64R2 0x00000100
293 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
294 MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2)
295 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
296 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
299 * CPU Option encodings
301 #define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
302 #define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
303 #define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
304 #define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
305 #define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
306 #define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
307 #define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
308 #define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
309 #define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
310 #define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
311 #define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
312 #define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
313 #define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
314 #define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
315 #define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
316 #define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
317 #define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
318 #define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
319 #define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
320 #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
321 #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
322 #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
323 #define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
324 #define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
329 #define MIPS_ASE_MIPS16 0x00000001 /* code compression */
330 #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
331 #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
332 #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
333 #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
334 #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
335 #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
338 #endif /* _ASM_CPU_H */