drivers/clk/shmobile/clk-div6.c

   1 /*
   2  * r8a7790 Common Clock Framework support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  *
   6  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  */
  12
  13 #include <linux/clk-provider.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20
  21 #define CPG_DIV6_CKSTP          BIT(8)
  22 #define CPG_DIV6_DIV(d)         ((d) & 0x3f)
  23 #define CPG_DIV6_DIV_MASK       0x3f
  24
  25 /**
  26  * struct div6_clock - CPG 6 bit divider clock
  27  * @hw: handle between common and hardware-specific interfaces
  28  * @reg: IO-remapped register
  29  * @div: divisor value (1-64)
  30  */
  31 struct div6_clock {
  32         struct clk_hw hw;
  33         void __iomem *reg;
  34         unsigned int div;
  35         u32 src_shift;
  36         u32 src_width;
  37         u8 *parents;
  38 };
  39
  40 #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
  41
  42 static int cpg_div6_clock_enable(struct clk_hw *hw)
  43 {
  44         struct div6_clock *clock = to_div6_clock(hw);
  45         u32 val;
  46
  47         val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
  48             | CPG_DIV6_DIV(clock->div - 1);
  49         clk_writel(val, clock->reg);
  50
  51         return 0;
  52 }
  53
  54 static void cpg_div6_clock_disable(struct clk_hw *hw)
  55 {
  56         struct div6_clock *clock = to_div6_clock(hw);
  57         u32 val;
  58
  59         val = clk_readl(clock->reg);
  60         val |= CPG_DIV6_CKSTP;
  61         /*
  62          * DIV6 clocks require the divisor field to be non-zero when stopping
  63          * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
  64          * re-enabled later if the divisor field is changed when stopping the
  65          * clock
  66          */
  67         if (!(val & CPG_DIV6_DIV_MASK))
  68                 val |= CPG_DIV6_DIV_MASK;
  69         clk_writel(val, clock->reg);
  70 }
  71
  72 static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
  73 {
  74         struct div6_clock *clock = to_div6_clock(hw);
  75
  76         return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
  77 }
  78
  79 static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
  80                                                 unsigned long parent_rate)
  81 {
  82         struct div6_clock *clock = to_div6_clock(hw);
  83         unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
  84
  85         return parent_rate / div;
  86 }
  87
  88 static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
  89                                             unsigned long parent_rate)
  90 {
  91         unsigned int div;
  92
  93         div = DIV_ROUND_CLOSEST(parent_rate, rate);
  94         return clamp_t(unsigned int, div, 1, 64);
  95 }
  96
  97 static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
  98                                       unsigned long *parent_rate)
  99 {
 100         unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
 101
 102         return *parent_rate / div;
 103 }
 104
 105 static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
 106                                    unsigned long parent_rate)
 107 {
 108         struct div6_clock *clock = to_div6_clock(hw);
 109         unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
 110         u32 val;
 111
 112         clock->div = div;
 113
 114         val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
 115         /* Only program the new divisor if the clock isn't stopped. */
 116         if (!(val & CPG_DIV6_CKSTP))
 117                 clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
 118
 119         return 0;
 120 }
 121
 122 static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
 123 {
 124         struct div6_clock *clock = to_div6_clock(hw);
 125         unsigned int i;
 126         u8 hw_index;
 127
 128         if (clock->src_width == 0)
 129                 return 0;
 130
 131         hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
 132                    (BIT(clock->src_width) - 1);
 133         for (i = 0; i < __clk_get_num_parents(hw->clk); i++) {
 134                 if (clock->parents[i] == hw_index)
 135                         return i;
 136         }
 137
 138         pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
 139                __func__, __clk_get_name(hw->clk), hw_index);
 140         return 0;
 141 }
 142
 143 static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
 144 {
 145         struct div6_clock *clock = to_div6_clock(hw);
 146         u8 hw_index;
 147         u32 mask;
 148
 149         if (index >= __clk_get_num_parents(hw->clk))
 150                 return -EINVAL;
 151
 152         mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
 153         hw_index = clock->parents[index];
 154
 155         clk_writel((clk_readl(clock->reg) & mask) |
 156                 (hw_index << clock->src_shift), clock->reg);
 157
 158         return 0;
 159 }
 160
 161 static const struct clk_ops cpg_div6_clock_ops = {
 162         .enable = cpg_div6_clock_enable,
 163         .disable = cpg_div6_clock_disable,
 164         .is_enabled = cpg_div6_clock_is_enabled,
 165         .get_parent = cpg_div6_clock_get_parent,
 166         .set_parent = cpg_div6_clock_set_parent,
 167         .recalc_rate = cpg_div6_clock_recalc_rate,
 168         .round_rate = cpg_div6_clock_round_rate,
 169         .set_rate = cpg_div6_clock_set_rate,
 170 };
 171
 172 static void __init cpg_div6_clock_init(struct device_node *np)
 173 {
 174         unsigned int num_parents, valid_parents;
 175         const char **parent_names;
 176         struct clk_init_data init;
 177         struct div6_clock *clock;
 178         const char *name;
 179         struct clk *clk;
 180         unsigned int i;
 181         int ret;
 182
 183         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 184         if (!clock)
 185                 return;
 186
 187         num_parents = of_clk_get_parent_count(np);
 188         if (num_parents < 1) {
 189                 pr_err("%s: no parent found for %s DIV6 clock\n",
 190                        __func__, np->name);
 191                 return;
 192         }
 193
 194         clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
 195                 GFP_KERNEL);
 196         parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
 197                                 GFP_KERNEL);
 198         if (!parent_names)
 199                 return;
 200
 201         /* Remap the clock register and read the divisor. Disabling the
 202          * clock overwrites the divisor, so we need to cache its value for the
 203          * enable operation.
 204          */
 205         clock->reg = of_iomap(np, 0);
 206         if (clock->reg == NULL) {
 207                 pr_err("%s: failed to map %s DIV6 clock register\n",
 208                        __func__, np->name);
 209                 goto error;
 210         }
 211
 212         clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
 213
 214         /* Parse the DT properties. */
 215         ret = of_property_read_string(np, "clock-output-names", &name);
 216         if (ret < 0) {
 217                 pr_err("%s: failed to get %s DIV6 clock output name\n",
 218                        __func__, np->name);
 219                 goto error;
 220         }
 221
 222
 223         for (i = 0, valid_parents = 0; i < num_parents; i++) {
 224                 const char *name = of_clk_get_parent_name(np, i);
 225
 226                 if (name) {
 227                         parent_names[valid_parents] = name;
 228                         clock->parents[valid_parents] = i;
 229                         valid_parents++;
 230                 }
 231         }
 232
 233         switch (num_parents) {
 234         case 1:
 235                 /* fixed parent clock */
 236                 clock->src_shift = clock->src_width = 0;
 237                 break;
 238         case 4:
 239                 /* clock with EXSRC bits 6-7 */
 240                 clock->src_shift = 6;
 241                 clock->src_width = 2;
 242                 break;
 243         case 8:
 244                 /* VCLK with EXSRC bits 12-14 */
 245                 clock->src_shift = 12;
 246                 clock->src_width = 3;
 247                 break;
 248         default:
 249                 pr_err("%s: invalid number of parents for DIV6 clock %s\n",
 250                        __func__, np->name);
 251                 goto error;
 252         }
 253
 254         /* Register the clock. */
 255         init.name = name;
 256         init.ops = &cpg_div6_clock_ops;
 257         init.flags = CLK_IS_BASIC;
 258         init.parent_names = parent_names;
 259         init.num_parents = valid_parents;
 260
 261         clock->hw.init = &init;
 262
 263         clk = clk_register(NULL, &clock->hw);
 264         if (IS_ERR(clk)) {
 265                 pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
 266                        __func__, np->name, PTR_ERR(clk));
 267                 goto error;
 268         }
 269
 270         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 271
 272         kfree(parent_names);
 273         return;
 274
 275 error:
 276         if (clock->reg)
 277                 iounmap(clock->reg);
 278         kfree(parent_names);
 279         kfree(clock);
 280 }
 281 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);