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[media] media: coda: Fix DT driver data pointer for i.MX27
[linux/fpc-iii.git] / drivers / clk / tegra / clk-pll.c
blob197074a5775421371d8c17526a6799ea4212b202
1 /*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/slab.h>
18 #include <linux/io.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
23
24 #include "clk.h"
25
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
30
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
38
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
49
50 #define OUT_OF_TABLE_CPCON 8
51
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
55
56 #define PLL_POST_LOCK_DELAY 50
57
58 #define PLLDU_LFCON_SET_DIVN 600
59
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_WIDTH 4
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 7
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
68
69 #define PLLE_MISC_SETUP_BASE_SHIFT 16
70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
71 #define PLLE_MISC_LOCK_ENABLE BIT(9)
72 #define PLLE_MISC_READY BIT(15)
73 #define PLLE_MISC_SETUP_EX_SHIFT 2
74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
76 PLLE_MISC_SETUP_EX_MASK)
77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
78
79 #define PLLE_SS_CTRL 0x68
80 #define PLLE_SS_DISABLE (7 << 10)
81
82 #define PLLE_AUX_PLLP_SEL BIT(2)
83 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
84 #define PLLE_AUX_SEQ_ENABLE BIT(24)
85 #define PLLE_AUX_PLLRE_SEL BIT(28)
86
87 #define PLLE_MISC_PLLE_PTS BIT(8)
88 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
89 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
90 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
91 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
92 #define PLLE_MISC_VREG_CTRL_SHIFT 2
93 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
94
95 #define PLLCX_MISC_STROBE BIT(31)
96 #define PLLCX_MISC_RESET BIT(30)
97 #define PLLCX_MISC_SDM_DIV_SHIFT 28
98 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
99 #define PLLCX_MISC_FILT_DIV_SHIFT 26
100 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
101 #define PLLCX_MISC_ALPHA_SHIFT 18
102 #define PLLCX_MISC_DIV_LOW_RANGE \
103 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
104 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
105 #define PLLCX_MISC_DIV_HIGH_RANGE \
106 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
107 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
108 #define PLLCX_MISC_COEF_LOW_RANGE \
109 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
110 #define PLLCX_MISC_KA_SHIFT 2
111 #define PLLCX_MISC_KB_SHIFT 9
112 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
113 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
114 PLLCX_MISC_DIV_LOW_RANGE | \
115 PLLCX_MISC_RESET)
116 #define PLLCX_MISC1_DEFAULT 0x000d2308
117 #define PLLCX_MISC2_DEFAULT 0x30211200
118 #define PLLCX_MISC3_DEFAULT 0x200
119
120 #define PMC_SATA_PWRGT 0x1ac
121 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
122 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
123
124 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
125 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
126 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
127 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
128
129 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
130 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
131 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
132 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
133
134 #define mask(w) ((1 << (w)) - 1)
135 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
136 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
137 #define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \
138 mask(p->params->div_nmp->divp_width))
139
140 #define divm_max(p) (divm_mask(p))
141 #define divn_max(p) (divn_mask(p))
142 #define divp_max(p) (1 << (divp_mask(p)))
143
144 static struct div_nmp default_nmp = {
145 .divn_shift = PLL_BASE_DIVN_SHIFT,
146 .divn_width = PLL_BASE_DIVN_WIDTH,
147 .divm_shift = PLL_BASE_DIVM_SHIFT,
148 .divm_width = PLL_BASE_DIVM_WIDTH,
149 .divp_shift = PLL_BASE_DIVP_SHIFT,
150 .divp_width = PLL_BASE_DIVP_WIDTH,
151 };
152
153 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
154 {
155 u32 val;
156
157 if (!(pll->flags & TEGRA_PLL_USE_LOCK))
158 return;
159
160 if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
161 return;
162
163 val = pll_readl_misc(pll);
164 val |= BIT(pll->params->lock_enable_bit_idx);
165 pll_writel_misc(val, pll);
166 }
167
168 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
169 {
170 int i;
171 u32 val, lock_mask;
172 void __iomem *lock_addr;
173
174 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
175 udelay(pll->params->lock_delay);
176 return 0;
177 }
178
179 lock_addr = pll->clk_base;
180 if (pll->flags & TEGRA_PLL_LOCK_MISC)
181 lock_addr += pll->params->misc_reg;
182 else
183 lock_addr += pll->params->base_reg;
184
185 lock_mask = pll->params->lock_mask;
186
187 for (i = 0; i < pll->params->lock_delay; i++) {
188 val = readl_relaxed(lock_addr);
189 if ((val & lock_mask) == lock_mask) {
190 udelay(PLL_POST_LOCK_DELAY);
191 return 0;
192 }
193 udelay(2); /* timeout = 2 * lock time */
194 }
195
196 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
197 __clk_get_name(pll->hw.clk));
198
199 return -1;
200 }
201
202 static int clk_pll_is_enabled(struct clk_hw *hw)
203 {
204 struct tegra_clk_pll *pll = to_clk_pll(hw);
205 u32 val;
206
207 if (pll->flags & TEGRA_PLLM) {
208 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
209 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
210 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
211 }
212
213 val = pll_readl_base(pll);
214
215 return val & PLL_BASE_ENABLE ? 1 : 0;
216 }
217
218 static void _clk_pll_enable(struct clk_hw *hw)
219 {
220 struct tegra_clk_pll *pll = to_clk_pll(hw);
221 u32 val;
222
223 clk_pll_enable_lock(pll);
224
225 val = pll_readl_base(pll);
226 if (pll->flags & TEGRA_PLL_BYPASS)
227 val &= ~PLL_BASE_BYPASS;
228 val |= PLL_BASE_ENABLE;
229 pll_writel_base(val, pll);
230
231 if (pll->flags & TEGRA_PLLM) {
232 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
233 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
234 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
235 }
236 }
237
238 static void _clk_pll_disable(struct clk_hw *hw)
239 {
240 struct tegra_clk_pll *pll = to_clk_pll(hw);
241 u32 val;
242
243 val = pll_readl_base(pll);
244 if (pll->flags & TEGRA_PLL_BYPASS)
245 val &= ~PLL_BASE_BYPASS;
246 val &= ~PLL_BASE_ENABLE;
247 pll_writel_base(val, pll);
248
249 if (pll->flags & TEGRA_PLLM) {
250 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
251 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
252 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
253 }
254 }
255
256 static int clk_pll_enable(struct clk_hw *hw)
257 {
258 struct tegra_clk_pll *pll = to_clk_pll(hw);
259 unsigned long flags = 0;
260 int ret;
261
262 if (pll->lock)
263 spin_lock_irqsave(pll->lock, flags);
264
265 _clk_pll_enable(hw);
266
267 ret = clk_pll_wait_for_lock(pll);
268
269 if (pll->lock)
270 spin_unlock_irqrestore(pll->lock, flags);
271
272 return ret;
273 }
274
275 static void clk_pll_disable(struct clk_hw *hw)
276 {
277 struct tegra_clk_pll *pll = to_clk_pll(hw);
278 unsigned long flags = 0;
279
280 if (pll->lock)
281 spin_lock_irqsave(pll->lock, flags);
282
283 _clk_pll_disable(hw);
284
285 if (pll->lock)
286 spin_unlock_irqrestore(pll->lock, flags);
287 }
288
289 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
290 {
291 struct tegra_clk_pll *pll = to_clk_pll(hw);
292 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
293
294 if (p_tohw) {
295 while (p_tohw->pdiv) {
296 if (p_div <= p_tohw->pdiv)
297 return p_tohw->hw_val;
298 p_tohw++;
299 }
300 return -EINVAL;
301 }
302 return -EINVAL;
303 }
304
305 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
306 {
307 struct tegra_clk_pll *pll = to_clk_pll(hw);
308 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
309
310 if (p_tohw) {
311 while (p_tohw->pdiv) {
312 if (p_div_hw == p_tohw->hw_val)
313 return p_tohw->pdiv;
314 p_tohw++;
315 }
316 return -EINVAL;
317 }
318
319 return 1 << p_div_hw;
320 }
321
322 static int _get_table_rate(struct clk_hw *hw,
323 struct tegra_clk_pll_freq_table *cfg,
324 unsigned long rate, unsigned long parent_rate)
325 {
326 struct tegra_clk_pll *pll = to_clk_pll(hw);
327 struct tegra_clk_pll_freq_table *sel;
328
329 for (sel = pll->freq_table; sel->input_rate != 0; sel++)
330 if (sel->input_rate == parent_rate &&
331 sel->output_rate == rate)
332 break;
333
334 if (sel->input_rate == 0)
335 return -EINVAL;
336
337 cfg->input_rate = sel->input_rate;
338 cfg->output_rate = sel->output_rate;
339 cfg->m = sel->m;
340 cfg->n = sel->n;
341 cfg->p = sel->p;
342 cfg->cpcon = sel->cpcon;
343
344 return 0;
345 }
346
347 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
348 unsigned long rate, unsigned long parent_rate)
349 {
350 struct tegra_clk_pll *pll = to_clk_pll(hw);
351 unsigned long cfreq;
352 u32 p_div = 0;
353 int ret;
354
355 switch (parent_rate) {
356 case 12000000:
357 case 26000000:
358 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
359 break;
360 case 13000000:
361 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
362 break;
363 case 16800000:
364 case 19200000:
365 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
366 break;
367 case 9600000:
368 case 28800000:
369 /*
370 * PLL_P_OUT1 rate is not listed in PLLA table
371 */
372 cfreq = parent_rate/(parent_rate/1000000);
373 break;
374 default:
375 pr_err("%s Unexpected reference rate %lu\n",
376 __func__, parent_rate);
377 BUG();
378 }
379
380 /* Raise VCO to guarantee 0.5% accuracy */
381 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
382 cfg->output_rate <<= 1)
383 p_div++;
384
385 cfg->m = parent_rate / cfreq;
386 cfg->n = cfg->output_rate / cfreq;
387 cfg->cpcon = OUT_OF_TABLE_CPCON;
388
389 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
390 (1 << p_div) > divp_max(pll)
391 || cfg->output_rate > pll->params->vco_max) {
392 pr_err("%s: Failed to set %s rate %lu\n",
393 __func__, __clk_get_name(hw->clk), rate);
394 WARN_ON(1);
395 return -EINVAL;
396 }
397
398 if (pll->params->pdiv_tohw) {
399 ret = _p_div_to_hw(hw, 1 << p_div);
400 if (ret < 0)
401 return ret;
402 else
403 cfg->p = ret;
404 } else
405 cfg->p = p_div;
406
407 return 0;
408 }
409
410 static void _update_pll_mnp(struct tegra_clk_pll *pll,
411 struct tegra_clk_pll_freq_table *cfg)
412 {
413 u32 val;
414 struct tegra_clk_pll_params *params = pll->params;
415 struct div_nmp *div_nmp = params->div_nmp;
416
417 if ((pll->flags & TEGRA_PLLM) &&
418 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
419 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
420 val = pll_override_readl(params->pmc_divp_reg, pll);
421 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
422 val |= cfg->p << div_nmp->override_divp_shift;
423 pll_override_writel(val, params->pmc_divp_reg, pll);
424
425 val = pll_override_readl(params->pmc_divnm_reg, pll);
426 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
427 ~(divn_mask(pll) << div_nmp->override_divn_shift);
428 val |= (cfg->m << div_nmp->override_divm_shift) |
429 (cfg->n << div_nmp->override_divn_shift);
430 pll_override_writel(val, params->pmc_divnm_reg, pll);
431 } else {
432 val = pll_readl_base(pll);
433
434 val &= ~((divm_mask(pll) << div_nmp->divm_shift) |
435 (divn_mask(pll) << div_nmp->divn_shift) |
436 (divp_mask(pll) << div_nmp->divp_shift));
437
438 val |= ((cfg->m << div_nmp->divm_shift) |
439 (cfg->n << div_nmp->divn_shift) |
440 (cfg->p << div_nmp->divp_shift));
441
442 pll_writel_base(val, pll);
443 }
444 }
445
446 static void _get_pll_mnp(struct tegra_clk_pll *pll,
447 struct tegra_clk_pll_freq_table *cfg)
448 {
449 u32 val;
450 struct tegra_clk_pll_params *params = pll->params;
451 struct div_nmp *div_nmp = params->div_nmp;
452
453 if ((pll->flags & TEGRA_PLLM) &&
454 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
455 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
456 val = pll_override_readl(params->pmc_divp_reg, pll);
457 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
458
459 val = pll_override_readl(params->pmc_divnm_reg, pll);
460 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
461 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
462 } else {
463 val = pll_readl_base(pll);
464
465 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
466 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
467 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
468 }
469 }
470
471 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
472 struct tegra_clk_pll_freq_table *cfg,
473 unsigned long rate)
474 {
475 u32 val;
476
477 val = pll_readl_misc(pll);
478
479 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
480 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
481
482 if (pll->flags & TEGRA_PLL_SET_LFCON) {
483 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
484 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
485 val |= 1 << PLL_MISC_LFCON_SHIFT;
486 } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
487 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
488 if (rate >= (pll->params->vco_max >> 1))
489 val |= 1 << PLL_MISC_DCCON_SHIFT;
490 }
491
492 pll_writel_misc(val, pll);
493 }
494
495 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
496 unsigned long rate)
497 {
498 struct tegra_clk_pll *pll = to_clk_pll(hw);
499 int state, ret = 0;
500
501 state = clk_pll_is_enabled(hw);
502
503 if (state)
504 _clk_pll_disable(hw);
505
506 _update_pll_mnp(pll, cfg);
507
508 if (pll->flags & TEGRA_PLL_HAS_CPCON)
509 _update_pll_cpcon(pll, cfg, rate);
510
511 if (state) {
512 _clk_pll_enable(hw);
513 ret = clk_pll_wait_for_lock(pll);
514 }
515
516 return ret;
517 }
518
519 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
520 unsigned long parent_rate)
521 {
522 struct tegra_clk_pll *pll = to_clk_pll(hw);
523 struct tegra_clk_pll_freq_table cfg, old_cfg;
524 unsigned long flags = 0;
525 int ret = 0;
526
527 if (pll->flags & TEGRA_PLL_FIXED) {
528 if (rate != pll->fixed_rate) {
529 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
530 __func__, __clk_get_name(hw->clk),
531 pll->fixed_rate, rate);
532 return -EINVAL;
533 }
534 return 0;
535 }
536
537 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
538 _calc_rate(hw, &cfg, rate, parent_rate)) {
539 WARN_ON(1);
540 return -EINVAL;
541 }
542 if (pll->lock)
543 spin_lock_irqsave(pll->lock, flags);
544
545 _get_pll_mnp(pll, &old_cfg);
546
547 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
548 ret = _program_pll(hw, &cfg, rate);
549
550 if (pll->lock)
551 spin_unlock_irqrestore(pll->lock, flags);
552
553 return ret;
554 }
555
556 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
557 unsigned long *prate)
558 {
559 struct tegra_clk_pll *pll = to_clk_pll(hw);
560 struct tegra_clk_pll_freq_table cfg;
561
562 if (pll->flags & TEGRA_PLL_FIXED)
563 return pll->fixed_rate;
564
565 /* PLLM is used for memory; we do not change rate */
566 if (pll->flags & TEGRA_PLLM)
567 return __clk_get_rate(hw->clk);
568
569 if (_get_table_rate(hw, &cfg, rate, *prate) &&
570 _calc_rate(hw, &cfg, rate, *prate)) {
571 WARN_ON(1);
572 return -EINVAL;
573 }
574
575 return cfg.output_rate;
576 }
577
578 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
579 unsigned long parent_rate)
580 {
581 struct tegra_clk_pll *pll = to_clk_pll(hw);
582 struct tegra_clk_pll_freq_table cfg;
583 u32 val;
584 u64 rate = parent_rate;
585 int pdiv;
586
587 val = pll_readl_base(pll);
588
589 if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
590 return parent_rate;
591
592 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
593 struct tegra_clk_pll_freq_table sel;
594 if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) {
595 pr_err("Clock %s has unknown fixed frequency\n",
596 __clk_get_name(hw->clk));
597 BUG();
598 }
599 return pll->fixed_rate;
600 }
601
602 _get_pll_mnp(pll, &cfg);
603
604 pdiv = _hw_to_p_div(hw, cfg.p);
605 if (pdiv < 0) {
606 WARN_ON(1);
607 pdiv = 1;
608 }
609
610 cfg.m *= pdiv;
611
612 rate *= cfg.n;
613 do_div(rate, cfg.m);
614
615 return rate;
616 }
617
618 static int clk_plle_training(struct tegra_clk_pll *pll)
619 {
620 u32 val;
621 unsigned long timeout;
622
623 if (!pll->pmc)
624 return -ENOSYS;
625
626 /*
627 * PLLE is already disabled, and setup cleared;
628 * create falling edge on PLLE IDDQ input.
629 */
630 val = readl(pll->pmc + PMC_SATA_PWRGT);
631 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
632 writel(val, pll->pmc + PMC_SATA_PWRGT);
633
634 val = readl(pll->pmc + PMC_SATA_PWRGT);
635 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
636 writel(val, pll->pmc + PMC_SATA_PWRGT);
637
638 val = readl(pll->pmc + PMC_SATA_PWRGT);
639 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
640 writel(val, pll->pmc + PMC_SATA_PWRGT);
641
642 val = pll_readl_misc(pll);
643
644 timeout = jiffies + msecs_to_jiffies(100);
645 while (1) {
646 val = pll_readl_misc(pll);
647 if (val & PLLE_MISC_READY)
648 break;
649 if (time_after(jiffies, timeout)) {
650 pr_err("%s: timeout waiting for PLLE\n", __func__);
651 return -EBUSY;
652 }
653 udelay(300);
654 }
655
656 return 0;
657 }
658
659 static int clk_plle_enable(struct clk_hw *hw)
660 {
661 struct tegra_clk_pll *pll = to_clk_pll(hw);
662 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
663 struct tegra_clk_pll_freq_table sel;
664 u32 val;
665 int err;
666
667 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
668 return -EINVAL;
669
670 clk_pll_disable(hw);
671
672 val = pll_readl_misc(pll);
673 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
674 pll_writel_misc(val, pll);
675
676 val = pll_readl_misc(pll);
677 if (!(val & PLLE_MISC_READY)) {
678 err = clk_plle_training(pll);
679 if (err)
680 return err;
681 }
682
683 if (pll->flags & TEGRA_PLLE_CONFIGURE) {
684 /* configure dividers */
685 val = pll_readl_base(pll);
686 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
687 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
688 val |= sel.m << pll->params->div_nmp->divm_shift;
689 val |= sel.n << pll->params->div_nmp->divn_shift;
690 val |= sel.p << pll->params->div_nmp->divp_shift;
691 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
692 pll_writel_base(val, pll);
693 }
694
695 val = pll_readl_misc(pll);
696 val |= PLLE_MISC_SETUP_VALUE;
697 val |= PLLE_MISC_LOCK_ENABLE;
698 pll_writel_misc(val, pll);
699
700 val = readl(pll->clk_base + PLLE_SS_CTRL);
701 val |= PLLE_SS_DISABLE;
702 writel(val, pll->clk_base + PLLE_SS_CTRL);
703
704 val |= pll_readl_base(pll);
705 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
706 pll_writel_base(val, pll);
707
708 clk_pll_wait_for_lock(pll);
709
710 return 0;
711 }
712
713 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
714 unsigned long parent_rate)
715 {
716 struct tegra_clk_pll *pll = to_clk_pll(hw);
717 u32 val = pll_readl_base(pll);
718 u32 divn = 0, divm = 0, divp = 0;
719 u64 rate = parent_rate;
720
721 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
722 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
723 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
724 divm *= divp;
725
726 rate *= divn;
727 do_div(rate, divm);
728 return rate;
729 }
730
731 const struct clk_ops tegra_clk_pll_ops = {
732 .is_enabled = clk_pll_is_enabled,
733 .enable = clk_pll_enable,
734 .disable = clk_pll_disable,
735 .recalc_rate = clk_pll_recalc_rate,
736 .round_rate = clk_pll_round_rate,
737 .set_rate = clk_pll_set_rate,
738 };
739
740 const struct clk_ops tegra_clk_plle_ops = {
741 .recalc_rate = clk_plle_recalc_rate,
742 .is_enabled = clk_pll_is_enabled,
743 .disable = clk_pll_disable,
744 .enable = clk_plle_enable,
745 };
746
747 #ifdef CONFIG_ARCH_TEGRA_114_SOC
748
749 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
750 unsigned long parent_rate)
751 {
752 if (parent_rate > pll_params->cf_max)
753 return 2;
754 else
755 return 1;
756 }
757
758 static int clk_pll_iddq_enable(struct clk_hw *hw)
759 {
760 struct tegra_clk_pll *pll = to_clk_pll(hw);
761 unsigned long flags = 0;
762
763 u32 val;
764 int ret;
765
766 if (pll->lock)
767 spin_lock_irqsave(pll->lock, flags);
768
769 val = pll_readl(pll->params->iddq_reg, pll);
770 val &= ~BIT(pll->params->iddq_bit_idx);
771 pll_writel(val, pll->params->iddq_reg, pll);
772 udelay(2);
773
774 _clk_pll_enable(hw);
775
776 ret = clk_pll_wait_for_lock(pll);
777
778 if (pll->lock)
779 spin_unlock_irqrestore(pll->lock, flags);
780
781 return 0;
782 }
783
784 static void clk_pll_iddq_disable(struct clk_hw *hw)
785 {
786 struct tegra_clk_pll *pll = to_clk_pll(hw);
787 unsigned long flags = 0;
788 u32 val;
789
790 if (pll->lock)
791 spin_lock_irqsave(pll->lock, flags);
792
793 _clk_pll_disable(hw);
794
795 val = pll_readl(pll->params->iddq_reg, pll);
796 val |= BIT(pll->params->iddq_bit_idx);
797 pll_writel(val, pll->params->iddq_reg, pll);
798 udelay(2);
799
800 if (pll->lock)
801 spin_unlock_irqrestore(pll->lock, flags);
802 }
803
804 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
805 struct tegra_clk_pll_freq_table *cfg,
806 unsigned long rate, unsigned long parent_rate)
807 {
808 struct tegra_clk_pll *pll = to_clk_pll(hw);
809 unsigned int p;
810 int p_div;
811
812 if (!rate)
813 return -EINVAL;
814
815 p = DIV_ROUND_UP(pll->params->vco_min, rate);
816 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
817 cfg->output_rate = rate * p;
818 cfg->n = cfg->output_rate * cfg->m / parent_rate;
819
820 p_div = _p_div_to_hw(hw, p);
821 if (p_div < 0)
822 return p_div;
823 else
824 cfg->p = p_div;
825
826 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
827 return -EINVAL;
828
829 return 0;
830 }
831
832 static int _pll_ramp_calc_pll(struct clk_hw *hw,
833 struct tegra_clk_pll_freq_table *cfg,
834 unsigned long rate, unsigned long parent_rate)
835 {
836 struct tegra_clk_pll *pll = to_clk_pll(hw);
837 int err = 0, p_div;
838
839 err = _get_table_rate(hw, cfg, rate, parent_rate);
840 if (err < 0)
841 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
842 else {
843 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
844 WARN_ON(1);
845 err = -EINVAL;
846 goto out;
847 }
848 p_div = _p_div_to_hw(hw, cfg->p);
849 if (p_div < 0)
850 return p_div;
851 else
852 cfg->p = p_div;
853 }
854
855 if (cfg->p > pll->params->max_p)
856 err = -EINVAL;
857
858 out:
859 return err;
860 }
861
862 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
863 unsigned long parent_rate)
864 {
865 struct tegra_clk_pll *pll = to_clk_pll(hw);
866 struct tegra_clk_pll_freq_table cfg, old_cfg;
867 unsigned long flags = 0;
868 int ret = 0;
869
870 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
871 if (ret < 0)
872 return ret;
873
874 if (pll->lock)
875 spin_lock_irqsave(pll->lock, flags);
876
877 _get_pll_mnp(pll, &old_cfg);
878
879 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
880 ret = _program_pll(hw, &cfg, rate);
881
882 if (pll->lock)
883 spin_unlock_irqrestore(pll->lock, flags);
884
885 return ret;
886 }
887
888 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
889 unsigned long *prate)
890 {
891 struct tegra_clk_pll_freq_table cfg;
892 int ret = 0, p_div;
893 u64 output_rate = *prate;
894
895 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
896 if (ret < 0)
897 return ret;
898
899 p_div = _hw_to_p_div(hw, cfg.p);
900 if (p_div < 0)
901 return p_div;
902
903 output_rate *= cfg.n;
904 do_div(output_rate, cfg.m * p_div);
905
906 return output_rate;
907 }
908
909 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
910 unsigned long parent_rate)
911 {
912 struct tegra_clk_pll_freq_table cfg;
913 struct tegra_clk_pll *pll = to_clk_pll(hw);
914 unsigned long flags = 0;
915 int state, ret = 0;
916
917 if (pll->lock)
918 spin_lock_irqsave(pll->lock, flags);
919
920 state = clk_pll_is_enabled(hw);
921 if (state) {
922 if (rate != clk_get_rate(hw->clk)) {
923 pr_err("%s: Cannot change active PLLM\n", __func__);
924 ret = -EINVAL;
925 goto out;
926 }
927 goto out;
928 }
929
930 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
931 if (ret < 0)
932 goto out;
933
934 _update_pll_mnp(pll, &cfg);
935
936 out:
937 if (pll->lock)
938 spin_unlock_irqrestore(pll->lock, flags);
939
940 return ret;
941 }
942
943 static void _pllcx_strobe(struct tegra_clk_pll *pll)
944 {
945 u32 val;
946
947 val = pll_readl_misc(pll);
948 val |= PLLCX_MISC_STROBE;
949 pll_writel_misc(val, pll);
950 udelay(2);
951
952 val &= ~PLLCX_MISC_STROBE;
953 pll_writel_misc(val, pll);
954 }
955
956 static int clk_pllc_enable(struct clk_hw *hw)
957 {
958 struct tegra_clk_pll *pll = to_clk_pll(hw);
959 u32 val;
960 int ret = 0;
961 unsigned long flags = 0;
962
963 if (pll->lock)
964 spin_lock_irqsave(pll->lock, flags);
965
966 _clk_pll_enable(hw);
967 udelay(2);
968
969 val = pll_readl_misc(pll);
970 val &= ~PLLCX_MISC_RESET;
971 pll_writel_misc(val, pll);
972 udelay(2);
973
974 _pllcx_strobe(pll);
975
976 ret = clk_pll_wait_for_lock(pll);
977
978 if (pll->lock)
979 spin_unlock_irqrestore(pll->lock, flags);
980
981 return ret;
982 }
983
984 static void _clk_pllc_disable(struct clk_hw *hw)
985 {
986 struct tegra_clk_pll *pll = to_clk_pll(hw);
987 u32 val;
988
989 _clk_pll_disable(hw);
990
991 val = pll_readl_misc(pll);
992 val |= PLLCX_MISC_RESET;
993 pll_writel_misc(val, pll);
994 udelay(2);
995 }
996
997 static void clk_pllc_disable(struct clk_hw *hw)
998 {
999 struct tegra_clk_pll *pll = to_clk_pll(hw);
1000 unsigned long flags = 0;
1001
1002 if (pll->lock)
1003 spin_lock_irqsave(pll->lock, flags);
1004
1005 _clk_pllc_disable(hw);
1006
1007 if (pll->lock)
1008 spin_unlock_irqrestore(pll->lock, flags);
1009 }
1010
1011 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1012 unsigned long input_rate, u32 n)
1013 {
1014 u32 val, n_threshold;
1015
1016 switch (input_rate) {
1017 case 12000000:
1018 n_threshold = 70;
1019 break;
1020 case 13000000:
1021 case 26000000:
1022 n_threshold = 71;
1023 break;
1024 case 16800000:
1025 n_threshold = 55;
1026 break;
1027 case 19200000:
1028 n_threshold = 48;
1029 break;
1030 default:
1031 pr_err("%s: Unexpected reference rate %lu\n",
1032 __func__, input_rate);
1033 return -EINVAL;
1034 }
1035
1036 val = pll_readl_misc(pll);
1037 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1038 val |= n <= n_threshold ?
1039 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1040 pll_writel_misc(val, pll);
1041
1042 return 0;
1043 }
1044
1045 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1046 unsigned long parent_rate)
1047 {
1048 struct tegra_clk_pll_freq_table cfg, old_cfg;
1049 struct tegra_clk_pll *pll = to_clk_pll(hw);
1050 unsigned long flags = 0;
1051 int state, ret = 0;
1052
1053 if (pll->lock)
1054 spin_lock_irqsave(pll->lock, flags);
1055
1056 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1057 if (ret < 0)
1058 goto out;
1059
1060 _get_pll_mnp(pll, &old_cfg);
1061
1062 if (cfg.m != old_cfg.m) {
1063 WARN_ON(1);
1064 goto out;
1065 }
1066
1067 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1068 goto out;
1069
1070 state = clk_pll_is_enabled(hw);
1071 if (state)
1072 _clk_pllc_disable(hw);
1073
1074 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1075 if (ret < 0)
1076 goto out;
1077
1078 _update_pll_mnp(pll, &cfg);
1079
1080 if (state)
1081 ret = clk_pllc_enable(hw);
1082
1083 out:
1084 if (pll->lock)
1085 spin_unlock_irqrestore(pll->lock, flags);
1086
1087 return ret;
1088 }
1089
1090 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1091 struct tegra_clk_pll_freq_table *cfg,
1092 unsigned long rate, unsigned long parent_rate)
1093 {
1094 u16 m, n;
1095 u64 output_rate = parent_rate;
1096
1097 m = _pll_fixed_mdiv(pll->params, parent_rate);
1098 n = rate * m / parent_rate;
1099
1100 output_rate *= n;
1101 do_div(output_rate, m);
1102
1103 if (cfg) {
1104 cfg->m = m;
1105 cfg->n = n;
1106 }
1107
1108 return output_rate;
1109 }
1110 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1111 unsigned long parent_rate)
1112 {
1113 struct tegra_clk_pll_freq_table cfg, old_cfg;
1114 struct tegra_clk_pll *pll = to_clk_pll(hw);
1115 unsigned long flags = 0;
1116 int state, ret = 0;
1117
1118 if (pll->lock)
1119 spin_lock_irqsave(pll->lock, flags);
1120
1121 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1122 _get_pll_mnp(pll, &old_cfg);
1123 cfg.p = old_cfg.p;
1124
1125 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1126 state = clk_pll_is_enabled(hw);
1127 if (state)
1128 _clk_pll_disable(hw);
1129
1130 _update_pll_mnp(pll, &cfg);
1131
1132 if (state) {
1133 _clk_pll_enable(hw);
1134 ret = clk_pll_wait_for_lock(pll);
1135 }
1136 }
1137
1138 if (pll->lock)
1139 spin_unlock_irqrestore(pll->lock, flags);
1140
1141 return ret;
1142 }
1143
1144 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1145 unsigned long parent_rate)
1146 {
1147 struct tegra_clk_pll_freq_table cfg;
1148 struct tegra_clk_pll *pll = to_clk_pll(hw);
1149 u64 rate = parent_rate;
1150
1151 _get_pll_mnp(pll, &cfg);
1152
1153 rate *= cfg.n;
1154 do_div(rate, cfg.m);
1155
1156 return rate;
1157 }
1158
1159 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1160 unsigned long *prate)
1161 {
1162 struct tegra_clk_pll *pll = to_clk_pll(hw);
1163
1164 return _pllre_calc_rate(pll, NULL, rate, *prate);
1165 }
1166
1167 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1168 {
1169 struct tegra_clk_pll *pll = to_clk_pll(hw);
1170 struct tegra_clk_pll_freq_table sel;
1171 u32 val;
1172 int ret;
1173 unsigned long flags = 0;
1174 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1175
1176 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
1177 return -EINVAL;
1178
1179 if (pll->lock)
1180 spin_lock_irqsave(pll->lock, flags);
1181
1182 val = pll_readl_base(pll);
1183 val &= ~BIT(29); /* Disable lock override */
1184 pll_writel_base(val, pll);
1185
1186 val = pll_readl(pll->params->aux_reg, pll);
1187 val |= PLLE_AUX_ENABLE_SWCTL;
1188 val &= ~PLLE_AUX_SEQ_ENABLE;
1189 pll_writel(val, pll->params->aux_reg, pll);
1190 udelay(1);
1191
1192 val = pll_readl_misc(pll);
1193 val |= PLLE_MISC_LOCK_ENABLE;
1194 val |= PLLE_MISC_IDDQ_SW_CTRL;
1195 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1196 val |= PLLE_MISC_PLLE_PTS;
1197 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1198 pll_writel_misc(val, pll);
1199 udelay(5);
1200
1201 val = pll_readl(PLLE_SS_CTRL, pll);
1202 val |= PLLE_SS_DISABLE;
1203 pll_writel(val, PLLE_SS_CTRL, pll);
1204
1205 val = pll_readl_base(pll);
1206 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
1207 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
1208 val |= sel.m << pll->params->div_nmp->divm_shift;
1209 val |= sel.n << pll->params->div_nmp->divn_shift;
1210 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1211 pll_writel_base(val, pll);
1212 udelay(1);
1213
1214 _clk_pll_enable(hw);
1215 ret = clk_pll_wait_for_lock(pll);
1216
1217 if (ret < 0)
1218 goto out;
1219
1220 /* TODO: enable hw control of xusb brick pll */
1221
1222 out:
1223 if (pll->lock)
1224 spin_unlock_irqrestore(pll->lock, flags);
1225
1226 return ret;
1227 }
1228
1229 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1230 {
1231 struct tegra_clk_pll *pll = to_clk_pll(hw);
1232 unsigned long flags = 0;
1233 u32 val;
1234
1235 if (pll->lock)
1236 spin_lock_irqsave(pll->lock, flags);
1237
1238 _clk_pll_disable(hw);
1239
1240 val = pll_readl_misc(pll);
1241 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1242 pll_writel_misc(val, pll);
1243 udelay(1);
1244
1245 if (pll->lock)
1246 spin_unlock_irqrestore(pll->lock, flags);
1247 }
1248 #endif
1249
1250 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1251 void __iomem *pmc, unsigned long fixed_rate,
1252 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1253 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1254 {
1255 struct tegra_clk_pll *pll;
1256
1257 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1258 if (!pll)
1259 return ERR_PTR(-ENOMEM);
1260
1261 pll->clk_base = clk_base;
1262 pll->pmc = pmc;
1263
1264 pll->freq_table = freq_table;
1265 pll->params = pll_params;
1266 pll->fixed_rate = fixed_rate;
1267 pll->flags = pll_flags;
1268 pll->lock = lock;
1269
1270 if (!pll_params->div_nmp)
1271 pll_params->div_nmp = &default_nmp;
1272
1273 return pll;
1274 }
1275
1276 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1277 const char *name, const char *parent_name, unsigned long flags,
1278 const struct clk_ops *ops)
1279 {
1280 struct clk_init_data init;
1281
1282 init.name = name;
1283 init.ops = ops;
1284 init.flags = flags;
1285 init.parent_names = (parent_name ? &parent_name : NULL);
1286 init.num_parents = (parent_name ? 1 : 0);
1287
1288 /* Data in .init is copied by clk_register(), so stack variable OK */
1289 pll->hw.init = &init;
1290
1291 return clk_register(NULL, &pll->hw);
1292 }
1293
1294 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1295 void __iomem *clk_base, void __iomem *pmc,
1296 unsigned long flags, unsigned long fixed_rate,
1297 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1298 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1299 {
1300 struct tegra_clk_pll *pll;
1301 struct clk *clk;
1302
1303 pll_flags |= TEGRA_PLL_BYPASS;
1304 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1305 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1306 freq_table, lock);
1307 if (IS_ERR(pll))
1308 return ERR_CAST(pll);
1309
1310 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1311 &tegra_clk_pll_ops);
1312 if (IS_ERR(clk))
1313 kfree(pll);
1314
1315 return clk;
1316 }
1317
1318 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1319 void __iomem *clk_base, void __iomem *pmc,
1320 unsigned long flags, unsigned long fixed_rate,
1321 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1322 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1323 {
1324 struct tegra_clk_pll *pll;
1325 struct clk *clk;
1326
1327 pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1328 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1329 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1330 freq_table, lock);
1331 if (IS_ERR(pll))
1332 return ERR_CAST(pll);
1333
1334 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1335 &tegra_clk_plle_ops);
1336 if (IS_ERR(clk))
1337 kfree(pll);
1338
1339 return clk;
1340 }
1341
1342 #ifdef CONFIG_ARCH_TEGRA_114_SOC
1343 const struct clk_ops tegra_clk_pllxc_ops = {
1344 .is_enabled = clk_pll_is_enabled,
1345 .enable = clk_pll_iddq_enable,
1346 .disable = clk_pll_iddq_disable,
1347 .recalc_rate = clk_pll_recalc_rate,
1348 .round_rate = clk_pll_ramp_round_rate,
1349 .set_rate = clk_pllxc_set_rate,
1350 };
1351
1352 const struct clk_ops tegra_clk_pllm_ops = {
1353 .is_enabled = clk_pll_is_enabled,
1354 .enable = clk_pll_iddq_enable,
1355 .disable = clk_pll_iddq_disable,
1356 .recalc_rate = clk_pll_recalc_rate,
1357 .round_rate = clk_pll_ramp_round_rate,
1358 .set_rate = clk_pllm_set_rate,
1359 };
1360
1361 const struct clk_ops tegra_clk_pllc_ops = {
1362 .is_enabled = clk_pll_is_enabled,
1363 .enable = clk_pllc_enable,
1364 .disable = clk_pllc_disable,
1365 .recalc_rate = clk_pll_recalc_rate,
1366 .round_rate = clk_pll_ramp_round_rate,
1367 .set_rate = clk_pllc_set_rate,
1368 };
1369
1370 const struct clk_ops tegra_clk_pllre_ops = {
1371 .is_enabled = clk_pll_is_enabled,
1372 .enable = clk_pll_iddq_enable,
1373 .disable = clk_pll_iddq_disable,
1374 .recalc_rate = clk_pllre_recalc_rate,
1375 .round_rate = clk_pllre_round_rate,
1376 .set_rate = clk_pllre_set_rate,
1377 };
1378
1379 const struct clk_ops tegra_clk_plle_tegra114_ops = {
1380 .is_enabled = clk_pll_is_enabled,
1381 .enable = clk_plle_tegra114_enable,
1382 .disable = clk_plle_tegra114_disable,
1383 .recalc_rate = clk_pll_recalc_rate,
1384 };
1385
1386
1387 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1388 void __iomem *clk_base, void __iomem *pmc,
1389 unsigned long flags, unsigned long fixed_rate,
1390 struct tegra_clk_pll_params *pll_params,
1391 u32 pll_flags,
1392 struct tegra_clk_pll_freq_table *freq_table,
1393 spinlock_t *lock)
1394 {
1395 struct tegra_clk_pll *pll;
1396 struct clk *clk;
1397
1398 if (!pll_params->pdiv_tohw)
1399 return ERR_PTR(-EINVAL);
1400
1401 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1402 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1403 freq_table, lock);
1404 if (IS_ERR(pll))
1405 return ERR_CAST(pll);
1406
1407 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1408 &tegra_clk_pllxc_ops);
1409 if (IS_ERR(clk))
1410 kfree(pll);
1411
1412 return clk;
1413 }
1414
1415 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1416 void __iomem *clk_base, void __iomem *pmc,
1417 unsigned long flags, unsigned long fixed_rate,
1418 struct tegra_clk_pll_params *pll_params,
1419 u32 pll_flags,
1420 struct tegra_clk_pll_freq_table *freq_table,
1421 spinlock_t *lock, unsigned long parent_rate)
1422 {
1423 u32 val;
1424 struct tegra_clk_pll *pll;
1425 struct clk *clk;
1426
1427 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1428 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1429 freq_table, lock);
1430 if (IS_ERR(pll))
1431 return ERR_CAST(pll);
1432
1433 /* program minimum rate by default */
1434
1435 val = pll_readl_base(pll);
1436 if (val & PLL_BASE_ENABLE)
1437 WARN_ON(val & pll_params->iddq_bit_idx);
1438 else {
1439 int m;
1440
1441 m = _pll_fixed_mdiv(pll_params, parent_rate);
1442 val = m << PLL_BASE_DIVM_SHIFT;
1443 val |= (pll_params->vco_min / parent_rate)
1444 << PLL_BASE_DIVN_SHIFT;
1445 pll_writel_base(val, pll);
1446 }
1447
1448 /* disable lock override */
1449
1450 val = pll_readl_misc(pll);
1451 val &= ~BIT(29);
1452 pll_writel_misc(val, pll);
1453
1454 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1455 &tegra_clk_pllre_ops);
1456 if (IS_ERR(clk))
1457 kfree(pll);
1458
1459 return clk;
1460 }
1461
1462 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1463 void __iomem *clk_base, void __iomem *pmc,
1464 unsigned long flags, unsigned long fixed_rate,
1465 struct tegra_clk_pll_params *pll_params,
1466 u32 pll_flags,
1467 struct tegra_clk_pll_freq_table *freq_table,
1468 spinlock_t *lock)
1469 {
1470 struct tegra_clk_pll *pll;
1471 struct clk *clk;
1472
1473 if (!pll_params->pdiv_tohw)
1474 return ERR_PTR(-EINVAL);
1475
1476 pll_flags |= TEGRA_PLL_BYPASS;
1477 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1478 pll_flags |= TEGRA_PLLM;
1479 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1480 freq_table, lock);
1481 if (IS_ERR(pll))
1482 return ERR_CAST(pll);
1483
1484 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1485 &tegra_clk_pllm_ops);
1486 if (IS_ERR(clk))
1487 kfree(pll);
1488
1489 return clk;
1490 }
1491
1492 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1493 void __iomem *clk_base, void __iomem *pmc,
1494 unsigned long flags, unsigned long fixed_rate,
1495 struct tegra_clk_pll_params *pll_params,
1496 u32 pll_flags,
1497 struct tegra_clk_pll_freq_table *freq_table,
1498 spinlock_t *lock)
1499 {
1500 struct clk *parent, *clk;
1501 struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1502 struct tegra_clk_pll *pll;
1503 struct tegra_clk_pll_freq_table cfg;
1504 unsigned long parent_rate;
1505
1506 if (!p_tohw)
1507 return ERR_PTR(-EINVAL);
1508
1509 parent = __clk_lookup(parent_name);
1510 if (IS_ERR(parent)) {
1511 WARN(1, "parent clk %s of %s must be registered first\n",
1512 name, parent_name);
1513 return ERR_PTR(-EINVAL);
1514 }
1515
1516 pll_flags |= TEGRA_PLL_BYPASS;
1517 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1518 freq_table, lock);
1519 if (IS_ERR(pll))
1520 return ERR_CAST(pll);
1521
1522 parent_rate = __clk_get_rate(parent);
1523
1524 /*
1525 * Most of PLLC register fields are shadowed, and can not be read
1526 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1527 * Initialize PLL to default state: disabled, reset; shadow registers
1528 * loaded with default parameters; dividers are preset for half of
1529 * minimum VCO rate (the latter assured that shadowed divider settings
1530 * are within supported range).
1531 */
1532
1533 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1534 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1535
1536 while (p_tohw->pdiv) {
1537 if (p_tohw->pdiv == 2) {
1538 cfg.p = p_tohw->hw_val;
1539 break;
1540 }
1541 p_tohw++;
1542 }
1543
1544 if (!p_tohw->pdiv) {
1545 WARN_ON(1);
1546 return ERR_PTR(-EINVAL);
1547 }
1548
1549 pll_writel_base(0, pll);
1550 _update_pll_mnp(pll, &cfg);
1551
1552 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1553 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1554 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1555 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1556
1557 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1558
1559 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1560 &tegra_clk_pllc_ops);
1561 if (IS_ERR(clk))
1562 kfree(pll);
1563
1564 return clk;
1565 }
1566
1567 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1568 const char *parent_name,
1569 void __iomem *clk_base, unsigned long flags,
1570 unsigned long fixed_rate,
1571 struct tegra_clk_pll_params *pll_params,
1572 struct tegra_clk_pll_freq_table *freq_table,
1573 spinlock_t *lock)
1574 {
1575 struct tegra_clk_pll *pll;
1576 struct clk *clk;
1577 u32 val, val_aux;
1578
1579 pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params,
1580 TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock);
1581 if (IS_ERR(pll))
1582 return ERR_CAST(pll);
1583
1584 /* ensure parent is set to pll_re_vco */
1585
1586 val = pll_readl_base(pll);
1587 val_aux = pll_readl(pll_params->aux_reg, pll);
1588
1589 if (val & PLL_BASE_ENABLE) {
1590 if (!(val_aux & PLLE_AUX_PLLRE_SEL))
1591 WARN(1, "pll_e enabled with unsupported parent %s\n",
1592 (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
1593 } else {
1594 val_aux |= PLLE_AUX_PLLRE_SEL;
1595 pll_writel(val, pll_params->aux_reg, pll);
1596 }
1597
1598 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1599 &tegra_clk_plle_tegra114_ops);
1600 if (IS_ERR(clk))
1601 kfree(pll);
1602
1603 return clk;
1604 }
1605 #endif
Linux with added FPC-III support