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crypto: arm64/aes-ghash - yield NEON after every block of input
[linux/fpc-iii.git] / drivers / crypto / n2_core.c
blob80e9c842aad463d0ece3b48862c202564488f8ec
1 /* n2_core.c: Niagara2 Stream Processing Unit (SPU) crypto support.
2 *
3 * Copyright (C) 2010, 2011 David S. Miller <davem@davemloft.net>
4 */
5
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/cpumask.h>
13 #include <linux/slab.h>
14 #include <linux/interrupt.h>
15 #include <linux/crypto.h>
16 #include <crypto/md5.h>
17 #include <crypto/sha.h>
18 #include <crypto/aes.h>
19 #include <crypto/des.h>
20 #include <linux/mutex.h>
21 #include <linux/delay.h>
22 #include <linux/sched.h>
23
24 #include <crypto/internal/hash.h>
25 #include <crypto/scatterwalk.h>
26 #include <crypto/algapi.h>
27
28 #include <asm/hypervisor.h>
29 #include <asm/mdesc.h>
30
31 #include "n2_core.h"
32
33 #define DRV_MODULE_NAME "n2_crypto"
34 #define DRV_MODULE_VERSION "0.2"
35 #define DRV_MODULE_RELDATE "July 28, 2011"
36
37 static const char version[] =
38 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
39
40 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
41 MODULE_DESCRIPTION("Niagara2 Crypto driver");
42 MODULE_LICENSE("GPL");
43 MODULE_VERSION(DRV_MODULE_VERSION);
44
45 #define N2_CRA_PRIORITY 200
46
47 static DEFINE_MUTEX(spu_lock);
48
49 struct spu_queue {
50 cpumask_t sharing;
51 unsigned long qhandle;
52
53 spinlock_t lock;
54 u8 q_type;
55 void *q;
56 unsigned long head;
57 unsigned long tail;
58 struct list_head jobs;
59
60 unsigned long devino;
61
62 char irq_name[32];
63 unsigned int irq;
64
65 struct list_head list;
66 };
67
68 struct spu_qreg {
69 struct spu_queue *queue;
70 unsigned long type;
71 };
72
73 static struct spu_queue **cpu_to_cwq;
74 static struct spu_queue **cpu_to_mau;
75
76 static unsigned long spu_next_offset(struct spu_queue *q, unsigned long off)
77 {
78 if (q->q_type == HV_NCS_QTYPE_MAU) {
79 off += MAU_ENTRY_SIZE;
80 if (off == (MAU_ENTRY_SIZE * MAU_NUM_ENTRIES))
81 off = 0;
82 } else {
83 off += CWQ_ENTRY_SIZE;
84 if (off == (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES))
85 off = 0;
86 }
87 return off;
88 }
89
90 struct n2_request_common {
91 struct list_head entry;
92 unsigned int offset;
93 };
94 #define OFFSET_NOT_RUNNING (~(unsigned int)0)
95
96 /* An async job request records the final tail value it used in
97 * n2_request_common->offset, test to see if that offset is in
98 * the range old_head, new_head, inclusive.
99 */
100 static inline bool job_finished(struct spu_queue *q, unsigned int offset,
101 unsigned long old_head, unsigned long new_head)
102 {
103 if (old_head <= new_head) {
104 if (offset > old_head && offset <= new_head)
105 return true;
106 } else {
107 if (offset > old_head || offset <= new_head)
108 return true;
109 }
110 return false;
111 }
112
113 /* When the HEAD marker is unequal to the actual HEAD, we get
114 * a virtual device INO interrupt. We should process the
115 * completed CWQ entries and adjust the HEAD marker to clear
116 * the IRQ.
117 */
118 static irqreturn_t cwq_intr(int irq, void *dev_id)
119 {
120 unsigned long off, new_head, hv_ret;
121 struct spu_queue *q = dev_id;
122
123 pr_err("CPU[%d]: Got CWQ interrupt for qhdl[%lx]\n",
124 smp_processor_id(), q->qhandle);
125
126 spin_lock(&q->lock);
127
128 hv_ret = sun4v_ncs_gethead(q->qhandle, &new_head);
129
130 pr_err("CPU[%d]: CWQ gethead[%lx] hv_ret[%lu]\n",
131 smp_processor_id(), new_head, hv_ret);
132
133 for (off = q->head; off != new_head; off = spu_next_offset(q, off)) {
134 /* XXX ... XXX */
135 }
136
137 hv_ret = sun4v_ncs_sethead_marker(q->qhandle, new_head);
138 if (hv_ret == HV_EOK)
139 q->head = new_head;
140
141 spin_unlock(&q->lock);
142
143 return IRQ_HANDLED;
144 }
145
146 static irqreturn_t mau_intr(int irq, void *dev_id)
147 {
148 struct spu_queue *q = dev_id;
149 unsigned long head, hv_ret;
150
151 spin_lock(&q->lock);
152
153 pr_err("CPU[%d]: Got MAU interrupt for qhdl[%lx]\n",
154 smp_processor_id(), q->qhandle);
155
156 hv_ret = sun4v_ncs_gethead(q->qhandle, &head);
157
158 pr_err("CPU[%d]: MAU gethead[%lx] hv_ret[%lu]\n",
159 smp_processor_id(), head, hv_ret);
160
161 sun4v_ncs_sethead_marker(q->qhandle, head);
162
163 spin_unlock(&q->lock);
164
165 return IRQ_HANDLED;
166 }
167
168 static void *spu_queue_next(struct spu_queue *q, void *cur)
169 {
170 return q->q + spu_next_offset(q, cur - q->q);
171 }
172
173 static int spu_queue_num_free(struct spu_queue *q)
174 {
175 unsigned long head = q->head;
176 unsigned long tail = q->tail;
177 unsigned long end = (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES);
178 unsigned long diff;
179
180 if (head > tail)
181 diff = head - tail;
182 else
183 diff = (end - tail) + head;
184
185 return (diff / CWQ_ENTRY_SIZE) - 1;
186 }
187
188 static void *spu_queue_alloc(struct spu_queue *q, int num_entries)
189 {
190 int avail = spu_queue_num_free(q);
191
192 if (avail >= num_entries)
193 return q->q + q->tail;
194
195 return NULL;
196 }
197
198 static unsigned long spu_queue_submit(struct spu_queue *q, void *last)
199 {
200 unsigned long hv_ret, new_tail;
201
202 new_tail = spu_next_offset(q, last - q->q);
203
204 hv_ret = sun4v_ncs_settail(q->qhandle, new_tail);
205 if (hv_ret == HV_EOK)
206 q->tail = new_tail;
207 return hv_ret;
208 }
209
210 static u64 control_word_base(unsigned int len, unsigned int hmac_key_len,
211 int enc_type, int auth_type,
212 unsigned int hash_len,
213 bool sfas, bool sob, bool eob, bool encrypt,
214 int opcode)
215 {
216 u64 word = (len - 1) & CONTROL_LEN;
217
218 word |= ((u64) opcode << CONTROL_OPCODE_SHIFT);
219 word |= ((u64) enc_type << CONTROL_ENC_TYPE_SHIFT);
220 word |= ((u64) auth_type << CONTROL_AUTH_TYPE_SHIFT);
221 if (sfas)
222 word |= CONTROL_STORE_FINAL_AUTH_STATE;
223 if (sob)
224 word |= CONTROL_START_OF_BLOCK;
225 if (eob)
226 word |= CONTROL_END_OF_BLOCK;
227 if (encrypt)
228 word |= CONTROL_ENCRYPT;
229 if (hmac_key_len)
230 word |= ((u64) (hmac_key_len - 1)) << CONTROL_HMAC_KEY_LEN_SHIFT;
231 if (hash_len)
232 word |= ((u64) (hash_len - 1)) << CONTROL_HASH_LEN_SHIFT;
233
234 return word;
235 }
236
237 #if 0
238 static inline bool n2_should_run_async(struct spu_queue *qp, int this_len)
239 {
240 if (this_len >= 64 ||
241 qp->head != qp->tail)
242 return true;
243 return false;
244 }
245 #endif
246
247 struct n2_ahash_alg {
248 struct list_head entry;
249 const u8 *hash_zero;
250 const u32 *hash_init;
251 u8 hw_op_hashsz;
252 u8 digest_size;
253 u8 auth_type;
254 u8 hmac_type;
255 struct ahash_alg alg;
256 };
257
258 static inline struct n2_ahash_alg *n2_ahash_alg(struct crypto_tfm *tfm)
259 {
260 struct crypto_alg *alg = tfm->__crt_alg;
261 struct ahash_alg *ahash_alg;
262
263 ahash_alg = container_of(alg, struct ahash_alg, halg.base);
264
265 return container_of(ahash_alg, struct n2_ahash_alg, alg);
266 }
267
268 struct n2_hmac_alg {
269 const char *child_alg;
270 struct n2_ahash_alg derived;
271 };
272
273 static inline struct n2_hmac_alg *n2_hmac_alg(struct crypto_tfm *tfm)
274 {
275 struct crypto_alg *alg = tfm->__crt_alg;
276 struct ahash_alg *ahash_alg;
277
278 ahash_alg = container_of(alg, struct ahash_alg, halg.base);
279
280 return container_of(ahash_alg, struct n2_hmac_alg, derived.alg);
281 }
282
283 struct n2_hash_ctx {
284 struct crypto_ahash *fallback_tfm;
285 };
286
287 #define N2_HASH_KEY_MAX 32 /* HW limit for all HMAC requests */
288
289 struct n2_hmac_ctx {
290 struct n2_hash_ctx base;
291
292 struct crypto_shash *child_shash;
293
294 int hash_key_len;
295 unsigned char hash_key[N2_HASH_KEY_MAX];
296 };
297
298 struct n2_hash_req_ctx {
299 union {
300 struct md5_state md5;
301 struct sha1_state sha1;
302 struct sha256_state sha256;
303 } u;
304
305 struct ahash_request fallback_req;
306 };
307
308 static int n2_hash_async_init(struct ahash_request *req)
309 {
310 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
311 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
312 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
313
314 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
315 rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
316
317 return crypto_ahash_init(&rctx->fallback_req);
318 }
319
320 static int n2_hash_async_update(struct ahash_request *req)
321 {
322 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
323 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
324 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
325
326 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
327 rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
328 rctx->fallback_req.nbytes = req->nbytes;
329 rctx->fallback_req.src = req->src;
330
331 return crypto_ahash_update(&rctx->fallback_req);
332 }
333
334 static int n2_hash_async_final(struct ahash_request *req)
335 {
336 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
337 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
338 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
339
340 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
341 rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
342 rctx->fallback_req.result = req->result;
343
344 return crypto_ahash_final(&rctx->fallback_req);
345 }
346
347 static int n2_hash_async_finup(struct ahash_request *req)
348 {
349 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
350 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
351 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
352
353 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
354 rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
355 rctx->fallback_req.nbytes = req->nbytes;
356 rctx->fallback_req.src = req->src;
357 rctx->fallback_req.result = req->result;
358
359 return crypto_ahash_finup(&rctx->fallback_req);
360 }
361
362 static int n2_hash_async_noimport(struct ahash_request *req, const void *in)
363 {
364 return -ENOSYS;
365 }
366
367 static int n2_hash_async_noexport(struct ahash_request *req, void *out)
368 {
369 return -ENOSYS;
370 }
371
372 static int n2_hash_cra_init(struct crypto_tfm *tfm)
373 {
374 const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
375 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
376 struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
377 struct crypto_ahash *fallback_tfm;
378 int err;
379
380 fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
381 CRYPTO_ALG_NEED_FALLBACK);
382 if (IS_ERR(fallback_tfm)) {
383 pr_warning("Fallback driver '%s' could not be loaded!\n",
384 fallback_driver_name);
385 err = PTR_ERR(fallback_tfm);
386 goto out;
387 }
388
389 crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
390 crypto_ahash_reqsize(fallback_tfm)));
391
392 ctx->fallback_tfm = fallback_tfm;
393 return 0;
394
395 out:
396 return err;
397 }
398
399 static void n2_hash_cra_exit(struct crypto_tfm *tfm)
400 {
401 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
402 struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
403
404 crypto_free_ahash(ctx->fallback_tfm);
405 }
406
407 static int n2_hmac_cra_init(struct crypto_tfm *tfm)
408 {
409 const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
410 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
411 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
412 struct n2_hmac_alg *n2alg = n2_hmac_alg(tfm);
413 struct crypto_ahash *fallback_tfm;
414 struct crypto_shash *child_shash;
415 int err;
416
417 fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
418 CRYPTO_ALG_NEED_FALLBACK);
419 if (IS_ERR(fallback_tfm)) {
420 pr_warning("Fallback driver '%s' could not be loaded!\n",
421 fallback_driver_name);
422 err = PTR_ERR(fallback_tfm);
423 goto out;
424 }
425
426 child_shash = crypto_alloc_shash(n2alg->child_alg, 0, 0);
427 if (IS_ERR(child_shash)) {
428 pr_warning("Child shash '%s' could not be loaded!\n",
429 n2alg->child_alg);
430 err = PTR_ERR(child_shash);
431 goto out_free_fallback;
432 }
433
434 crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
435 crypto_ahash_reqsize(fallback_tfm)));
436
437 ctx->child_shash = child_shash;
438 ctx->base.fallback_tfm = fallback_tfm;
439 return 0;
440
441 out_free_fallback:
442 crypto_free_ahash(fallback_tfm);
443
444 out:
445 return err;
446 }
447
448 static void n2_hmac_cra_exit(struct crypto_tfm *tfm)
449 {
450 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
451 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
452
453 crypto_free_ahash(ctx->base.fallback_tfm);
454 crypto_free_shash(ctx->child_shash);
455 }
456
457 static int n2_hmac_async_setkey(struct crypto_ahash *tfm, const u8 *key,
458 unsigned int keylen)
459 {
460 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
461 struct crypto_shash *child_shash = ctx->child_shash;
462 struct crypto_ahash *fallback_tfm;
463 SHASH_DESC_ON_STACK(shash, child_shash);
464 int err, bs, ds;
465
466 fallback_tfm = ctx->base.fallback_tfm;
467 err = crypto_ahash_setkey(fallback_tfm, key, keylen);
468 if (err)
469 return err;
470
471 shash->tfm = child_shash;
472 shash->flags = crypto_ahash_get_flags(tfm) &
473 CRYPTO_TFM_REQ_MAY_SLEEP;
474
475 bs = crypto_shash_blocksize(child_shash);
476 ds = crypto_shash_digestsize(child_shash);
477 BUG_ON(ds > N2_HASH_KEY_MAX);
478 if (keylen > bs) {
479 err = crypto_shash_digest(shash, key, keylen,
480 ctx->hash_key);
481 if (err)
482 return err;
483 keylen = ds;
484 } else if (keylen <= N2_HASH_KEY_MAX)
485 memcpy(ctx->hash_key, key, keylen);
486
487 ctx->hash_key_len = keylen;
488
489 return err;
490 }
491
492 static unsigned long wait_for_tail(struct spu_queue *qp)
493 {
494 unsigned long head, hv_ret;
495
496 do {
497 hv_ret = sun4v_ncs_gethead(qp->qhandle, &head);
498 if (hv_ret != HV_EOK) {
499 pr_err("Hypervisor error on gethead\n");
500 break;
501 }
502 if (head == qp->tail) {
503 qp->head = head;
504 break;
505 }
506 } while (1);
507 return hv_ret;
508 }
509
510 static unsigned long submit_and_wait_for_tail(struct spu_queue *qp,
511 struct cwq_initial_entry *ent)
512 {
513 unsigned long hv_ret = spu_queue_submit(qp, ent);
514
515 if (hv_ret == HV_EOK)
516 hv_ret = wait_for_tail(qp);
517
518 return hv_ret;
519 }
520
521 static int n2_do_async_digest(struct ahash_request *req,
522 unsigned int auth_type, unsigned int digest_size,
523 unsigned int result_size, void *hash_loc,
524 unsigned long auth_key, unsigned int auth_key_len)
525 {
526 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
527 struct cwq_initial_entry *ent;
528 struct crypto_hash_walk walk;
529 struct spu_queue *qp;
530 unsigned long flags;
531 int err = -ENODEV;
532 int nbytes, cpu;
533
534 /* The total effective length of the operation may not
535 * exceed 2^16.
536 */
537 if (unlikely(req->nbytes > (1 << 16))) {
538 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
539 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
540
541 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
542 rctx->fallback_req.base.flags =
543 req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
544 rctx->fallback_req.nbytes = req->nbytes;
545 rctx->fallback_req.src = req->src;
546 rctx->fallback_req.result = req->result;
547
548 return crypto_ahash_digest(&rctx->fallback_req);
549 }
550
551 nbytes = crypto_hash_walk_first(req, &walk);
552
553 cpu = get_cpu();
554 qp = cpu_to_cwq[cpu];
555 if (!qp)
556 goto out;
557
558 spin_lock_irqsave(&qp->lock, flags);
559
560 /* XXX can do better, improve this later by doing a by-hand scatterlist
561 * XXX walk, etc.
562 */
563 ent = qp->q + qp->tail;
564
565 ent->control = control_word_base(nbytes, auth_key_len, 0,
566 auth_type, digest_size,
567 false, true, false, false,
568 OPCODE_INPLACE_BIT |
569 OPCODE_AUTH_MAC);
570 ent->src_addr = __pa(walk.data);
571 ent->auth_key_addr = auth_key;
572 ent->auth_iv_addr = __pa(hash_loc);
573 ent->final_auth_state_addr = 0UL;
574 ent->enc_key_addr = 0UL;
575 ent->enc_iv_addr = 0UL;
576 ent->dest_addr = __pa(hash_loc);
577
578 nbytes = crypto_hash_walk_done(&walk, 0);
579 while (nbytes > 0) {
580 ent = spu_queue_next(qp, ent);
581
582 ent->control = (nbytes - 1);
583 ent->src_addr = __pa(walk.data);
584 ent->auth_key_addr = 0UL;
585 ent->auth_iv_addr = 0UL;
586 ent->final_auth_state_addr = 0UL;
587 ent->enc_key_addr = 0UL;
588 ent->enc_iv_addr = 0UL;
589 ent->dest_addr = 0UL;
590
591 nbytes = crypto_hash_walk_done(&walk, 0);
592 }
593 ent->control |= CONTROL_END_OF_BLOCK;
594
595 if (submit_and_wait_for_tail(qp, ent) != HV_EOK)
596 err = -EINVAL;
597 else
598 err = 0;
599
600 spin_unlock_irqrestore(&qp->lock, flags);
601
602 if (!err)
603 memcpy(req->result, hash_loc, result_size);
604 out:
605 put_cpu();
606
607 return err;
608 }
609
610 static int n2_hash_async_digest(struct ahash_request *req)
611 {
612 struct n2_ahash_alg *n2alg = n2_ahash_alg(req->base.tfm);
613 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
614 int ds;
615
616 ds = n2alg->digest_size;
617 if (unlikely(req->nbytes == 0)) {
618 memcpy(req->result, n2alg->hash_zero, ds);
619 return 0;
620 }
621 memcpy(&rctx->u, n2alg->hash_init, n2alg->hw_op_hashsz);
622
623 return n2_do_async_digest(req, n2alg->auth_type,
624 n2alg->hw_op_hashsz, ds,
625 &rctx->u, 0UL, 0);
626 }
627
628 static int n2_hmac_async_digest(struct ahash_request *req)
629 {
630 struct n2_hmac_alg *n2alg = n2_hmac_alg(req->base.tfm);
631 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
632 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
633 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
634 int ds;
635
636 ds = n2alg->derived.digest_size;
637 if (unlikely(req->nbytes == 0) ||
638 unlikely(ctx->hash_key_len > N2_HASH_KEY_MAX)) {
639 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
640 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
641
642 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
643 rctx->fallback_req.base.flags =
644 req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
645 rctx->fallback_req.nbytes = req->nbytes;
646 rctx->fallback_req.src = req->src;
647 rctx->fallback_req.result = req->result;
648
649 return crypto_ahash_digest(&rctx->fallback_req);
650 }
651 memcpy(&rctx->u, n2alg->derived.hash_init,
652 n2alg->derived.hw_op_hashsz);
653
654 return n2_do_async_digest(req, n2alg->derived.hmac_type,
655 n2alg->derived.hw_op_hashsz, ds,
656 &rctx->u,
657 __pa(&ctx->hash_key),
658 ctx->hash_key_len);
659 }
660
661 struct n2_cipher_context {
662 int key_len;
663 int enc_type;
664 union {
665 u8 aes[AES_MAX_KEY_SIZE];
666 u8 des[DES_KEY_SIZE];
667 u8 des3[3 * DES_KEY_SIZE];
668 u8 arc4[258]; /* S-box, X, Y */
669 } key;
670 };
671
672 #define N2_CHUNK_ARR_LEN 16
673
674 struct n2_crypto_chunk {
675 struct list_head entry;
676 unsigned long iv_paddr : 44;
677 unsigned long arr_len : 20;
678 unsigned long dest_paddr;
679 unsigned long dest_final;
680 struct {
681 unsigned long src_paddr : 44;
682 unsigned long src_len : 20;
683 } arr[N2_CHUNK_ARR_LEN];
684 };
685
686 struct n2_request_context {
687 struct ablkcipher_walk walk;
688 struct list_head chunk_list;
689 struct n2_crypto_chunk chunk;
690 u8 temp_iv[16];
691 };
692
693 /* The SPU allows some level of flexibility for partial cipher blocks
694 * being specified in a descriptor.
695 *
696 * It merely requires that every descriptor's length field is at least
697 * as large as the cipher block size. This means that a cipher block
698 * can span at most 2 descriptors. However, this does not allow a
699 * partial block to span into the final descriptor as that would
700 * violate the rule (since every descriptor's length must be at lest
701 * the block size). So, for example, assuming an 8 byte block size:
702 *
703 * 0xe --> 0xa --> 0x8
704 *
705 * is a valid length sequence, whereas:
706 *
707 * 0xe --> 0xb --> 0x7
708 *
709 * is not a valid sequence.
710 */
711
712 struct n2_cipher_alg {
713 struct list_head entry;
714 u8 enc_type;
715 struct crypto_alg alg;
716 };
717
718 static inline struct n2_cipher_alg *n2_cipher_alg(struct crypto_tfm *tfm)
719 {
720 struct crypto_alg *alg = tfm->__crt_alg;
721
722 return container_of(alg, struct n2_cipher_alg, alg);
723 }
724
725 struct n2_cipher_request_context {
726 struct ablkcipher_walk walk;
727 };
728
729 static int n2_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
730 unsigned int keylen)
731 {
732 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
733 struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
734 struct n2_cipher_alg *n2alg = n2_cipher_alg(tfm);
735
736 ctx->enc_type = (n2alg->enc_type & ENC_TYPE_CHAINING_MASK);
737
738 switch (keylen) {
739 case AES_KEYSIZE_128:
740 ctx->enc_type |= ENC_TYPE_ALG_AES128;
741 break;
742 case AES_KEYSIZE_192:
743 ctx->enc_type |= ENC_TYPE_ALG_AES192;
744 break;
745 case AES_KEYSIZE_256:
746 ctx->enc_type |= ENC_TYPE_ALG_AES256;
747 break;
748 default:
749 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
750 return -EINVAL;
751 }
752
753 ctx->key_len = keylen;
754 memcpy(ctx->key.aes, key, keylen);
755 return 0;
756 }
757
758 static int n2_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
759 unsigned int keylen)
760 {
761 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
762 struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
763 struct n2_cipher_alg *n2alg = n2_cipher_alg(tfm);
764 u32 tmp[DES_EXPKEY_WORDS];
765 int err;
766
767 ctx->enc_type = n2alg->enc_type;
768
769 if (keylen != DES_KEY_SIZE) {
770 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
771 return -EINVAL;
772 }
773
774 err = des_ekey(tmp, key);
775 if (err == 0 && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
776 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
777 return -EINVAL;
778 }
779
780 ctx->key_len = keylen;
781 memcpy(ctx->key.des, key, keylen);
782 return 0;
783 }
784
785 static int n2_3des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
786 unsigned int keylen)
787 {
788 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
789 struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
790 struct n2_cipher_alg *n2alg = n2_cipher_alg(tfm);
791
792 ctx->enc_type = n2alg->enc_type;
793
794 if (keylen != (3 * DES_KEY_SIZE)) {
795 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
796 return -EINVAL;
797 }
798 ctx->key_len = keylen;
799 memcpy(ctx->key.des3, key, keylen);
800 return 0;
801 }
802
803 static int n2_arc4_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
804 unsigned int keylen)
805 {
806 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
807 struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
808 struct n2_cipher_alg *n2alg = n2_cipher_alg(tfm);
809 u8 *s = ctx->key.arc4;
810 u8 *x = s + 256;
811 u8 *y = x + 1;
812 int i, j, k;
813
814 ctx->enc_type = n2alg->enc_type;
815
816 j = k = 0;
817 *x = 0;
818 *y = 0;
819 for (i = 0; i < 256; i++)
820 s[i] = i;
821 for (i = 0; i < 256; i++) {
822 u8 a = s[i];
823 j = (j + key[k] + a) & 0xff;
824 s[i] = s[j];
825 s[j] = a;
826 if (++k >= keylen)
827 k = 0;
828 }
829
830 return 0;
831 }
832
833 static inline int cipher_descriptor_len(int nbytes, unsigned int block_size)
834 {
835 int this_len = nbytes;
836
837 this_len -= (nbytes & (block_size - 1));
838 return this_len > (1 << 16) ? (1 << 16) : this_len;
839 }
840
841 static int __n2_crypt_chunk(struct crypto_tfm *tfm, struct n2_crypto_chunk *cp,
842 struct spu_queue *qp, bool encrypt)
843 {
844 struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
845 struct cwq_initial_entry *ent;
846 bool in_place;
847 int i;
848
849 ent = spu_queue_alloc(qp, cp->arr_len);
850 if (!ent) {
851 pr_info("queue_alloc() of %d fails\n",
852 cp->arr_len);
853 return -EBUSY;
854 }
855
856 in_place = (cp->dest_paddr == cp->arr[0].src_paddr);
857
858 ent->control = control_word_base(cp->arr[0].src_len,
859 0, ctx->enc_type, 0, 0,
860 false, true, false, encrypt,
861 OPCODE_ENCRYPT |
862 (in_place ? OPCODE_INPLACE_BIT : 0));
863 ent->src_addr = cp->arr[0].src_paddr;
864 ent->auth_key_addr = 0UL;
865 ent->auth_iv_addr = 0UL;
866 ent->final_auth_state_addr = 0UL;
867 ent->enc_key_addr = __pa(&ctx->key);
868 ent->enc_iv_addr = cp->iv_paddr;
869 ent->dest_addr = (in_place ? 0UL : cp->dest_paddr);
870
871 for (i = 1; i < cp->arr_len; i++) {
872 ent = spu_queue_next(qp, ent);
873
874 ent->control = cp->arr[i].src_len - 1;
875 ent->src_addr = cp->arr[i].src_paddr;
876 ent->auth_key_addr = 0UL;
877 ent->auth_iv_addr = 0UL;
878 ent->final_auth_state_addr = 0UL;
879 ent->enc_key_addr = 0UL;
880 ent->enc_iv_addr = 0UL;
881 ent->dest_addr = 0UL;
882 }
883 ent->control |= CONTROL_END_OF_BLOCK;
884
885 return (spu_queue_submit(qp, ent) != HV_EOK) ? -EINVAL : 0;
886 }
887
888 static int n2_compute_chunks(struct ablkcipher_request *req)
889 {
890 struct n2_request_context *rctx = ablkcipher_request_ctx(req);
891 struct ablkcipher_walk *walk = &rctx->walk;
892 struct n2_crypto_chunk *chunk;
893 unsigned long dest_prev;
894 unsigned int tot_len;
895 bool prev_in_place;
896 int err, nbytes;
897
898 ablkcipher_walk_init(walk, req->dst, req->src, req->nbytes);
899 err = ablkcipher_walk_phys(req, walk);
900 if (err)
901 return err;
902
903 INIT_LIST_HEAD(&rctx->chunk_list);
904
905 chunk = &rctx->chunk;
906 INIT_LIST_HEAD(&chunk->entry);
907
908 chunk->iv_paddr = 0UL;
909 chunk->arr_len = 0;
910 chunk->dest_paddr = 0UL;
911
912 prev_in_place = false;
913 dest_prev = ~0UL;
914 tot_len = 0;
915
916 while ((nbytes = walk->nbytes) != 0) {
917 unsigned long dest_paddr, src_paddr;
918 bool in_place;
919 int this_len;
920
921 src_paddr = (page_to_phys(walk->src.page) +
922 walk->src.offset);
923 dest_paddr = (page_to_phys(walk->dst.page) +
924 walk->dst.offset);
925 in_place = (src_paddr == dest_paddr);
926 this_len = cipher_descriptor_len(nbytes, walk->blocksize);
927
928 if (chunk->arr_len != 0) {
929 if (in_place != prev_in_place ||
930 (!prev_in_place &&
931 dest_paddr != dest_prev) ||
932 chunk->arr_len == N2_CHUNK_ARR_LEN ||
933 tot_len + this_len > (1 << 16)) {
934 chunk->dest_final = dest_prev;
935 list_add_tail(&chunk->entry,
936 &rctx->chunk_list);
937 chunk = kzalloc(sizeof(*chunk), GFP_ATOMIC);
938 if (!chunk) {
939 err = -ENOMEM;
940 break;
941 }
942 INIT_LIST_HEAD(&chunk->entry);
943 }
944 }
945 if (chunk->arr_len == 0) {
946 chunk->dest_paddr = dest_paddr;
947 tot_len = 0;
948 }
949 chunk->arr[chunk->arr_len].src_paddr = src_paddr;
950 chunk->arr[chunk->arr_len].src_len = this_len;
951 chunk->arr_len++;
952
953 dest_prev = dest_paddr + this_len;
954 prev_in_place = in_place;
955 tot_len += this_len;
956
957 err = ablkcipher_walk_done(req, walk, nbytes - this_len);
958 if (err)
959 break;
960 }
961 if (!err && chunk->arr_len != 0) {
962 chunk->dest_final = dest_prev;
963 list_add_tail(&chunk->entry, &rctx->chunk_list);
964 }
965
966 return err;
967 }
968
969 static void n2_chunk_complete(struct ablkcipher_request *req, void *final_iv)
970 {
971 struct n2_request_context *rctx = ablkcipher_request_ctx(req);
972 struct n2_crypto_chunk *c, *tmp;
973
974 if (final_iv)
975 memcpy(rctx->walk.iv, final_iv, rctx->walk.blocksize);
976
977 ablkcipher_walk_complete(&rctx->walk);
978 list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
979 list_del(&c->entry);
980 if (unlikely(c != &rctx->chunk))
981 kfree(c);
982 }
983
984 }
985
986 static int n2_do_ecb(struct ablkcipher_request *req, bool encrypt)
987 {
988 struct n2_request_context *rctx = ablkcipher_request_ctx(req);
989 struct crypto_tfm *tfm = req->base.tfm;
990 int err = n2_compute_chunks(req);
991 struct n2_crypto_chunk *c, *tmp;
992 unsigned long flags, hv_ret;
993 struct spu_queue *qp;
994
995 if (err)
996 return err;
997
998 qp = cpu_to_cwq[get_cpu()];
999 err = -ENODEV;
1000 if (!qp)
1001 goto out;
1002
1003 spin_lock_irqsave(&qp->lock, flags);
1004
1005 list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
1006 err = __n2_crypt_chunk(tfm, c, qp, encrypt);
1007 if (err)
1008 break;
1009 list_del(&c->entry);
1010 if (unlikely(c != &rctx->chunk))
1011 kfree(c);
1012 }
1013 if (!err) {
1014 hv_ret = wait_for_tail(qp);
1015 if (hv_ret != HV_EOK)
1016 err = -EINVAL;
1017 }
1018
1019 spin_unlock_irqrestore(&qp->lock, flags);
1020
1021 out:
1022 put_cpu();
1023
1024 n2_chunk_complete(req, NULL);
1025 return err;
1026 }
1027
1028 static int n2_encrypt_ecb(struct ablkcipher_request *req)
1029 {
1030 return n2_do_ecb(req, true);
1031 }
1032
1033 static int n2_decrypt_ecb(struct ablkcipher_request *req)
1034 {
1035 return n2_do_ecb(req, false);
1036 }
1037
1038 static int n2_do_chaining(struct ablkcipher_request *req, bool encrypt)
1039 {
1040 struct n2_request_context *rctx = ablkcipher_request_ctx(req);
1041 struct crypto_tfm *tfm = req->base.tfm;
1042 unsigned long flags, hv_ret, iv_paddr;
1043 int err = n2_compute_chunks(req);
1044 struct n2_crypto_chunk *c, *tmp;
1045 struct spu_queue *qp;
1046 void *final_iv_addr;
1047
1048 final_iv_addr = NULL;
1049
1050 if (err)
1051 return err;
1052
1053 qp = cpu_to_cwq[get_cpu()];
1054 err = -ENODEV;
1055 if (!qp)
1056 goto out;
1057
1058 spin_lock_irqsave(&qp->lock, flags);
1059
1060 if (encrypt) {
1061 iv_paddr = __pa(rctx->walk.iv);
1062 list_for_each_entry_safe(c, tmp, &rctx->chunk_list,
1063 entry) {
1064 c->iv_paddr = iv_paddr;
1065 err = __n2_crypt_chunk(tfm, c, qp, true);
1066 if (err)
1067 break;
1068 iv_paddr = c->dest_final - rctx->walk.blocksize;
1069 list_del(&c->entry);
1070 if (unlikely(c != &rctx->chunk))
1071 kfree(c);
1072 }
1073 final_iv_addr = __va(iv_paddr);
1074 } else {
1075 list_for_each_entry_safe_reverse(c, tmp, &rctx->chunk_list,
1076 entry) {
1077 if (c == &rctx->chunk) {
1078 iv_paddr = __pa(rctx->walk.iv);
1079 } else {
1080 iv_paddr = (tmp->arr[tmp->arr_len-1].src_paddr +
1081 tmp->arr[tmp->arr_len-1].src_len -
1082 rctx->walk.blocksize);
1083 }
1084 if (!final_iv_addr) {
1085 unsigned long pa;
1086
1087 pa = (c->arr[c->arr_len-1].src_paddr +
1088 c->arr[c->arr_len-1].src_len -
1089 rctx->walk.blocksize);
1090 final_iv_addr = rctx->temp_iv;
1091 memcpy(rctx->temp_iv, __va(pa),
1092 rctx->walk.blocksize);
1093 }
1094 c->iv_paddr = iv_paddr;
1095 err = __n2_crypt_chunk(tfm, c, qp, false);
1096 if (err)
1097 break;
1098 list_del(&c->entry);
1099 if (unlikely(c != &rctx->chunk))
1100 kfree(c);
1101 }
1102 }
1103 if (!err) {
1104 hv_ret = wait_for_tail(qp);
1105 if (hv_ret != HV_EOK)
1106 err = -EINVAL;
1107 }
1108
1109 spin_unlock_irqrestore(&qp->lock, flags);
1110
1111 out:
1112 put_cpu();
1113
1114 n2_chunk_complete(req, err ? NULL : final_iv_addr);
1115 return err;
1116 }
1117
1118 static int n2_encrypt_chaining(struct ablkcipher_request *req)
1119 {
1120 return n2_do_chaining(req, true);
1121 }
1122
1123 static int n2_decrypt_chaining(struct ablkcipher_request *req)
1124 {
1125 return n2_do_chaining(req, false);
1126 }
1127
1128 struct n2_cipher_tmpl {
1129 const char *name;
1130 const char *drv_name;
1131 u8 block_size;
1132 u8 enc_type;
1133 struct ablkcipher_alg ablkcipher;
1134 };
1135
1136 static const struct n2_cipher_tmpl cipher_tmpls[] = {
1137 /* ARC4: only ECB is supported (chaining bits ignored) */
1138 { .name = "ecb(arc4)",
1139 .drv_name = "ecb-arc4",
1140 .block_size = 1,
1141 .enc_type = (ENC_TYPE_ALG_RC4_STREAM |
1142 ENC_TYPE_CHAINING_ECB),
1143 .ablkcipher = {
1144 .min_keysize = 1,
1145 .max_keysize = 256,
1146 .setkey = n2_arc4_setkey,
1147 .encrypt = n2_encrypt_ecb,
1148 .decrypt = n2_decrypt_ecb,
1149 },
1150 },
1151
1152 /* DES: ECB CBC and CFB are supported */
1153 { .name = "ecb(des)",
1154 .drv_name = "ecb-des",
1155 .block_size = DES_BLOCK_SIZE,
1156 .enc_type = (ENC_TYPE_ALG_DES |
1157 ENC_TYPE_CHAINING_ECB),
1158 .ablkcipher = {
1159 .min_keysize = DES_KEY_SIZE,
1160 .max_keysize = DES_KEY_SIZE,
1161 .setkey = n2_des_setkey,
1162 .encrypt = n2_encrypt_ecb,
1163 .decrypt = n2_decrypt_ecb,
1164 },
1165 },
1166 { .name = "cbc(des)",
1167 .drv_name = "cbc-des",
1168 .block_size = DES_BLOCK_SIZE,
1169 .enc_type = (ENC_TYPE_ALG_DES |
1170 ENC_TYPE_CHAINING_CBC),
1171 .ablkcipher = {
1172 .ivsize = DES_BLOCK_SIZE,
1173 .min_keysize = DES_KEY_SIZE,
1174 .max_keysize = DES_KEY_SIZE,
1175 .setkey = n2_des_setkey,
1176 .encrypt = n2_encrypt_chaining,
1177 .decrypt = n2_decrypt_chaining,
1178 },
1179 },
1180 { .name = "cfb(des)",
1181 .drv_name = "cfb-des",
1182 .block_size = DES_BLOCK_SIZE,
1183 .enc_type = (ENC_TYPE_ALG_DES |
1184 ENC_TYPE_CHAINING_CFB),
1185 .ablkcipher = {
1186 .min_keysize = DES_KEY_SIZE,
1187 .max_keysize = DES_KEY_SIZE,
1188 .setkey = n2_des_setkey,
1189 .encrypt = n2_encrypt_chaining,
1190 .decrypt = n2_decrypt_chaining,
1191 },
1192 },
1193
1194 /* 3DES: ECB CBC and CFB are supported */
1195 { .name = "ecb(des3_ede)",
1196 .drv_name = "ecb-3des",
1197 .block_size = DES_BLOCK_SIZE,
1198 .enc_type = (ENC_TYPE_ALG_3DES |
1199 ENC_TYPE_CHAINING_ECB),
1200 .ablkcipher = {
1201 .min_keysize = 3 * DES_KEY_SIZE,
1202 .max_keysize = 3 * DES_KEY_SIZE,
1203 .setkey = n2_3des_setkey,
1204 .encrypt = n2_encrypt_ecb,
1205 .decrypt = n2_decrypt_ecb,
1206 },
1207 },
1208 { .name = "cbc(des3_ede)",
1209 .drv_name = "cbc-3des",
1210 .block_size = DES_BLOCK_SIZE,
1211 .enc_type = (ENC_TYPE_ALG_3DES |
1212 ENC_TYPE_CHAINING_CBC),
1213 .ablkcipher = {
1214 .ivsize = DES_BLOCK_SIZE,
1215 .min_keysize = 3 * DES_KEY_SIZE,
1216 .max_keysize = 3 * DES_KEY_SIZE,
1217 .setkey = n2_3des_setkey,
1218 .encrypt = n2_encrypt_chaining,
1219 .decrypt = n2_decrypt_chaining,
1220 },
1221 },
1222 { .name = "cfb(des3_ede)",
1223 .drv_name = "cfb-3des",
1224 .block_size = DES_BLOCK_SIZE,
1225 .enc_type = (ENC_TYPE_ALG_3DES |
1226 ENC_TYPE_CHAINING_CFB),
1227 .ablkcipher = {
1228 .min_keysize = 3 * DES_KEY_SIZE,
1229 .max_keysize = 3 * DES_KEY_SIZE,
1230 .setkey = n2_3des_setkey,
1231 .encrypt = n2_encrypt_chaining,
1232 .decrypt = n2_decrypt_chaining,
1233 },
1234 },
1235 /* AES: ECB CBC and CTR are supported */
1236 { .name = "ecb(aes)",
1237 .drv_name = "ecb-aes",
1238 .block_size = AES_BLOCK_SIZE,
1239 .enc_type = (ENC_TYPE_ALG_AES128 |
1240 ENC_TYPE_CHAINING_ECB),
1241 .ablkcipher = {
1242 .min_keysize = AES_MIN_KEY_SIZE,
1243 .max_keysize = AES_MAX_KEY_SIZE,
1244 .setkey = n2_aes_setkey,
1245 .encrypt = n2_encrypt_ecb,
1246 .decrypt = n2_decrypt_ecb,
1247 },
1248 },
1249 { .name = "cbc(aes)",
1250 .drv_name = "cbc-aes",
1251 .block_size = AES_BLOCK_SIZE,
1252 .enc_type = (ENC_TYPE_ALG_AES128 |
1253 ENC_TYPE_CHAINING_CBC),
1254 .ablkcipher = {
1255 .ivsize = AES_BLOCK_SIZE,
1256 .min_keysize = AES_MIN_KEY_SIZE,
1257 .max_keysize = AES_MAX_KEY_SIZE,
1258 .setkey = n2_aes_setkey,
1259 .encrypt = n2_encrypt_chaining,
1260 .decrypt = n2_decrypt_chaining,
1261 },
1262 },
1263 { .name = "ctr(aes)",
1264 .drv_name = "ctr-aes",
1265 .block_size = AES_BLOCK_SIZE,
1266 .enc_type = (ENC_TYPE_ALG_AES128 |
1267 ENC_TYPE_CHAINING_COUNTER),
1268 .ablkcipher = {
1269 .ivsize = AES_BLOCK_SIZE,
1270 .min_keysize = AES_MIN_KEY_SIZE,
1271 .max_keysize = AES_MAX_KEY_SIZE,
1272 .setkey = n2_aes_setkey,
1273 .encrypt = n2_encrypt_chaining,
1274 .decrypt = n2_encrypt_chaining,
1275 },
1276 },
1277
1278 };
1279 #define NUM_CIPHER_TMPLS ARRAY_SIZE(cipher_tmpls)
1280
1281 static LIST_HEAD(cipher_algs);
1282
1283 struct n2_hash_tmpl {
1284 const char *name;
1285 const u8 *hash_zero;
1286 const u32 *hash_init;
1287 u8 hw_op_hashsz;
1288 u8 digest_size;
1289 u8 block_size;
1290 u8 auth_type;
1291 u8 hmac_type;
1292 };
1293
1294 static const u32 md5_init[MD5_HASH_WORDS] = {
1295 cpu_to_le32(MD5_H0),
1296 cpu_to_le32(MD5_H1),
1297 cpu_to_le32(MD5_H2),
1298 cpu_to_le32(MD5_H3),
1299 };
1300 static const u32 sha1_init[SHA1_DIGEST_SIZE / 4] = {
1301 SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4,
1302 };
1303 static const u32 sha256_init[SHA256_DIGEST_SIZE / 4] = {
1304 SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
1305 SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7,
1306 };
1307 static const u32 sha224_init[SHA256_DIGEST_SIZE / 4] = {
1308 SHA224_H0, SHA224_H1, SHA224_H2, SHA224_H3,
1309 SHA224_H4, SHA224_H5, SHA224_H6, SHA224_H7,
1310 };
1311
1312 static const struct n2_hash_tmpl hash_tmpls[] = {
1313 { .name = "md5",
1314 .hash_zero = md5_zero_message_hash,
1315 .hash_init = md5_init,
1316 .auth_type = AUTH_TYPE_MD5,
1317 .hmac_type = AUTH_TYPE_HMAC_MD5,
1318 .hw_op_hashsz = MD5_DIGEST_SIZE,
1319 .digest_size = MD5_DIGEST_SIZE,
1320 .block_size = MD5_HMAC_BLOCK_SIZE },
1321 { .name = "sha1",
1322 .hash_zero = sha1_zero_message_hash,
1323 .hash_init = sha1_init,
1324 .auth_type = AUTH_TYPE_SHA1,
1325 .hmac_type = AUTH_TYPE_HMAC_SHA1,
1326 .hw_op_hashsz = SHA1_DIGEST_SIZE,
1327 .digest_size = SHA1_DIGEST_SIZE,
1328 .block_size = SHA1_BLOCK_SIZE },
1329 { .name = "sha256",
1330 .hash_zero = sha256_zero_message_hash,
1331 .hash_init = sha256_init,
1332 .auth_type = AUTH_TYPE_SHA256,
1333 .hmac_type = AUTH_TYPE_HMAC_SHA256,
1334 .hw_op_hashsz = SHA256_DIGEST_SIZE,
1335 .digest_size = SHA256_DIGEST_SIZE,
1336 .block_size = SHA256_BLOCK_SIZE },
1337 { .name = "sha224",
1338 .hash_zero = sha224_zero_message_hash,
1339 .hash_init = sha224_init,
1340 .auth_type = AUTH_TYPE_SHA256,
1341 .hmac_type = AUTH_TYPE_RESERVED,
1342 .hw_op_hashsz = SHA256_DIGEST_SIZE,
1343 .digest_size = SHA224_DIGEST_SIZE,
1344 .block_size = SHA224_BLOCK_SIZE },
1345 };
1346 #define NUM_HASH_TMPLS ARRAY_SIZE(hash_tmpls)
1347
1348 static LIST_HEAD(ahash_algs);
1349 static LIST_HEAD(hmac_algs);
1350
1351 static int algs_registered;
1352
1353 static void __n2_unregister_algs(void)
1354 {
1355 struct n2_cipher_alg *cipher, *cipher_tmp;
1356 struct n2_ahash_alg *alg, *alg_tmp;
1357 struct n2_hmac_alg *hmac, *hmac_tmp;
1358
1359 list_for_each_entry_safe(cipher, cipher_tmp, &cipher_algs, entry) {
1360 crypto_unregister_alg(&cipher->alg);
1361 list_del(&cipher->entry);
1362 kfree(cipher);
1363 }
1364 list_for_each_entry_safe(hmac, hmac_tmp, &hmac_algs, derived.entry) {
1365 crypto_unregister_ahash(&hmac->derived.alg);
1366 list_del(&hmac->derived.entry);
1367 kfree(hmac);
1368 }
1369 list_for_each_entry_safe(alg, alg_tmp, &ahash_algs, entry) {
1370 crypto_unregister_ahash(&alg->alg);
1371 list_del(&alg->entry);
1372 kfree(alg);
1373 }
1374 }
1375
1376 static int n2_cipher_cra_init(struct crypto_tfm *tfm)
1377 {
1378 tfm->crt_ablkcipher.reqsize = sizeof(struct n2_request_context);
1379 return 0;
1380 }
1381
1382 static int __n2_register_one_cipher(const struct n2_cipher_tmpl *tmpl)
1383 {
1384 struct n2_cipher_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1385 struct crypto_alg *alg;
1386 int err;
1387
1388 if (!p)
1389 return -ENOMEM;
1390
1391 alg = &p->alg;
1392
1393 snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1394 snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->drv_name);
1395 alg->cra_priority = N2_CRA_PRIORITY;
1396 alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1397 CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC;
1398 alg->cra_blocksize = tmpl->block_size;
1399 p->enc_type = tmpl->enc_type;
1400 alg->cra_ctxsize = sizeof(struct n2_cipher_context);
1401 alg->cra_type = &crypto_ablkcipher_type;
1402 alg->cra_u.ablkcipher = tmpl->ablkcipher;
1403 alg->cra_init = n2_cipher_cra_init;
1404 alg->cra_module = THIS_MODULE;
1405
1406 list_add(&p->entry, &cipher_algs);
1407 err = crypto_register_alg(alg);
1408 if (err) {
1409 pr_err("%s alg registration failed\n", alg->cra_name);
1410 list_del(&p->entry);
1411 kfree(p);
1412 } else {
1413 pr_info("%s alg registered\n", alg->cra_name);
1414 }
1415 return err;
1416 }
1417
1418 static int __n2_register_one_hmac(struct n2_ahash_alg *n2ahash)
1419 {
1420 struct n2_hmac_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1421 struct ahash_alg *ahash;
1422 struct crypto_alg *base;
1423 int err;
1424
1425 if (!p)
1426 return -ENOMEM;
1427
1428 p->child_alg = n2ahash->alg.halg.base.cra_name;
1429 memcpy(&p->derived, n2ahash, sizeof(struct n2_ahash_alg));
1430 INIT_LIST_HEAD(&p->derived.entry);
1431
1432 ahash = &p->derived.alg;
1433 ahash->digest = n2_hmac_async_digest;
1434 ahash->setkey = n2_hmac_async_setkey;
1435
1436 base = &ahash->halg.base;
1437 snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "hmac(%s)", p->child_alg);
1438 snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "hmac-%s-n2", p->child_alg);
1439
1440 base->cra_ctxsize = sizeof(struct n2_hmac_ctx);
1441 base->cra_init = n2_hmac_cra_init;
1442 base->cra_exit = n2_hmac_cra_exit;
1443
1444 list_add(&p->derived.entry, &hmac_algs);
1445 err = crypto_register_ahash(ahash);
1446 if (err) {
1447 pr_err("%s alg registration failed\n", base->cra_name);
1448 list_del(&p->derived.entry);
1449 kfree(p);
1450 } else {
1451 pr_info("%s alg registered\n", base->cra_name);
1452 }
1453 return err;
1454 }
1455
1456 static int __n2_register_one_ahash(const struct n2_hash_tmpl *tmpl)
1457 {
1458 struct n2_ahash_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1459 struct hash_alg_common *halg;
1460 struct crypto_alg *base;
1461 struct ahash_alg *ahash;
1462 int err;
1463
1464 if (!p)
1465 return -ENOMEM;
1466
1467 p->hash_zero = tmpl->hash_zero;
1468 p->hash_init = tmpl->hash_init;
1469 p->auth_type = tmpl->auth_type;
1470 p->hmac_type = tmpl->hmac_type;
1471 p->hw_op_hashsz = tmpl->hw_op_hashsz;
1472 p->digest_size = tmpl->digest_size;
1473
1474 ahash = &p->alg;
1475 ahash->init = n2_hash_async_init;
1476 ahash->update = n2_hash_async_update;
1477 ahash->final = n2_hash_async_final;
1478 ahash->finup = n2_hash_async_finup;
1479 ahash->digest = n2_hash_async_digest;
1480 ahash->export = n2_hash_async_noexport;
1481 ahash->import = n2_hash_async_noimport;
1482
1483 halg = &ahash->halg;
1484 halg->digestsize = tmpl->digest_size;
1485
1486 base = &halg->base;
1487 snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1488 snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->name);
1489 base->cra_priority = N2_CRA_PRIORITY;
1490 base->cra_flags = CRYPTO_ALG_TYPE_AHASH |
1491 CRYPTO_ALG_KERN_DRIVER_ONLY |
1492 CRYPTO_ALG_NEED_FALLBACK;
1493 base->cra_blocksize = tmpl->block_size;
1494 base->cra_ctxsize = sizeof(struct n2_hash_ctx);
1495 base->cra_module = THIS_MODULE;
1496 base->cra_init = n2_hash_cra_init;
1497 base->cra_exit = n2_hash_cra_exit;
1498
1499 list_add(&p->entry, &ahash_algs);
1500 err = crypto_register_ahash(ahash);
1501 if (err) {
1502 pr_err("%s alg registration failed\n", base->cra_name);
1503 list_del(&p->entry);
1504 kfree(p);
1505 } else {
1506 pr_info("%s alg registered\n", base->cra_name);
1507 }
1508 if (!err && p->hmac_type != AUTH_TYPE_RESERVED)
1509 err = __n2_register_one_hmac(p);
1510 return err;
1511 }
1512
1513 static int n2_register_algs(void)
1514 {
1515 int i, err = 0;
1516
1517 mutex_lock(&spu_lock);
1518 if (algs_registered++)
1519 goto out;
1520
1521 for (i = 0; i < NUM_HASH_TMPLS; i++) {
1522 err = __n2_register_one_ahash(&hash_tmpls[i]);
1523 if (err) {
1524 __n2_unregister_algs();
1525 goto out;
1526 }
1527 }
1528 for (i = 0; i < NUM_CIPHER_TMPLS; i++) {
1529 err = __n2_register_one_cipher(&cipher_tmpls[i]);
1530 if (err) {
1531 __n2_unregister_algs();
1532 goto out;
1533 }
1534 }
1535
1536 out:
1537 mutex_unlock(&spu_lock);
1538 return err;
1539 }
1540
1541 static void n2_unregister_algs(void)
1542 {
1543 mutex_lock(&spu_lock);
1544 if (!--algs_registered)
1545 __n2_unregister_algs();
1546 mutex_unlock(&spu_lock);
1547 }
1548
1549 /* To map CWQ queues to interrupt sources, the hypervisor API provides
1550 * a devino. This isn't very useful to us because all of the
1551 * interrupts listed in the device_node have been translated to
1552 * Linux virtual IRQ cookie numbers.
1553 *
1554 * So we have to back-translate, going through the 'intr' and 'ino'
1555 * property tables of the n2cp MDESC node, matching it with the OF
1556 * 'interrupts' property entries, in order to to figure out which
1557 * devino goes to which already-translated IRQ.
1558 */
1559 static int find_devino_index(struct platform_device *dev, struct spu_mdesc_info *ip,
1560 unsigned long dev_ino)
1561 {
1562 const unsigned int *dev_intrs;
1563 unsigned int intr;
1564 int i;
1565
1566 for (i = 0; i < ip->num_intrs; i++) {
1567 if (ip->ino_table[i].ino == dev_ino)
1568 break;
1569 }
1570 if (i == ip->num_intrs)
1571 return -ENODEV;
1572
1573 intr = ip->ino_table[i].intr;
1574
1575 dev_intrs = of_get_property(dev->dev.of_node, "interrupts", NULL);
1576 if (!dev_intrs)
1577 return -ENODEV;
1578
1579 for (i = 0; i < dev->archdata.num_irqs; i++) {
1580 if (dev_intrs[i] == intr)
1581 return i;
1582 }
1583
1584 return -ENODEV;
1585 }
1586
1587 static int spu_map_ino(struct platform_device *dev, struct spu_mdesc_info *ip,
1588 const char *irq_name, struct spu_queue *p,
1589 irq_handler_t handler)
1590 {
1591 unsigned long herr;
1592 int index;
1593
1594 herr = sun4v_ncs_qhandle_to_devino(p->qhandle, &p->devino);
1595 if (herr)
1596 return -EINVAL;
1597
1598 index = find_devino_index(dev, ip, p->devino);
1599 if (index < 0)
1600 return index;
1601
1602 p->irq = dev->archdata.irqs[index];
1603
1604 sprintf(p->irq_name, "%s-%d", irq_name, index);
1605
1606 return request_irq(p->irq, handler, 0, p->irq_name, p);
1607 }
1608
1609 static struct kmem_cache *queue_cache[2];
1610
1611 static void *new_queue(unsigned long q_type)
1612 {
1613 return kmem_cache_zalloc(queue_cache[q_type - 1], GFP_KERNEL);
1614 }
1615
1616 static void free_queue(void *p, unsigned long q_type)
1617 {
1618 kmem_cache_free(queue_cache[q_type - 1], p);
1619 }
1620
1621 static int queue_cache_init(void)
1622 {
1623 if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1624 queue_cache[HV_NCS_QTYPE_MAU - 1] =
1625 kmem_cache_create("mau_queue",
1626 (MAU_NUM_ENTRIES *
1627 MAU_ENTRY_SIZE),
1628 MAU_ENTRY_SIZE, 0, NULL);
1629 if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1630 return -ENOMEM;
1631
1632 if (!queue_cache[HV_NCS_QTYPE_CWQ - 1])
1633 queue_cache[HV_NCS_QTYPE_CWQ - 1] =
1634 kmem_cache_create("cwq_queue",
1635 (CWQ_NUM_ENTRIES *
1636 CWQ_ENTRY_SIZE),
1637 CWQ_ENTRY_SIZE, 0, NULL);
1638 if (!queue_cache[HV_NCS_QTYPE_CWQ - 1]) {
1639 kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1640 queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1641 return -ENOMEM;
1642 }
1643 return 0;
1644 }
1645
1646 static void queue_cache_destroy(void)
1647 {
1648 kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1649 kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_CWQ - 1]);
1650 queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1651 queue_cache[HV_NCS_QTYPE_CWQ - 1] = NULL;
1652 }
1653
1654 static long spu_queue_register_workfn(void *arg)
1655 {
1656 struct spu_qreg *qr = arg;
1657 struct spu_queue *p = qr->queue;
1658 unsigned long q_type = qr->type;
1659 unsigned long hv_ret;
1660
1661 hv_ret = sun4v_ncs_qconf(q_type, __pa(p->q),
1662 CWQ_NUM_ENTRIES, &p->qhandle);
1663 if (!hv_ret)
1664 sun4v_ncs_sethead_marker(p->qhandle, 0);
1665
1666 return hv_ret ? -EINVAL : 0;
1667 }
1668
1669 static int spu_queue_register(struct spu_queue *p, unsigned long q_type)
1670 {
1671 int cpu = cpumask_any_and(&p->sharing, cpu_online_mask);
1672 struct spu_qreg qr = { .queue = p, .type = q_type };
1673
1674 return work_on_cpu_safe(cpu, spu_queue_register_workfn, &qr);
1675 }
1676
1677 static int spu_queue_setup(struct spu_queue *p)
1678 {
1679 int err;
1680
1681 p->q = new_queue(p->q_type);
1682 if (!p->q)
1683 return -ENOMEM;
1684
1685 err = spu_queue_register(p, p->q_type);
1686 if (err) {
1687 free_queue(p->q, p->q_type);
1688 p->q = NULL;
1689 }
1690
1691 return err;
1692 }
1693
1694 static void spu_queue_destroy(struct spu_queue *p)
1695 {
1696 unsigned long hv_ret;
1697
1698 if (!p->q)
1699 return;
1700
1701 hv_ret = sun4v_ncs_qconf(p->q_type, p->qhandle, 0, &p->qhandle);
1702
1703 if (!hv_ret)
1704 free_queue(p->q, p->q_type);
1705 }
1706
1707 static void spu_list_destroy(struct list_head *list)
1708 {
1709 struct spu_queue *p, *n;
1710
1711 list_for_each_entry_safe(p, n, list, list) {
1712 int i;
1713
1714 for (i = 0; i < NR_CPUS; i++) {
1715 if (cpu_to_cwq[i] == p)
1716 cpu_to_cwq[i] = NULL;
1717 }
1718
1719 if (p->irq) {
1720 free_irq(p->irq, p);
1721 p->irq = 0;
1722 }
1723 spu_queue_destroy(p);
1724 list_del(&p->list);
1725 kfree(p);
1726 }
1727 }
1728
1729 /* Walk the backward arcs of a CWQ 'exec-unit' node,
1730 * gathering cpu membership information.
1731 */
1732 static int spu_mdesc_walk_arcs(struct mdesc_handle *mdesc,
1733 struct platform_device *dev,
1734 u64 node, struct spu_queue *p,
1735 struct spu_queue **table)
1736 {
1737 u64 arc;
1738
1739 mdesc_for_each_arc(arc, mdesc, node, MDESC_ARC_TYPE_BACK) {
1740 u64 tgt = mdesc_arc_target(mdesc, arc);
1741 const char *name = mdesc_node_name(mdesc, tgt);
1742 const u64 *id;
1743
1744 if (strcmp(name, "cpu"))
1745 continue;
1746 id = mdesc_get_property(mdesc, tgt, "id", NULL);
1747 if (table[*id] != NULL) {
1748 dev_err(&dev->dev, "%pOF: SPU cpu slot already set.\n",
1749 dev->dev.of_node);
1750 return -EINVAL;
1751 }
1752 cpumask_set_cpu(*id, &p->sharing);
1753 table[*id] = p;
1754 }
1755 return 0;
1756 }
1757
1758 /* Process an 'exec-unit' MDESC node of type 'cwq'. */
1759 static int handle_exec_unit(struct spu_mdesc_info *ip, struct list_head *list,
1760 struct platform_device *dev, struct mdesc_handle *mdesc,
1761 u64 node, const char *iname, unsigned long q_type,
1762 irq_handler_t handler, struct spu_queue **table)
1763 {
1764 struct spu_queue *p;
1765 int err;
1766
1767 p = kzalloc(sizeof(struct spu_queue), GFP_KERNEL);
1768 if (!p) {
1769 dev_err(&dev->dev, "%pOF: Could not allocate SPU queue.\n",
1770 dev->dev.of_node);
1771 return -ENOMEM;
1772 }
1773
1774 cpumask_clear(&p->sharing);
1775 spin_lock_init(&p->lock);
1776 p->q_type = q_type;
1777 INIT_LIST_HEAD(&p->jobs);
1778 list_add(&p->list, list);
1779
1780 err = spu_mdesc_walk_arcs(mdesc, dev, node, p, table);
1781 if (err)
1782 return err;
1783
1784 err = spu_queue_setup(p);
1785 if (err)
1786 return err;
1787
1788 return spu_map_ino(dev, ip, iname, p, handler);
1789 }
1790
1791 static int spu_mdesc_scan(struct mdesc_handle *mdesc, struct platform_device *dev,
1792 struct spu_mdesc_info *ip, struct list_head *list,
1793 const char *exec_name, unsigned long q_type,
1794 irq_handler_t handler, struct spu_queue **table)
1795 {
1796 int err = 0;
1797 u64 node;
1798
1799 mdesc_for_each_node_by_name(mdesc, node, "exec-unit") {
1800 const char *type;
1801
1802 type = mdesc_get_property(mdesc, node, "type", NULL);
1803 if (!type || strcmp(type, exec_name))
1804 continue;
1805
1806 err = handle_exec_unit(ip, list, dev, mdesc, node,
1807 exec_name, q_type, handler, table);
1808 if (err) {
1809 spu_list_destroy(list);
1810 break;
1811 }
1812 }
1813
1814 return err;
1815 }
1816
1817 static int get_irq_props(struct mdesc_handle *mdesc, u64 node,
1818 struct spu_mdesc_info *ip)
1819 {
1820 const u64 *ino;
1821 int ino_len;
1822 int i;
1823
1824 ino = mdesc_get_property(mdesc, node, "ino", &ino_len);
1825 if (!ino) {
1826 printk("NO 'ino'\n");
1827 return -ENODEV;
1828 }
1829
1830 ip->num_intrs = ino_len / sizeof(u64);
1831 ip->ino_table = kzalloc((sizeof(struct ino_blob) *
1832 ip->num_intrs),
1833 GFP_KERNEL);
1834 if (!ip->ino_table)
1835 return -ENOMEM;
1836
1837 for (i = 0; i < ip->num_intrs; i++) {
1838 struct ino_blob *b = &ip->ino_table[i];
1839 b->intr = i + 1;
1840 b->ino = ino[i];
1841 }
1842
1843 return 0;
1844 }
1845
1846 static int grab_mdesc_irq_props(struct mdesc_handle *mdesc,
1847 struct platform_device *dev,
1848 struct spu_mdesc_info *ip,
1849 const char *node_name)
1850 {
1851 const unsigned int *reg;
1852 u64 node;
1853
1854 reg = of_get_property(dev->dev.of_node, "reg", NULL);
1855 if (!reg)
1856 return -ENODEV;
1857
1858 mdesc_for_each_node_by_name(mdesc, node, "virtual-device") {
1859 const char *name;
1860 const u64 *chdl;
1861
1862 name = mdesc_get_property(mdesc, node, "name", NULL);
1863 if (!name || strcmp(name, node_name))
1864 continue;
1865 chdl = mdesc_get_property(mdesc, node, "cfg-handle", NULL);
1866 if (!chdl || (*chdl != *reg))
1867 continue;
1868 ip->cfg_handle = *chdl;
1869 return get_irq_props(mdesc, node, ip);
1870 }
1871
1872 return -ENODEV;
1873 }
1874
1875 static unsigned long n2_spu_hvapi_major;
1876 static unsigned long n2_spu_hvapi_minor;
1877
1878 static int n2_spu_hvapi_register(void)
1879 {
1880 int err;
1881
1882 n2_spu_hvapi_major = 2;
1883 n2_spu_hvapi_minor = 0;
1884
1885 err = sun4v_hvapi_register(HV_GRP_NCS,
1886 n2_spu_hvapi_major,
1887 &n2_spu_hvapi_minor);
1888
1889 if (!err)
1890 pr_info("Registered NCS HVAPI version %lu.%lu\n",
1891 n2_spu_hvapi_major,
1892 n2_spu_hvapi_minor);
1893
1894 return err;
1895 }
1896
1897 static void n2_spu_hvapi_unregister(void)
1898 {
1899 sun4v_hvapi_unregister(HV_GRP_NCS);
1900 }
1901
1902 static int global_ref;
1903
1904 static int grab_global_resources(void)
1905 {
1906 int err = 0;
1907
1908 mutex_lock(&spu_lock);
1909
1910 if (global_ref++)
1911 goto out;
1912
1913 err = n2_spu_hvapi_register();
1914 if (err)
1915 goto out;
1916
1917 err = queue_cache_init();
1918 if (err)
1919 goto out_hvapi_release;
1920
1921 err = -ENOMEM;
1922 cpu_to_cwq = kzalloc(sizeof(struct spu_queue *) * NR_CPUS,
1923 GFP_KERNEL);
1924 if (!cpu_to_cwq)
1925 goto out_queue_cache_destroy;
1926
1927 cpu_to_mau = kzalloc(sizeof(struct spu_queue *) * NR_CPUS,
1928 GFP_KERNEL);
1929 if (!cpu_to_mau)
1930 goto out_free_cwq_table;
1931
1932 err = 0;
1933
1934 out:
1935 if (err)
1936 global_ref--;
1937 mutex_unlock(&spu_lock);
1938 return err;
1939
1940 out_free_cwq_table:
1941 kfree(cpu_to_cwq);
1942 cpu_to_cwq = NULL;
1943
1944 out_queue_cache_destroy:
1945 queue_cache_destroy();
1946
1947 out_hvapi_release:
1948 n2_spu_hvapi_unregister();
1949 goto out;
1950 }
1951
1952 static void release_global_resources(void)
1953 {
1954 mutex_lock(&spu_lock);
1955 if (!--global_ref) {
1956 kfree(cpu_to_cwq);
1957 cpu_to_cwq = NULL;
1958
1959 kfree(cpu_to_mau);
1960 cpu_to_mau = NULL;
1961
1962 queue_cache_destroy();
1963 n2_spu_hvapi_unregister();
1964 }
1965 mutex_unlock(&spu_lock);
1966 }
1967
1968 static struct n2_crypto *alloc_n2cp(void)
1969 {
1970 struct n2_crypto *np = kzalloc(sizeof(struct n2_crypto), GFP_KERNEL);
1971
1972 if (np)
1973 INIT_LIST_HEAD(&np->cwq_list);
1974
1975 return np;
1976 }
1977
1978 static void free_n2cp(struct n2_crypto *np)
1979 {
1980 kfree(np->cwq_info.ino_table);
1981 np->cwq_info.ino_table = NULL;
1982
1983 kfree(np);
1984 }
1985
1986 static void n2_spu_driver_version(void)
1987 {
1988 static int n2_spu_version_printed;
1989
1990 if (n2_spu_version_printed++ == 0)
1991 pr_info("%s", version);
1992 }
1993
1994 static int n2_crypto_probe(struct platform_device *dev)
1995 {
1996 struct mdesc_handle *mdesc;
1997 struct n2_crypto *np;
1998 int err;
1999
2000 n2_spu_driver_version();
2001
2002 pr_info("Found N2CP at %pOF\n", dev->dev.of_node);
2003
2004 np = alloc_n2cp();
2005 if (!np) {
2006 dev_err(&dev->dev, "%pOF: Unable to allocate n2cp.\n",
2007 dev->dev.of_node);
2008 return -ENOMEM;
2009 }
2010
2011 err = grab_global_resources();
2012 if (err) {
2013 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
2014 dev->dev.of_node);
2015 goto out_free_n2cp;
2016 }
2017
2018 mdesc = mdesc_grab();
2019
2020 if (!mdesc) {
2021 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
2022 dev->dev.of_node);
2023 err = -ENODEV;
2024 goto out_free_global;
2025 }
2026 err = grab_mdesc_irq_props(mdesc, dev, &np->cwq_info, "n2cp");
2027 if (err) {
2028 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
2029 dev->dev.of_node);
2030 mdesc_release(mdesc);
2031 goto out_free_global;
2032 }
2033
2034 err = spu_mdesc_scan(mdesc, dev, &np->cwq_info, &np->cwq_list,
2035 "cwq", HV_NCS_QTYPE_CWQ, cwq_intr,
2036 cpu_to_cwq);
2037 mdesc_release(mdesc);
2038
2039 if (err) {
2040 dev_err(&dev->dev, "%pOF: CWQ MDESC scan failed.\n",
2041 dev->dev.of_node);
2042 goto out_free_global;
2043 }
2044
2045 err = n2_register_algs();
2046 if (err) {
2047 dev_err(&dev->dev, "%pOF: Unable to register algorithms.\n",
2048 dev->dev.of_node);
2049 goto out_free_spu_list;
2050 }
2051
2052 dev_set_drvdata(&dev->dev, np);
2053
2054 return 0;
2055
2056 out_free_spu_list:
2057 spu_list_destroy(&np->cwq_list);
2058
2059 out_free_global:
2060 release_global_resources();
2061
2062 out_free_n2cp:
2063 free_n2cp(np);
2064
2065 return err;
2066 }
2067
2068 static int n2_crypto_remove(struct platform_device *dev)
2069 {
2070 struct n2_crypto *np = dev_get_drvdata(&dev->dev);
2071
2072 n2_unregister_algs();
2073
2074 spu_list_destroy(&np->cwq_list);
2075
2076 release_global_resources();
2077
2078 free_n2cp(np);
2079
2080 return 0;
2081 }
2082
2083 static struct n2_mau *alloc_ncp(void)
2084 {
2085 struct n2_mau *mp = kzalloc(sizeof(struct n2_mau), GFP_KERNEL);
2086
2087 if (mp)
2088 INIT_LIST_HEAD(&mp->mau_list);
2089
2090 return mp;
2091 }
2092
2093 static void free_ncp(struct n2_mau *mp)
2094 {
2095 kfree(mp->mau_info.ino_table);
2096 mp->mau_info.ino_table = NULL;
2097
2098 kfree(mp);
2099 }
2100
2101 static int n2_mau_probe(struct platform_device *dev)
2102 {
2103 struct mdesc_handle *mdesc;
2104 struct n2_mau *mp;
2105 int err;
2106
2107 n2_spu_driver_version();
2108
2109 pr_info("Found NCP at %pOF\n", dev->dev.of_node);
2110
2111 mp = alloc_ncp();
2112 if (!mp) {
2113 dev_err(&dev->dev, "%pOF: Unable to allocate ncp.\n",
2114 dev->dev.of_node);
2115 return -ENOMEM;
2116 }
2117
2118 err = grab_global_resources();
2119 if (err) {
2120 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
2121 dev->dev.of_node);
2122 goto out_free_ncp;
2123 }
2124
2125 mdesc = mdesc_grab();
2126
2127 if (!mdesc) {
2128 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
2129 dev->dev.of_node);
2130 err = -ENODEV;
2131 goto out_free_global;
2132 }
2133
2134 err = grab_mdesc_irq_props(mdesc, dev, &mp->mau_info, "ncp");
2135 if (err) {
2136 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
2137 dev->dev.of_node);
2138 mdesc_release(mdesc);
2139 goto out_free_global;
2140 }
2141
2142 err = spu_mdesc_scan(mdesc, dev, &mp->mau_info, &mp->mau_list,
2143 "mau", HV_NCS_QTYPE_MAU, mau_intr,
2144 cpu_to_mau);
2145 mdesc_release(mdesc);
2146
2147 if (err) {
2148 dev_err(&dev->dev, "%pOF: MAU MDESC scan failed.\n",
2149 dev->dev.of_node);
2150 goto out_free_global;
2151 }
2152
2153 dev_set_drvdata(&dev->dev, mp);
2154
2155 return 0;
2156
2157 out_free_global:
2158 release_global_resources();
2159
2160 out_free_ncp:
2161 free_ncp(mp);
2162
2163 return err;
2164 }
2165
2166 static int n2_mau_remove(struct platform_device *dev)
2167 {
2168 struct n2_mau *mp = dev_get_drvdata(&dev->dev);
2169
2170 spu_list_destroy(&mp->mau_list);
2171
2172 release_global_resources();
2173
2174 free_ncp(mp);
2175
2176 return 0;
2177 }
2178
2179 static const struct of_device_id n2_crypto_match[] = {
2180 {
2181 .name = "n2cp",
2182 .compatible = "SUNW,n2-cwq",
2183 },
2184 {
2185 .name = "n2cp",
2186 .compatible = "SUNW,vf-cwq",
2187 },
2188 {
2189 .name = "n2cp",
2190 .compatible = "SUNW,kt-cwq",
2191 },
2192 {},
2193 };
2194
2195 MODULE_DEVICE_TABLE(of, n2_crypto_match);
2196
2197 static struct platform_driver n2_crypto_driver = {
2198 .driver = {
2199 .name = "n2cp",
2200 .of_match_table = n2_crypto_match,
2201 },
2202 .probe = n2_crypto_probe,
2203 .remove = n2_crypto_remove,
2204 };
2205
2206 static const struct of_device_id n2_mau_match[] = {
2207 {
2208 .name = "ncp",
2209 .compatible = "SUNW,n2-mau",
2210 },
2211 {
2212 .name = "ncp",
2213 .compatible = "SUNW,vf-mau",
2214 },
2215 {
2216 .name = "ncp",
2217 .compatible = "SUNW,kt-mau",
2218 },
2219 {},
2220 };
2221
2222 MODULE_DEVICE_TABLE(of, n2_mau_match);
2223
2224 static struct platform_driver n2_mau_driver = {
2225 .driver = {
2226 .name = "ncp",
2227 .of_match_table = n2_mau_match,
2228 },
2229 .probe = n2_mau_probe,
2230 .remove = n2_mau_remove,
2231 };
2232
2233 static struct platform_driver * const drivers[] = {
2234 &n2_crypto_driver,
2235 &n2_mau_driver,
2236 };
2237
2238 static int __init n2_init(void)
2239 {
2240 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2241 }
2242
2243 static void __exit n2_exit(void)
2244 {
2245 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2246 }
2247
2248 module_init(n2_init);
2249 module_exit(n2_exit);
Linux with added FPC-III support