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crypto: arm64/aes-ghash - yield NEON after every block of input
[linux/fpc-iii.git] / drivers / scsi / bfa / bfi.h
blob5f698d038b21f2c7d54c26da10949bfcbce0655a
1 /*
2 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
3 * Copyright (c) 2014- QLogic Corporation.
4 * All rights reserved
5 * www.qlogic.com
6 *
7 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License (GPL) Version 2 as
11 * published by the Free Software Foundation
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19 #ifndef __BFI_H__
20 #define __BFI_H__
21
22 #include "bfa_defs.h"
23 #include "bfa_defs_svc.h"
24
25 #pragma pack(1)
26
27 /* Per dma segment max size */
28 #define BFI_MEM_DMA_SEG_SZ (131072)
29
30 /* Get number of dma segments required */
31 #define BFI_MEM_DMA_NSEGS(_num_reqs, _req_sz) \
32 ((u16)(((((_num_reqs) * (_req_sz)) + BFI_MEM_DMA_SEG_SZ - 1) & \
33 ~(BFI_MEM_DMA_SEG_SZ - 1)) / BFI_MEM_DMA_SEG_SZ))
34
35 /* Get num dma reqs - that fit in a segment */
36 #define BFI_MEM_NREQS_SEG(_rqsz) (BFI_MEM_DMA_SEG_SZ / (_rqsz))
37
38 /* Get segment num from tag */
39 #define BFI_MEM_SEG_FROM_TAG(_tag, _rqsz) ((_tag) / BFI_MEM_NREQS_SEG(_rqsz))
40
41 /* Get dma req offset in a segment */
42 #define BFI_MEM_SEG_REQ_OFFSET(_tag, _sz) \
43 ((_tag) - (BFI_MEM_SEG_FROM_TAG(_tag, _sz) * BFI_MEM_NREQS_SEG(_sz)))
44
45 /*
46 * BFI FW image type
47 */
48 #define BFI_FLASH_CHUNK_SZ 256 /* Flash chunk size */
49 #define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
50 #define BFI_FLASH_IMAGE_SZ 0x100000
51
52 /*
53 * Msg header common to all msgs
54 */
55 struct bfi_mhdr_s {
56 u8 msg_class; /* @ref bfi_mclass_t */
57 u8 msg_id; /* msg opcode with in the class */
58 union {
59 struct {
60 u8 qid;
61 u8 fn_lpu; /* msg destination */
62 } h2i;
63 u16 i2htok; /* token in msgs to host */
64 } mtag;
65 };
66
67 #define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu))
68 #define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1)
69
70 #define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do { \
71 (_mh).msg_class = (_mc); \
72 (_mh).msg_id = (_op); \
73 (_mh).mtag.h2i.fn_lpu = (_fn_lpu); \
74 } while (0)
75
76 #define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
77 (_mh).msg_class = (_mc); \
78 (_mh).msg_id = (_op); \
79 (_mh).mtag.i2htok = (_i2htok); \
80 } while (0)
81
82 /*
83 * Message opcodes: 0-127 to firmware, 128-255 to host
84 */
85 #define BFI_I2H_OPCODE_BASE 128
86 #define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
87
88 /*
89 ****************************************************************************
90 *
91 * Scatter Gather Element and Page definition
92 *
93 ****************************************************************************
94 */
95
96 #define BFI_SGE_INLINE 1
97 #define BFI_SGE_INLINE_MAX (BFI_SGE_INLINE + 1)
98
99 /*
100 * SG Flags
101 */
102 enum {
103 BFI_SGE_DATA = 0, /* data address, not last */
104 BFI_SGE_DATA_CPL = 1, /* data addr, last in current page */
105 BFI_SGE_DATA_LAST = 3, /* data address, last */
106 BFI_SGE_LINK = 2, /* link address */
107 BFI_SGE_PGDLEN = 2, /* cumulative data length for page */
108 };
109
110 /*
111 * DMA addresses
112 */
113 union bfi_addr_u {
114 struct {
115 __be32 addr_lo;
116 __be32 addr_hi;
117 } a32;
118 };
119
120 /*
121 * Scatter Gather Element used for fast-path IO requests
122 */
123 struct bfi_sge_s {
124 #ifdef __BIG_ENDIAN
125 u32 flags:2,
126 rsvd:2,
127 sg_len:28;
128 #else
129 u32 sg_len:28,
130 rsvd:2,
131 flags:2;
132 #endif
133 union bfi_addr_u sga;
134 };
135
136 /**
137 * Generic DMA addr-len pair.
138 */
139 struct bfi_alen_s {
140 union bfi_addr_u al_addr; /* DMA addr of buffer */
141 u32 al_len; /* length of buffer */
142 };
143
144 /*
145 * Scatter Gather Page
146 */
147 #define BFI_SGPG_DATA_SGES 7
148 #define BFI_SGPG_SGES_MAX (BFI_SGPG_DATA_SGES + 1)
149 #define BFI_SGPG_RSVD_WD_LEN 8
150 struct bfi_sgpg_s {
151 struct bfi_sge_s sges[BFI_SGPG_SGES_MAX];
152 u32 rsvd[BFI_SGPG_RSVD_WD_LEN];
153 };
154
155 /* FCP module definitions */
156 #define BFI_IO_MAX (2000)
157 #define BFI_IOIM_SNSLEN (256)
158 #define BFI_IOIM_SNSBUF_SEGS \
159 BFI_MEM_DMA_NSEGS(BFI_IO_MAX, BFI_IOIM_SNSLEN)
160
161 /*
162 * Large Message structure - 128 Bytes size Msgs
163 */
164 #define BFI_LMSG_SZ 128
165 #define BFI_LMSG_PL_WSZ \
166 ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr_s)) / 4)
167
168 struct bfi_msg_s {
169 struct bfi_mhdr_s mhdr;
170 u32 pl[BFI_LMSG_PL_WSZ];
171 };
172
173 /*
174 * Mailbox message structure
175 */
176 #define BFI_MBMSG_SZ 7
177 struct bfi_mbmsg_s {
178 struct bfi_mhdr_s mh;
179 u32 pl[BFI_MBMSG_SZ];
180 };
181
182 /*
183 * Supported PCI function class codes (personality)
184 */
185 enum bfi_pcifn_class {
186 BFI_PCIFN_CLASS_FC = 0x0c04,
187 BFI_PCIFN_CLASS_ETH = 0x0200,
188 };
189
190 /*
191 * Message Classes
192 */
193 enum bfi_mclass {
194 BFI_MC_IOC = 1, /* IO Controller (IOC) */
195 BFI_MC_DIAG = 2, /* Diagnostic Msgs */
196 BFI_MC_FLASH = 3, /* Flash message class */
197 BFI_MC_CEE = 4, /* CEE */
198 BFI_MC_FCPORT = 5, /* FC port */
199 BFI_MC_IOCFC = 6, /* FC - IO Controller (IOC) */
200 BFI_MC_ABLK = 7, /* ASIC block configuration */
201 BFI_MC_UF = 8, /* Unsolicited frame receive */
202 BFI_MC_FCXP = 9, /* FC Transport */
203 BFI_MC_LPS = 10, /* lport fc login services */
204 BFI_MC_RPORT = 11, /* Remote port */
205 BFI_MC_ITN = 12, /* I-T nexus (Initiator mode) */
206 BFI_MC_IOIM_READ = 13, /* read IO (Initiator mode) */
207 BFI_MC_IOIM_WRITE = 14, /* write IO (Initiator mode) */
208 BFI_MC_IOIM_IO = 15, /* IO (Initiator mode) */
209 BFI_MC_IOIM = 16, /* IO (Initiator mode) */
210 BFI_MC_IOIM_IOCOM = 17, /* good IO completion */
211 BFI_MC_TSKIM = 18, /* Initiator Task management */
212 BFI_MC_PORT = 21, /* Physical port */
213 BFI_MC_SFP = 22, /* SFP module */
214 BFI_MC_PHY = 25, /* External PHY message class */
215 BFI_MC_FRU = 34,
216 BFI_MC_MAX = 35
217 };
218
219 #define BFI_IOC_MAX_CQS 4
220 #define BFI_IOC_MAX_CQS_ASIC 8
221 #define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */
222
223 /*
224 *----------------------------------------------------------------------
225 * IOC
226 *----------------------------------------------------------------------
227 */
228
229 /*
230 * Different asic generations
231 */
232 enum bfi_asic_gen {
233 BFI_ASIC_GEN_CB = 1, /* crossbow 8G FC */
234 BFI_ASIC_GEN_CT = 2, /* catapult 8G FC or 10G CNA */
235 BFI_ASIC_GEN_CT2 = 3, /* catapult-2 16G FC or 10G CNA */
236 };
237
238 enum bfi_asic_mode {
239 BFI_ASIC_MODE_FC = 1, /* FC upto 8G speed */
240 BFI_ASIC_MODE_FC16 = 2, /* FC upto 16G speed */
241 BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */
242 BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */
243 };
244
245 enum bfi_ioc_h2i_msgs {
246 BFI_IOC_H2I_ENABLE_REQ = 1,
247 BFI_IOC_H2I_DISABLE_REQ = 2,
248 BFI_IOC_H2I_GETATTR_REQ = 3,
249 BFI_IOC_H2I_DBG_SYNC = 4,
250 BFI_IOC_H2I_DBG_DUMP = 5,
251 };
252
253 enum bfi_ioc_i2h_msgs {
254 BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
255 BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
256 BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
257 BFI_IOC_I2H_HBEAT = BFA_I2HM(4),
258 BFI_IOC_I2H_ACQ_ADDR_REPLY = BFA_I2HM(5),
259 };
260
261 /*
262 * BFI_IOC_H2I_GETATTR_REQ message
263 */
264 struct bfi_ioc_getattr_req_s {
265 struct bfi_mhdr_s mh;
266 union bfi_addr_u attr_addr;
267 };
268
269 #define BFI_IOC_ATTR_UUID_SZ 16
270 struct bfi_ioc_attr_s {
271 wwn_t mfg_pwwn; /* Mfg port wwn */
272 wwn_t mfg_nwwn; /* Mfg node wwn */
273 mac_t mfg_mac; /* Mfg mac */
274 u8 port_mode; /* bfi_port_mode */
275 u8 rsvd_a;
276 wwn_t pwwn;
277 wwn_t nwwn;
278 mac_t mac; /* PBC or Mfg mac */
279 u16 rsvd_b;
280 mac_t fcoe_mac;
281 u16 rsvd_c;
282 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
283 u8 pcie_gen;
284 u8 pcie_lanes_orig;
285 u8 pcie_lanes;
286 u8 rx_bbcredit; /* receive buffer credits */
287 u32 adapter_prop; /* adapter properties */
288 u16 maxfrsize; /* max receive frame size */
289 char asic_rev;
290 u8 rsvd_d;
291 char fw_version[BFA_VERSION_LEN];
292 char optrom_version[BFA_VERSION_LEN];
293 struct bfa_mfg_vpd_s vpd;
294 u32 card_type; /* card type */
295 u8 mfg_day; /* manufacturing day */
296 u8 mfg_month; /* manufacturing month */
297 u16 mfg_year; /* manufacturing year */
298 u8 uuid[BFI_IOC_ATTR_UUID_SZ]; /*!< chinook uuid */
299 };
300
301 /*
302 * BFI_IOC_I2H_GETATTR_REPLY message
303 */
304 struct bfi_ioc_getattr_reply_s {
305 struct bfi_mhdr_s mh; /* Common msg header */
306 u8 status; /* cfg reply status */
307 u8 rsvd[3];
308 };
309
310 /*
311 * Firmware memory page offsets
312 */
313 #define BFI_IOC_SMEM_PG0_CB (0x40)
314 #define BFI_IOC_SMEM_PG0_CT (0x180)
315
316 /*
317 * Firmware statistic offset
318 */
319 #define BFI_IOC_FWSTATS_OFF (0x6B40)
320 #define BFI_IOC_FWSTATS_SZ (4096)
321
322 /*
323 * Firmware trace offset
324 */
325 #define BFI_IOC_TRC_OFF (0x4b00)
326 #define BFI_IOC_TRC_ENTS 256
327
328 #define BFI_IOC_FW_SIGNATURE (0xbfadbfad)
329 #define BFA_IOC_FW_INV_SIGN (0xdeaddead)
330 #define BFI_IOC_MD5SUM_SZ 4
331
332 struct bfi_ioc_fwver_s {
333 #ifdef __BIG_ENDIAN
334 uint8_t patch;
335 uint8_t maint;
336 uint8_t minor;
337 uint8_t major;
338 uint8_t rsvd[2];
339 uint8_t build;
340 uint8_t phase;
341 #else
342 uint8_t major;
343 uint8_t minor;
344 uint8_t maint;
345 uint8_t patch;
346 uint8_t phase;
347 uint8_t build;
348 uint8_t rsvd[2];
349 #endif
350 };
351
352 struct bfi_ioc_image_hdr_s {
353 u32 signature; /* constant signature */
354 u8 asic_gen; /* asic generation */
355 u8 asic_mode;
356 u8 port0_mode; /* device mode for port 0 */
357 u8 port1_mode; /* device mode for port 1 */
358 u32 exec; /* exec vector */
359 u32 bootenv; /* firmware boot env */
360 u32 rsvd_b[2];
361 struct bfi_ioc_fwver_s fwver;
362 u32 md5sum[BFI_IOC_MD5SUM_SZ];
363 };
364
365 enum bfi_ioc_img_ver_cmp_e {
366 BFI_IOC_IMG_VER_INCOMP,
367 BFI_IOC_IMG_VER_OLD,
368 BFI_IOC_IMG_VER_SAME,
369 BFI_IOC_IMG_VER_BETTER
370 };
371
372 #define BFI_FWBOOT_DEVMODE_OFF 4
373 #define BFI_FWBOOT_TYPE_OFF 8
374 #define BFI_FWBOOT_ENV_OFF 12
375 #define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
376 (((u32)(__asic_gen)) << 24 | \
377 ((u32)(__asic_mode)) << 16 | \
378 ((u32)(__p0_mode)) << 8 | \
379 ((u32)(__p1_mode)))
380
381 enum bfi_fwboot_type {
382 BFI_FWBOOT_TYPE_NORMAL = 0,
383 BFI_FWBOOT_TYPE_FLASH = 1,
384 BFI_FWBOOT_TYPE_MEMTEST = 2,
385 };
386
387 #define BFI_FWBOOT_TYPE_NORMAL 0
388 #define BFI_FWBOOT_TYPE_MEMTEST 2
389 #define BFI_FWBOOT_ENV_OS 0
390
391 enum bfi_port_mode {
392 BFI_PORT_MODE_FC = 1,
393 BFI_PORT_MODE_ETH = 2,
394 };
395
396 struct bfi_ioc_hbeat_s {
397 struct bfi_mhdr_s mh; /* common msg header */
398 u32 hb_count; /* current heart beat count */
399 };
400
401 /*
402 * IOC hardware/firmware state
403 */
404 enum bfi_ioc_state {
405 BFI_IOC_UNINIT = 0, /* not initialized */
406 BFI_IOC_INITING = 1, /* h/w is being initialized */
407 BFI_IOC_HWINIT = 2, /* h/w is initialized */
408 BFI_IOC_CFG = 3, /* IOC configuration in progress */
409 BFI_IOC_OP = 4, /* IOC is operational */
410 BFI_IOC_DISABLING = 5, /* IOC is being disabled */
411 BFI_IOC_DISABLED = 6, /* IOC is disabled */
412 BFI_IOC_CFG_DISABLED = 7, /* IOC is being disabled;transient */
413 BFI_IOC_FAIL = 8, /* IOC heart-beat failure */
414 BFI_IOC_MEMTEST = 9, /* IOC is doing memtest */
415 };
416
417 #define BFA_IOC_CB_JOIN_SH 16
418 #define BFA_IOC_CB_FWSTATE_MASK 0x0000ffff
419 #define BFA_IOC_CB_JOIN_MASK 0xffff0000
420
421 #define BFI_IOC_ENDIAN_SIG 0x12345678
422
423 enum {
424 BFI_ADAPTER_TYPE_FC = 0x01, /* FC adapters */
425 BFI_ADAPTER_TYPE_MK = 0x0f0000, /* adapter type mask */
426 BFI_ADAPTER_TYPE_SH = 16, /* adapter type shift */
427 BFI_ADAPTER_NPORTS_MK = 0xff00, /* number of ports mask */
428 BFI_ADAPTER_NPORTS_SH = 8, /* number of ports shift */
429 BFI_ADAPTER_SPEED_MK = 0xff, /* adapter speed mask */
430 BFI_ADAPTER_SPEED_SH = 0, /* adapter speed shift */
431 BFI_ADAPTER_PROTO = 0x100000, /* prototype adapaters */
432 BFI_ADAPTER_TTV = 0x200000, /* TTV debug capable */
433 BFI_ADAPTER_UNSUPP = 0x400000, /* unknown adapter type */
434 };
435
436 #define BFI_ADAPTER_GETP(__prop, __adap_prop) \
437 (((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \
438 BFI_ADAPTER_ ## __prop ## _SH)
439 #define BFI_ADAPTER_SETP(__prop, __val) \
440 ((__val) << BFI_ADAPTER_ ## __prop ## _SH)
441 #define BFI_ADAPTER_IS_PROTO(__adap_type) \
442 ((__adap_type) & BFI_ADAPTER_PROTO)
443 #define BFI_ADAPTER_IS_TTV(__adap_type) \
444 ((__adap_type) & BFI_ADAPTER_TTV)
445 #define BFI_ADAPTER_IS_UNSUPP(__adap_type) \
446 ((__adap_type) & BFI_ADAPTER_UNSUPP)
447 #define BFI_ADAPTER_IS_SPECIAL(__adap_type) \
448 ((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \
449 BFI_ADAPTER_UNSUPP))
450
451 /*
452 * BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages
453 */
454 struct bfi_ioc_ctrl_req_s {
455 struct bfi_mhdr_s mh;
456 u16 clscode;
457 u16 rsvd;
458 u32 tv_sec;
459 };
460 #define bfi_ioc_enable_req_t struct bfi_ioc_ctrl_req_s;
461 #define bfi_ioc_disable_req_t struct bfi_ioc_ctrl_req_s;
462
463 /*
464 * BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages
465 */
466 struct bfi_ioc_ctrl_reply_s {
467 struct bfi_mhdr_s mh; /* Common msg header */
468 u8 status; /* enable/disable status */
469 u8 port_mode; /* bfa_mode_s */
470 u8 cap_bm; /* capability bit mask */
471 u8 rsvd;
472 };
473 #define bfi_ioc_enable_reply_t struct bfi_ioc_ctrl_reply_s;
474 #define bfi_ioc_disable_reply_t struct bfi_ioc_ctrl_reply_s;
475
476 #define BFI_IOC_MSGSZ 8
477 /*
478 * H2I Messages
479 */
480 union bfi_ioc_h2i_msg_u {
481 struct bfi_mhdr_s mh;
482 struct bfi_ioc_ctrl_req_s enable_req;
483 struct bfi_ioc_ctrl_req_s disable_req;
484 struct bfi_ioc_getattr_req_s getattr_req;
485 u32 mboxmsg[BFI_IOC_MSGSZ];
486 };
487
488 /*
489 * I2H Messages
490 */
491 union bfi_ioc_i2h_msg_u {
492 struct bfi_mhdr_s mh;
493 struct bfi_ioc_ctrl_reply_s fw_event;
494 u32 mboxmsg[BFI_IOC_MSGSZ];
495 };
496
497
498 /*
499 *----------------------------------------------------------------------
500 * PBC
501 *----------------------------------------------------------------------
502 */
503
504 #define BFI_PBC_MAX_BLUNS 8
505 #define BFI_PBC_MAX_VPORTS 16
506 #define BFI_PBC_PORT_DISABLED 2
507
508 /*
509 * PBC boot lun configuration
510 */
511 struct bfi_pbc_blun_s {
512 wwn_t tgt_pwwn;
513 struct scsi_lun tgt_lun;
514 };
515
516 /*
517 * PBC virtual port configuration
518 */
519 struct bfi_pbc_vport_s {
520 wwn_t vp_pwwn;
521 wwn_t vp_nwwn;
522 };
523
524 /*
525 * BFI pre-boot configuration information
526 */
527 struct bfi_pbc_s {
528 u8 port_enabled;
529 u8 boot_enabled;
530 u8 nbluns;
531 u8 nvports;
532 u8 port_speed;
533 u8 rsvd_a;
534 u16 hss;
535 wwn_t pbc_pwwn;
536 wwn_t pbc_nwwn;
537 struct bfi_pbc_blun_s blun[BFI_PBC_MAX_BLUNS];
538 struct bfi_pbc_vport_s vport[BFI_PBC_MAX_VPORTS];
539 };
540
541 /*
542 *----------------------------------------------------------------------
543 * MSGQ
544 *----------------------------------------------------------------------
545 */
546 #define BFI_MSGQ_FULL(_q) (((_q->pi + 1) % _q->q_depth) == _q->ci)
547 #define BFI_MSGQ_EMPTY(_q) (_q->pi == _q->ci)
548 #define BFI_MSGQ_UPDATE_CI(_q) (_q->ci = (_q->ci + 1) % _q->q_depth)
549 #define BFI_MSGQ_UPDATE_PI(_q) (_q->pi = (_q->pi + 1) % _q->q_depth)
550
551 /* q_depth must be power of 2 */
552 #define BFI_MSGQ_FREE_CNT(_q) ((_q->ci - _q->pi - 1) & (_q->q_depth - 1))
553
554 enum bfi_msgq_h2i_msgs_e {
555 BFI_MSGQ_H2I_INIT_REQ = 1,
556 BFI_MSGQ_H2I_DOORBELL = 2,
557 BFI_MSGQ_H2I_SHUTDOWN = 3,
558 };
559
560 enum bfi_msgq_i2h_msgs_e {
561 BFI_MSGQ_I2H_INIT_RSP = 1,
562 BFI_MSGQ_I2H_DOORBELL = 2,
563 };
564
565
566 /* Messages(commands/responsed/AENS will have the following header */
567 struct bfi_msgq_mhdr_s {
568 u8 msg_class;
569 u8 msg_id;
570 u16 msg_token;
571 u16 num_entries;
572 u8 enet_id;
573 u8 rsvd[1];
574 };
575
576 #define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \
577 (_mh).msg_class = (_mc); \
578 (_mh).msg_id = (_mid); \
579 (_mh).msg_token = (_tok); \
580 (_mh).enet_id = (_enet_id); \
581 } while (0)
582
583 /*
584 * Mailbox for messaging interface
585 *
586 */
587 #define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */
588 #define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */
589 #define BFI_MSGQ_MSG_SIZE_MAX (2048) /* TBD */
590
591 struct bfi_msgq_s {
592 union bfi_addr_u addr;
593 u16 q_depth; /* Total num of entries in the queue */
594 u8 rsvd[2];
595 };
596
597 /* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
598 struct bfi_msgq_cfg_req_s {
599 struct bfi_mhdr_s mh;
600 struct bfi_msgq_s cmdq;
601 struct bfi_msgq_s rspq;
602 };
603
604 /* BFI_ENET_MSGQ_CFG_RSP */
605 struct bfi_msgq_cfg_rsp_s {
606 struct bfi_mhdr_s mh;
607 u8 cmd_status;
608 u8 rsvd[3];
609 };
610
611
612 /* BFI_MSGQ_H2I_DOORBELL */
613 struct bfi_msgq_h2i_db_s {
614 struct bfi_mhdr_s mh;
615 u16 cmdq_pi;
616 u16 rspq_ci;
617 };
618
619 /* BFI_MSGQ_I2H_DOORBELL */
620 struct bfi_msgq_i2h_db_s {
621 struct bfi_mhdr_s mh;
622 u16 rspq_pi;
623 u16 cmdq_ci;
624 };
625
626 #pragma pack()
627
628 /* BFI port specific */
629 #pragma pack(1)
630
631 enum bfi_port_h2i {
632 BFI_PORT_H2I_ENABLE_REQ = (1),
633 BFI_PORT_H2I_DISABLE_REQ = (2),
634 BFI_PORT_H2I_GET_STATS_REQ = (3),
635 BFI_PORT_H2I_CLEAR_STATS_REQ = (4),
636 };
637
638 enum bfi_port_i2h {
639 BFI_PORT_I2H_ENABLE_RSP = BFA_I2HM(1),
640 BFI_PORT_I2H_DISABLE_RSP = BFA_I2HM(2),
641 BFI_PORT_I2H_GET_STATS_RSP = BFA_I2HM(3),
642 BFI_PORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(4),
643 };
644
645 /*
646 * Generic REQ type
647 */
648 struct bfi_port_generic_req_s {
649 struct bfi_mhdr_s mh; /* msg header */
650 u32 msgtag; /* msgtag for reply */
651 u32 rsvd;
652 };
653
654 /*
655 * Generic RSP type
656 */
657 struct bfi_port_generic_rsp_s {
658 struct bfi_mhdr_s mh; /* common msg header */
659 u8 status; /* port enable status */
660 u8 rsvd[3];
661 u32 msgtag; /* msgtag for reply */
662 };
663
664 /*
665 * BFI_PORT_H2I_GET_STATS_REQ
666 */
667 struct bfi_port_get_stats_req_s {
668 struct bfi_mhdr_s mh; /* common msg header */
669 union bfi_addr_u dma_addr;
670 };
671
672 union bfi_port_h2i_msg_u {
673 struct bfi_mhdr_s mh;
674 struct bfi_port_generic_req_s enable_req;
675 struct bfi_port_generic_req_s disable_req;
676 struct bfi_port_get_stats_req_s getstats_req;
677 struct bfi_port_generic_req_s clearstats_req;
678 };
679
680 union bfi_port_i2h_msg_u {
681 struct bfi_mhdr_s mh;
682 struct bfi_port_generic_rsp_s enable_rsp;
683 struct bfi_port_generic_rsp_s disable_rsp;
684 struct bfi_port_generic_rsp_s getstats_rsp;
685 struct bfi_port_generic_rsp_s clearstats_rsp;
686 };
687
688 /*
689 *----------------------------------------------------------------------
690 * ABLK
691 *----------------------------------------------------------------------
692 */
693 enum bfi_ablk_h2i_msgs_e {
694 BFI_ABLK_H2I_QUERY = 1,
695 BFI_ABLK_H2I_ADPT_CONFIG = 2,
696 BFI_ABLK_H2I_PORT_CONFIG = 3,
697 BFI_ABLK_H2I_PF_CREATE = 4,
698 BFI_ABLK_H2I_PF_DELETE = 5,
699 BFI_ABLK_H2I_PF_UPDATE = 6,
700 BFI_ABLK_H2I_OPTROM_ENABLE = 7,
701 BFI_ABLK_H2I_OPTROM_DISABLE = 8,
702 };
703
704 enum bfi_ablk_i2h_msgs_e {
705 BFI_ABLK_I2H_QUERY = BFA_I2HM(BFI_ABLK_H2I_QUERY),
706 BFI_ABLK_I2H_ADPT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_ADPT_CONFIG),
707 BFI_ABLK_I2H_PORT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_PORT_CONFIG),
708 BFI_ABLK_I2H_PF_CREATE = BFA_I2HM(BFI_ABLK_H2I_PF_CREATE),
709 BFI_ABLK_I2H_PF_DELETE = BFA_I2HM(BFI_ABLK_H2I_PF_DELETE),
710 BFI_ABLK_I2H_PF_UPDATE = BFA_I2HM(BFI_ABLK_H2I_PF_UPDATE),
711 BFI_ABLK_I2H_OPTROM_ENABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_ENABLE),
712 BFI_ABLK_I2H_OPTROM_DISABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_DISABLE),
713 };
714
715 /* BFI_ABLK_H2I_QUERY */
716 struct bfi_ablk_h2i_query_s {
717 struct bfi_mhdr_s mh;
718 union bfi_addr_u addr;
719 };
720
721 /* BFI_ABL_H2I_ADPT_CONFIG, BFI_ABLK_H2I_PORT_CONFIG */
722 struct bfi_ablk_h2i_cfg_req_s {
723 struct bfi_mhdr_s mh;
724 u8 mode;
725 u8 port;
726 u8 max_pf;
727 u8 max_vf;
728 };
729
730 /*
731 * BFI_ABLK_H2I_PF_CREATE, BFI_ABLK_H2I_PF_DELETE,
732 */
733 struct bfi_ablk_h2i_pf_req_s {
734 struct bfi_mhdr_s mh;
735 u8 pcifn;
736 u8 port;
737 u16 pers;
738 u16 bw_min; /* percent BW @ max speed */
739 u16 bw_max; /* percent BW @ max speed */
740 };
741
742 /* BFI_ABLK_H2I_OPTROM_ENABLE, BFI_ABLK_H2I_OPTROM_DISABLE */
743 struct bfi_ablk_h2i_optrom_s {
744 struct bfi_mhdr_s mh;
745 };
746
747 /*
748 * BFI_ABLK_I2H_QUERY
749 * BFI_ABLK_I2H_PORT_CONFIG
750 * BFI_ABLK_I2H_PF_CREATE
751 * BFI_ABLK_I2H_PF_DELETE
752 * BFI_ABLK_I2H_PF_UPDATE
753 * BFI_ABLK_I2H_OPTROM_ENABLE
754 * BFI_ABLK_I2H_OPTROM_DISABLE
755 */
756 struct bfi_ablk_i2h_rsp_s {
757 struct bfi_mhdr_s mh;
758 u8 status;
759 u8 pcifn;
760 u8 port_mode;
761 };
762
763
764 /*
765 * CEE module specific messages
766 */
767
768 /* Mailbox commands from host to firmware */
769 enum bfi_cee_h2i_msgs_e {
770 BFI_CEE_H2I_GET_CFG_REQ = 1,
771 BFI_CEE_H2I_RESET_STATS = 2,
772 BFI_CEE_H2I_GET_STATS_REQ = 3,
773 };
774
775 enum bfi_cee_i2h_msgs_e {
776 BFI_CEE_I2H_GET_CFG_RSP = BFA_I2HM(1),
777 BFI_CEE_I2H_RESET_STATS_RSP = BFA_I2HM(2),
778 BFI_CEE_I2H_GET_STATS_RSP = BFA_I2HM(3),
779 };
780
781 /*
782 * H2I command structure for resetting the stats
783 */
784 struct bfi_cee_reset_stats_s {
785 struct bfi_mhdr_s mh;
786 };
787
788 /*
789 * Get configuration command from host
790 */
791 struct bfi_cee_get_req_s {
792 struct bfi_mhdr_s mh;
793 union bfi_addr_u dma_addr;
794 };
795
796 /*
797 * Reply message from firmware
798 */
799 struct bfi_cee_get_rsp_s {
800 struct bfi_mhdr_s mh;
801 u8 cmd_status;
802 u8 rsvd[3];
803 };
804
805 /*
806 * Reply message from firmware
807 */
808 struct bfi_cee_stats_rsp_s {
809 struct bfi_mhdr_s mh;
810 u8 cmd_status;
811 u8 rsvd[3];
812 };
813
814 /* Mailbox message structures from firmware to host */
815 union bfi_cee_i2h_msg_u {
816 struct bfi_mhdr_s mh;
817 struct bfi_cee_get_rsp_s get_rsp;
818 struct bfi_cee_stats_rsp_s stats_rsp;
819 };
820
821 /*
822 * SFP related
823 */
824
825 enum bfi_sfp_h2i_e {
826 BFI_SFP_H2I_SHOW = 1,
827 BFI_SFP_H2I_SCN = 2,
828 };
829
830 enum bfi_sfp_i2h_e {
831 BFI_SFP_I2H_SHOW = BFA_I2HM(BFI_SFP_H2I_SHOW),
832 BFI_SFP_I2H_SCN = BFA_I2HM(BFI_SFP_H2I_SCN),
833 };
834
835 /*
836 * SFP state change notification
837 */
838 struct bfi_sfp_scn_s {
839 struct bfi_mhdr_s mhr; /* host msg header */
840 u8 event;
841 u8 sfpid;
842 u8 pomlvl; /* pom level: normal/warning/alarm */
843 u8 is_elb; /* e-loopback */
844 };
845
846 /*
847 * SFP state
848 */
849 enum bfa_sfp_stat_e {
850 BFA_SFP_STATE_INIT = 0, /* SFP state is uninit */
851 BFA_SFP_STATE_REMOVED = 1, /* SFP is removed */
852 BFA_SFP_STATE_INSERTED = 2, /* SFP is inserted */
853 BFA_SFP_STATE_VALID = 3, /* SFP is valid */
854 BFA_SFP_STATE_UNSUPPORT = 4, /* SFP is unsupport */
855 BFA_SFP_STATE_FAILED = 5, /* SFP i2c read fail */
856 };
857
858 /*
859 * SFP memory access type
860 */
861 enum bfi_sfp_mem_e {
862 BFI_SFP_MEM_ALL = 0x1, /* access all data field */
863 BFI_SFP_MEM_DIAGEXT = 0x2, /* access diag ext data field only */
864 };
865
866 struct bfi_sfp_req_s {
867 struct bfi_mhdr_s mh;
868 u8 memtype;
869 u8 rsvd[3];
870 struct bfi_alen_s alen;
871 };
872
873 struct bfi_sfp_rsp_s {
874 struct bfi_mhdr_s mh;
875 u8 status;
876 u8 state;
877 u8 rsvd[2];
878 };
879
880 /*
881 * FLASH module specific
882 */
883 enum bfi_flash_h2i_msgs {
884 BFI_FLASH_H2I_QUERY_REQ = 1,
885 BFI_FLASH_H2I_ERASE_REQ = 2,
886 BFI_FLASH_H2I_WRITE_REQ = 3,
887 BFI_FLASH_H2I_READ_REQ = 4,
888 BFI_FLASH_H2I_BOOT_VER_REQ = 5,
889 };
890
891 enum bfi_flash_i2h_msgs {
892 BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1),
893 BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2),
894 BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3),
895 BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4),
896 BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5),
897 BFI_FLASH_I2H_EVENT = BFA_I2HM(127),
898 };
899
900 /*
901 * Flash query request
902 */
903 struct bfi_flash_query_req_s {
904 struct bfi_mhdr_s mh; /* Common msg header */
905 struct bfi_alen_s alen;
906 };
907
908 /*
909 * Flash erase request
910 */
911 struct bfi_flash_erase_req_s {
912 struct bfi_mhdr_s mh; /* Common msg header */
913 u32 type; /* partition type */
914 u8 instance; /* partition instance */
915 u8 rsv[3];
916 };
917
918 /*
919 * Flash write request
920 */
921 struct bfi_flash_write_req_s {
922 struct bfi_mhdr_s mh; /* Common msg header */
923 struct bfi_alen_s alen;
924 u32 type; /* partition type */
925 u8 instance; /* partition instance */
926 u8 last;
927 u8 rsv[2];
928 u32 offset;
929 u32 length;
930 };
931
932 /*
933 * Flash read request
934 */
935 struct bfi_flash_read_req_s {
936 struct bfi_mhdr_s mh; /* Common msg header */
937 u32 type; /* partition type */
938 u8 instance; /* partition instance */
939 u8 rsv[3];
940 u32 offset;
941 u32 length;
942 struct bfi_alen_s alen;
943 };
944
945 /*
946 * Flash query response
947 */
948 struct bfi_flash_query_rsp_s {
949 struct bfi_mhdr_s mh; /* Common msg header */
950 u32 status;
951 };
952
953 /*
954 * Flash read response
955 */
956 struct bfi_flash_read_rsp_s {
957 struct bfi_mhdr_s mh; /* Common msg header */
958 u32 type; /* partition type */
959 u8 instance; /* partition instance */
960 u8 rsv[3];
961 u32 status;
962 u32 length;
963 };
964
965 /*
966 * Flash write response
967 */
968 struct bfi_flash_write_rsp_s {
969 struct bfi_mhdr_s mh; /* Common msg header */
970 u32 type; /* partition type */
971 u8 instance; /* partition instance */
972 u8 rsv[3];
973 u32 status;
974 u32 length;
975 };
976
977 /*
978 * Flash erase response
979 */
980 struct bfi_flash_erase_rsp_s {
981 struct bfi_mhdr_s mh; /* Common msg header */
982 u32 type; /* partition type */
983 u8 instance; /* partition instance */
984 u8 rsv[3];
985 u32 status;
986 };
987
988 /*
989 * Flash event notification
990 */
991 struct bfi_flash_event_s {
992 struct bfi_mhdr_s mh; /* Common msg header */
993 bfa_status_t status;
994 u32 param;
995 };
996
997 /*
998 *----------------------------------------------------------------------
999 * DIAG
1000 *----------------------------------------------------------------------
1001 */
1002 enum bfi_diag_h2i {
1003 BFI_DIAG_H2I_PORTBEACON = 1,
1004 BFI_DIAG_H2I_LOOPBACK = 2,
1005 BFI_DIAG_H2I_FWPING = 3,
1006 BFI_DIAG_H2I_TEMPSENSOR = 4,
1007 BFI_DIAG_H2I_LEDTEST = 5,
1008 BFI_DIAG_H2I_QTEST = 6,
1009 BFI_DIAG_H2I_DPORT = 7,
1010 };
1011
1012 enum bfi_diag_i2h {
1013 BFI_DIAG_I2H_PORTBEACON = BFA_I2HM(BFI_DIAG_H2I_PORTBEACON),
1014 BFI_DIAG_I2H_LOOPBACK = BFA_I2HM(BFI_DIAG_H2I_LOOPBACK),
1015 BFI_DIAG_I2H_FWPING = BFA_I2HM(BFI_DIAG_H2I_FWPING),
1016 BFI_DIAG_I2H_TEMPSENSOR = BFA_I2HM(BFI_DIAG_H2I_TEMPSENSOR),
1017 BFI_DIAG_I2H_LEDTEST = BFA_I2HM(BFI_DIAG_H2I_LEDTEST),
1018 BFI_DIAG_I2H_QTEST = BFA_I2HM(BFI_DIAG_H2I_QTEST),
1019 BFI_DIAG_I2H_DPORT = BFA_I2HM(BFI_DIAG_H2I_DPORT),
1020 BFI_DIAG_I2H_DPORT_SCN = BFA_I2HM(8),
1021 };
1022
1023 #define BFI_DIAG_MAX_SGES 2
1024 #define BFI_DIAG_DMA_BUF_SZ (2 * 1024)
1025 #define BFI_BOOT_MEMTEST_RES_ADDR 0x900
1026 #define BFI_BOOT_MEMTEST_RES_SIG 0xA0A1A2A3
1027
1028 struct bfi_diag_lb_req_s {
1029 struct bfi_mhdr_s mh;
1030 u32 loopcnt;
1031 u32 pattern;
1032 u8 lb_mode; /*!< bfa_port_opmode_t */
1033 u8 speed; /*!< bfa_port_speed_t */
1034 u8 rsvd[2];
1035 };
1036
1037 struct bfi_diag_lb_rsp_s {
1038 struct bfi_mhdr_s mh; /* 4 bytes */
1039 struct bfa_diag_loopback_result_s res; /* 16 bytes */
1040 };
1041
1042 struct bfi_diag_fwping_req_s {
1043 struct bfi_mhdr_s mh; /* 4 bytes */
1044 struct bfi_alen_s alen; /* 12 bytes */
1045 u32 data; /* user input data pattern */
1046 u32 count; /* user input dma count */
1047 u8 qtag; /* track CPE vc */
1048 u8 rsv[3];
1049 };
1050
1051 struct bfi_diag_fwping_rsp_s {
1052 struct bfi_mhdr_s mh; /* 4 bytes */
1053 u32 data; /* user input data pattern */
1054 u8 qtag; /* track CPE vc */
1055 u8 dma_status; /* dma status */
1056 u8 rsv[2];
1057 };
1058
1059 /*
1060 * Temperature Sensor
1061 */
1062 struct bfi_diag_ts_req_s {
1063 struct bfi_mhdr_s mh; /* 4 bytes */
1064 u16 temp; /* 10-bit A/D value */
1065 u16 brd_temp; /* 9-bit board temp */
1066 u8 status;
1067 u8 ts_junc; /* show junction tempsensor */
1068 u8 ts_brd; /* show board tempsensor */
1069 u8 rsv;
1070 };
1071 #define bfi_diag_ts_rsp_t struct bfi_diag_ts_req_s
1072
1073 struct bfi_diag_ledtest_req_s {
1074 struct bfi_mhdr_s mh; /* 4 bytes */
1075 u8 cmd;
1076 u8 color;
1077 u8 portid;
1078 u8 led; /* bitmap of LEDs to be tested */
1079 u16 freq; /* no. of blinks every 10 secs */
1080 u8 rsv[2];
1081 };
1082
1083 /* notify host led operation is done */
1084 struct bfi_diag_ledtest_rsp_s {
1085 struct bfi_mhdr_s mh; /* 4 bytes */
1086 };
1087
1088 struct bfi_diag_portbeacon_req_s {
1089 struct bfi_mhdr_s mh; /* 4 bytes */
1090 u32 period; /* beaconing period */
1091 u8 beacon; /* 1: beacon on */
1092 u8 rsvd[3];
1093 };
1094
1095 /* notify host the beacon is off */
1096 struct bfi_diag_portbeacon_rsp_s {
1097 struct bfi_mhdr_s mh; /* 4 bytes */
1098 };
1099
1100 struct bfi_diag_qtest_req_s {
1101 struct bfi_mhdr_s mh; /* 4 bytes */
1102 u32 data[BFI_LMSG_PL_WSZ]; /* fill up tcm prefetch area */
1103 };
1104 #define bfi_diag_qtest_rsp_t struct bfi_diag_qtest_req_s
1105
1106 /*
1107 * D-port test
1108 */
1109 enum bfi_dport_req {
1110 BFI_DPORT_DISABLE = 0, /* disable dport request */
1111 BFI_DPORT_ENABLE = 1, /* enable dport request */
1112 BFI_DPORT_START = 2, /* start dport request */
1113 BFI_DPORT_SHOW = 3, /* show dport request */
1114 BFI_DPORT_DYN_DISABLE = 4, /* disable dynamic dport request */
1115 };
1116
1117 enum bfi_dport_scn {
1118 BFI_DPORT_SCN_TESTSTART = 1,
1119 BFI_DPORT_SCN_TESTCOMP = 2,
1120 BFI_DPORT_SCN_SFP_REMOVED = 3,
1121 BFI_DPORT_SCN_DDPORT_ENABLE = 4,
1122 BFI_DPORT_SCN_DDPORT_DISABLE = 5,
1123 BFI_DPORT_SCN_FCPORT_DISABLE = 6,
1124 BFI_DPORT_SCN_SUBTESTSTART = 7,
1125 BFI_DPORT_SCN_TESTSKIP = 8,
1126 BFI_DPORT_SCN_DDPORT_DISABLED = 9,
1127 };
1128
1129 struct bfi_diag_dport_req_s {
1130 struct bfi_mhdr_s mh; /* 4 bytes */
1131 u8 req; /* request 1: enable 0: disable */
1132 u8 rsvd[3];
1133 u32 lpcnt;
1134 u32 payload;
1135 };
1136
1137 struct bfi_diag_dport_rsp_s {
1138 struct bfi_mhdr_s mh; /* header 4 bytes */
1139 bfa_status_t status; /* reply status */
1140 wwn_t pwwn; /* switch port wwn. 8 bytes */
1141 wwn_t nwwn; /* switch node wwn. 8 bytes */
1142 };
1143
1144 struct bfi_diag_dport_scn_teststart_s {
1145 wwn_t pwwn; /* switch port wwn. 8 bytes */
1146 wwn_t nwwn; /* switch node wwn. 8 bytes */
1147 u8 type; /* bfa_diag_dport_test_type_e */
1148 u8 mode; /* bfa_diag_dport_test_opmode */
1149 u8 rsvd[2];
1150 u32 numfrm; /* from switch uint in 1M */
1151 };
1152
1153 struct bfi_diag_dport_scn_testcomp_s {
1154 u8 status; /* bfa_diag_dport_test_status_e */
1155 u8 speed; /* bfa_port_speed_t */
1156 u16 numbuffer; /* from switch */
1157 u8 subtest_status[DPORT_TEST_MAX]; /* 4 bytes */
1158 u32 latency; /* from switch */
1159 u32 distance; /* from swtich unit in meters */
1160 /* Buffers required to saturate the link */
1161 u16 frm_sz; /* from switch for buf_reqd */
1162 u8 rsvd[2];
1163 };
1164
1165 struct bfi_diag_dport_scn_s { /* max size == RDS_RMESZ */
1166 struct bfi_mhdr_s mh; /* header 4 bytes */
1167 u8 state; /* new state */
1168 u8 rsvd[3];
1169 union {
1170 struct bfi_diag_dport_scn_teststart_s teststart;
1171 struct bfi_diag_dport_scn_testcomp_s testcomp;
1172 } info;
1173 };
1174
1175 union bfi_diag_dport_msg_u {
1176 struct bfi_diag_dport_req_s req;
1177 struct bfi_diag_dport_rsp_s rsp;
1178 struct bfi_diag_dport_scn_s scn;
1179 };
1180
1181 /*
1182 * PHY module specific
1183 */
1184 enum bfi_phy_h2i_msgs_e {
1185 BFI_PHY_H2I_QUERY_REQ = 1,
1186 BFI_PHY_H2I_STATS_REQ = 2,
1187 BFI_PHY_H2I_WRITE_REQ = 3,
1188 BFI_PHY_H2I_READ_REQ = 4,
1189 };
1190
1191 enum bfi_phy_i2h_msgs_e {
1192 BFI_PHY_I2H_QUERY_RSP = BFA_I2HM(1),
1193 BFI_PHY_I2H_STATS_RSP = BFA_I2HM(2),
1194 BFI_PHY_I2H_WRITE_RSP = BFA_I2HM(3),
1195 BFI_PHY_I2H_READ_RSP = BFA_I2HM(4),
1196 };
1197
1198 /*
1199 * External PHY query request
1200 */
1201 struct bfi_phy_query_req_s {
1202 struct bfi_mhdr_s mh; /* Common msg header */
1203 u8 instance;
1204 u8 rsv[3];
1205 struct bfi_alen_s alen;
1206 };
1207
1208 /*
1209 * External PHY stats request
1210 */
1211 struct bfi_phy_stats_req_s {
1212 struct bfi_mhdr_s mh; /* Common msg header */
1213 u8 instance;
1214 u8 rsv[3];
1215 struct bfi_alen_s alen;
1216 };
1217
1218 /*
1219 * External PHY write request
1220 */
1221 struct bfi_phy_write_req_s {
1222 struct bfi_mhdr_s mh; /* Common msg header */
1223 u8 instance;
1224 u8 last;
1225 u8 rsv[2];
1226 u32 offset;
1227 u32 length;
1228 struct bfi_alen_s alen;
1229 };
1230
1231 /*
1232 * External PHY read request
1233 */
1234 struct bfi_phy_read_req_s {
1235 struct bfi_mhdr_s mh; /* Common msg header */
1236 u8 instance;
1237 u8 rsv[3];
1238 u32 offset;
1239 u32 length;
1240 struct bfi_alen_s alen;
1241 };
1242
1243 /*
1244 * External PHY query response
1245 */
1246 struct bfi_phy_query_rsp_s {
1247 struct bfi_mhdr_s mh; /* Common msg header */
1248 u32 status;
1249 };
1250
1251 /*
1252 * External PHY stats response
1253 */
1254 struct bfi_phy_stats_rsp_s {
1255 struct bfi_mhdr_s mh; /* Common msg header */
1256 u32 status;
1257 };
1258
1259 /*
1260 * External PHY read response
1261 */
1262 struct bfi_phy_read_rsp_s {
1263 struct bfi_mhdr_s mh; /* Common msg header */
1264 u32 status;
1265 u32 length;
1266 };
1267
1268 /*
1269 * External PHY write response
1270 */
1271 struct bfi_phy_write_rsp_s {
1272 struct bfi_mhdr_s mh; /* Common msg header */
1273 u32 status;
1274 u32 length;
1275 };
1276
1277 enum bfi_fru_h2i_msgs {
1278 BFI_FRUVPD_H2I_WRITE_REQ = 1,
1279 BFI_FRUVPD_H2I_READ_REQ = 2,
1280 BFI_TFRU_H2I_WRITE_REQ = 3,
1281 BFI_TFRU_H2I_READ_REQ = 4,
1282 };
1283
1284 enum bfi_fru_i2h_msgs {
1285 BFI_FRUVPD_I2H_WRITE_RSP = BFA_I2HM(1),
1286 BFI_FRUVPD_I2H_READ_RSP = BFA_I2HM(2),
1287 BFI_TFRU_I2H_WRITE_RSP = BFA_I2HM(3),
1288 BFI_TFRU_I2H_READ_RSP = BFA_I2HM(4),
1289 };
1290
1291 /*
1292 * FRU write request
1293 */
1294 struct bfi_fru_write_req_s {
1295 struct bfi_mhdr_s mh; /* Common msg header */
1296 u8 last;
1297 u8 rsv_1[3];
1298 u8 trfr_cmpl;
1299 u8 rsv_2[3];
1300 u32 offset;
1301 u32 length;
1302 struct bfi_alen_s alen;
1303 };
1304
1305 /*
1306 * FRU read request
1307 */
1308 struct bfi_fru_read_req_s {
1309 struct bfi_mhdr_s mh; /* Common msg header */
1310 u32 offset;
1311 u32 length;
1312 struct bfi_alen_s alen;
1313 };
1314
1315 /*
1316 * FRU response
1317 */
1318 struct bfi_fru_rsp_s {
1319 struct bfi_mhdr_s mh; /* Common msg header */
1320 u32 status;
1321 u32 length;
1322 };
1323 #pragma pack()
1324
1325 #endif /* __BFI_H__ */
Linux with added FPC-III support