arch/arm/mach-zynq/common.h

   1 /*
   2  * This file contains common function prototypes to avoid externs
   3  * in the c files.
   4  *
   5  *  Copyright (C) 2011 Xilinx
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef __MACH_ZYNQ_COMMON_H__
  18 #define __MACH_ZYNQ_COMMON_H__
  19
  20 extern int zynq_slcr_init(void);
  21 extern int zynq_early_slcr_init(void);
  22 extern void zynq_slcr_cpu_stop(int cpu);
  23 extern void zynq_slcr_cpu_start(int cpu);
  24 extern bool zynq_slcr_cpu_state_read(int cpu);
  25 extern void zynq_slcr_cpu_state_write(int cpu, bool die);
  26 extern u32 zynq_slcr_get_device_id(void);
  27
  28 #ifdef CONFIG_SMP
  29 extern char zynq_secondary_trampoline;
  30 extern char zynq_secondary_trampoline_jump;
  31 extern char zynq_secondary_trampoline_end;
  32 extern int zynq_cpun_start(u32 address, int cpu);
  33 extern struct smp_operations zynq_smp_ops __initdata;
  34 #endif
  35
  36 extern void __iomem *zynq_scu_base;
  37
  38 void zynq_pm_late_init(void);
  39
  40 static inline void zynq_core_pm_init(void)
  41 {
  42         /* A9 clock gating */
  43         asm volatile ("mrc  p15, 0, r12, c15, c0, 0\n"
  44                       "orr  r12, r12, #1\n"
  45                       "mcr  p15, 0, r12, c15, c0, 0\n"
  46                       : /* no outputs */
  47                       : /* no inputs */
  48                       : "r12");
  49 }
  50
  51 #endif