drivers/gpio/gpio-mt7621.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   4  * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
   5  */
   6
   7 #include <linux/err.h>
   8 #include <linux/gpio/driver.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spinlock.h>
  15
  16 #define MTK_BANK_CNT    3
  17 #define MTK_BANK_WIDTH  32
  18
  19 #define GPIO_BANK_STRIDE        0x04
  20 #define GPIO_REG_CTRL           0x00
  21 #define GPIO_REG_POL            0x10
  22 #define GPIO_REG_DATA           0x20
  23 #define GPIO_REG_DSET           0x30
  24 #define GPIO_REG_DCLR           0x40
  25 #define GPIO_REG_REDGE          0x50
  26 #define GPIO_REG_FEDGE          0x60
  27 #define GPIO_REG_HLVL           0x70
  28 #define GPIO_REG_LLVL           0x80
  29 #define GPIO_REG_STAT           0x90
  30 #define GPIO_REG_EDGE           0xA0
  31
  32 struct mtk_gc {
  33         struct irq_chip irq_chip;
  34         struct gpio_chip chip;
  35         spinlock_t lock;
  36         int bank;
  37         u32 rising;
  38         u32 falling;
  39         u32 hlevel;
  40         u32 llevel;
  41 };
  42
  43 /**
  44  * struct mtk - state container for
  45  * data of the platform driver. It is 3
  46  * separate gpio-chip each one with its
  47  * own irq_chip.
  48  * @dev: device instance
  49  * @base: memory base address
  50  * @gpio_irq: irq number from the device tree
  51  * @gc_map: array of the gpio chips
  52  */
  53 struct mtk {
  54         struct device *dev;
  55         void __iomem *base;
  56         int gpio_irq;
  57         struct mtk_gc gc_map[MTK_BANK_CNT];
  58 };
  59
  60 static inline struct mtk_gc *
  61 to_mediatek_gpio(struct gpio_chip *chip)
  62 {
  63         return container_of(chip, struct mtk_gc, chip);
  64 }
  65
  66 static inline void
  67 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
  68 {
  69         struct gpio_chip *gc = &rg->chip;
  70         struct mtk *mtk = gpiochip_get_data(gc);
  71
  72         offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
  73         gc->write_reg(mtk->base + offset, val);
  74 }
  75
  76 static inline u32
  77 mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
  78 {
  79         struct gpio_chip *gc = &rg->chip;
  80         struct mtk *mtk = gpiochip_get_data(gc);
  81
  82         offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
  83         return gc->read_reg(mtk->base + offset);
  84 }
  85
  86 static irqreturn_t
  87 mediatek_gpio_irq_handler(int irq, void *data)
  88 {
  89         struct gpio_chip *gc = data;
  90         struct mtk_gc *rg = to_mediatek_gpio(gc);
  91         irqreturn_t ret = IRQ_NONE;
  92         unsigned long pending;
  93         int bit;
  94
  95         pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
  96
  97         for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
  98                 u32 map = irq_find_mapping(gc->irq.domain, bit);
  99
 100                 generic_handle_irq(map);
 101                 mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
 102                 ret |= IRQ_HANDLED;
 103         }
 104
 105         return ret;
 106 }
 107
 108 static void
 109 mediatek_gpio_irq_unmask(struct irq_data *d)
 110 {
 111         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 112         struct mtk_gc *rg = to_mediatek_gpio(gc);
 113         int pin = d->hwirq;
 114         unsigned long flags;
 115         u32 rise, fall, high, low;
 116
 117         spin_lock_irqsave(&rg->lock, flags);
 118         rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
 119         fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
 120         high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
 121         low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
 122         mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
 123         mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
 124         mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
 125         mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
 126         spin_unlock_irqrestore(&rg->lock, flags);
 127 }
 128
 129 static void
 130 mediatek_gpio_irq_mask(struct irq_data *d)
 131 {
 132         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 133         struct mtk_gc *rg = to_mediatek_gpio(gc);
 134         int pin = d->hwirq;
 135         unsigned long flags;
 136         u32 rise, fall, high, low;
 137
 138         spin_lock_irqsave(&rg->lock, flags);
 139         rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
 140         fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
 141         high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
 142         low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
 143         mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
 144         mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
 145         mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
 146         mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
 147         spin_unlock_irqrestore(&rg->lock, flags);
 148 }
 149
 150 static int
 151 mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
 152 {
 153         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 154         struct mtk_gc *rg = to_mediatek_gpio(gc);
 155         int pin = d->hwirq;
 156         u32 mask = BIT(pin);
 157
 158         if (type == IRQ_TYPE_PROBE) {
 159                 if ((rg->rising | rg->falling |
 160                      rg->hlevel | rg->llevel) & mask)
 161                         return 0;
 162
 163                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 164         }
 165
 166         rg->rising &= ~mask;
 167         rg->falling &= ~mask;
 168         rg->hlevel &= ~mask;
 169         rg->llevel &= ~mask;
 170
 171         switch (type & IRQ_TYPE_SENSE_MASK) {
 172         case IRQ_TYPE_EDGE_BOTH:
 173                 rg->rising |= mask;
 174                 rg->falling |= mask;
 175                 break;
 176         case IRQ_TYPE_EDGE_RISING:
 177                 rg->rising |= mask;
 178                 break;
 179         case IRQ_TYPE_EDGE_FALLING:
 180                 rg->falling |= mask;
 181                 break;
 182         case IRQ_TYPE_LEVEL_HIGH:
 183                 rg->hlevel |= mask;
 184                 break;
 185         case IRQ_TYPE_LEVEL_LOW:
 186                 rg->llevel |= mask;
 187                 break;
 188         }
 189
 190         return 0;
 191 }
 192
 193 static int
 194 mediatek_gpio_xlate(struct gpio_chip *chip,
 195                     const struct of_phandle_args *spec, u32 *flags)
 196 {
 197         int gpio = spec->args[0];
 198         struct mtk_gc *rg = to_mediatek_gpio(chip);
 199
 200         if (rg->bank != gpio / MTK_BANK_WIDTH)
 201                 return -EINVAL;
 202
 203         if (flags)
 204                 *flags = spec->args[1];
 205
 206         return gpio % MTK_BANK_WIDTH;
 207 }
 208
 209 static int
 210 mediatek_gpio_bank_probe(struct device *dev,
 211                          struct device_node *node, int bank)
 212 {
 213         struct mtk *mtk = dev_get_drvdata(dev);
 214         struct mtk_gc *rg;
 215         void __iomem *dat, *set, *ctrl, *diro;
 216         int ret;
 217
 218         rg = &mtk->gc_map[bank];
 219         memset(rg, 0, sizeof(*rg));
 220
 221         spin_lock_init(&rg->lock);
 222         rg->chip.of_node = node;
 223         rg->bank = bank;
 224
 225         dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
 226         set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
 227         ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
 228         diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
 229
 230         ret = bgpio_init(&rg->chip, dev, 4,
 231                          dat, set, ctrl, diro, NULL, 0);
 232         if (ret) {
 233                 dev_err(dev, "bgpio_init() failed\n");
 234                 return ret;
 235         }
 236
 237         rg->chip.of_gpio_n_cells = 2;
 238         rg->chip.of_xlate = mediatek_gpio_xlate;
 239         rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
 240                                         dev_name(dev), bank);
 241         if (!rg->chip.label)
 242                 return -ENOMEM;
 243
 244         rg->irq_chip.name = dev_name(dev);
 245         rg->irq_chip.parent_device = dev;
 246         rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
 247         rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
 248         rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
 249         rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;
 250
 251         if (mtk->gpio_irq) {
 252                 struct gpio_irq_chip *girq;
 253
 254                 /*
 255                  * Directly request the irq here instead of passing
 256                  * a flow-handler to gpiochip_set_chained_irqchip,
 257                  * because the irq is shared.
 258                  */
 259                 ret = devm_request_irq(dev, mtk->gpio_irq,
 260                                        mediatek_gpio_irq_handler, IRQF_SHARED,
 261                                        rg->chip.label, &rg->chip);
 262
 263                 if (ret) {
 264                         dev_err(dev, "Error requesting IRQ %d: %d\n",
 265                                 mtk->gpio_irq, ret);
 266                         return ret;
 267                 }
 268
 269                 girq = &rg->chip.irq;
 270                 girq->chip = &rg->irq_chip;
 271                 /* This will let us handle the parent IRQ in the driver */
 272                 girq->parent_handler = NULL;
 273                 girq->num_parents = 0;
 274                 girq->parents = NULL;
 275                 girq->default_type = IRQ_TYPE_NONE;
 276                 girq->handler = handle_simple_irq;
 277         }
 278
 279         ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
 280         if (ret < 0) {
 281                 dev_err(dev, "Could not register gpio %d, ret=%d\n",
 282                         rg->chip.ngpio, ret);
 283                 return ret;
 284         }
 285
 286         /* set polarity to low for all gpios */
 287         mtk_gpio_w32(rg, GPIO_REG_POL, 0);
 288
 289         dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
 290
 291         return 0;
 292 }
 293
 294 static int
 295 mediatek_gpio_probe(struct platform_device *pdev)
 296 {
 297         struct device *dev = &pdev->dev;
 298         struct device_node *np = dev->of_node;
 299         struct mtk *mtk;
 300         int i;
 301         int ret;
 302
 303         mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
 304         if (!mtk)
 305                 return -ENOMEM;
 306
 307         mtk->base = devm_platform_ioremap_resource(pdev, 0);
 308         if (IS_ERR(mtk->base))
 309                 return PTR_ERR(mtk->base);
 310
 311         mtk->gpio_irq = irq_of_parse_and_map(np, 0);
 312         mtk->dev = dev;
 313         platform_set_drvdata(pdev, mtk);
 314
 315         for (i = 0; i < MTK_BANK_CNT; i++) {
 316                 ret = mediatek_gpio_bank_probe(dev, np, i);
 317                 if (ret)
 318                         return ret;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static const struct of_device_id mediatek_gpio_match[] = {
 325         { .compatible = "mediatek,mt7621-gpio" },
 326         {},
 327 };
 328 MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
 329
 330 static struct platform_driver mediatek_gpio_driver = {
 331         .probe = mediatek_gpio_probe,
 332         .driver = {
 333                 .name = "mt7621_gpio",
 334                 .of_match_table = mediatek_gpio_match,
 335         },
 336 };
 337
 338 builtin_platform_driver(mediatek_gpio_driver);