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tty: Add support for PCIe WCH382 2S multi-IO card
[linux/fpc-iii.git] / drivers / tty / serial / mxs-auart.c
blobcd0414bbe094898ed3fdeca0a941549312472581
1 /*
2 * Freescale STMP37XX/STMP378X Application UART driver
3 *
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
5 *
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17 #if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #define SUPPORT_SYSRQ
19 #endif
20
21 #include <linux/kernel.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/console.h>
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <linux/wait.h>
29 #include <linux/tty.h>
30 #include <linux/tty_driver.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/serial_core.h>
34 #include <linux/platform_device.h>
35 #include <linux/device.h>
36 #include <linux/clk.h>
37 #include <linux/delay.h>
38 #include <linux/io.h>
39 #include <linux/of_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/dmaengine.h>
42
43 #include <asm/cacheflush.h>
44
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include "serial_mctrl_gpio.h"
50
51 #define MXS_AUART_PORTS 5
52 #define MXS_AUART_FIFO_SIZE 16
53
54 #define AUART_CTRL0 0x00000000
55 #define AUART_CTRL0_SET 0x00000004
56 #define AUART_CTRL0_CLR 0x00000008
57 #define AUART_CTRL0_TOG 0x0000000c
58 #define AUART_CTRL1 0x00000010
59 #define AUART_CTRL1_SET 0x00000014
60 #define AUART_CTRL1_CLR 0x00000018
61 #define AUART_CTRL1_TOG 0x0000001c
62 #define AUART_CTRL2 0x00000020
63 #define AUART_CTRL2_SET 0x00000024
64 #define AUART_CTRL2_CLR 0x00000028
65 #define AUART_CTRL2_TOG 0x0000002c
66 #define AUART_LINECTRL 0x00000030
67 #define AUART_LINECTRL_SET 0x00000034
68 #define AUART_LINECTRL_CLR 0x00000038
69 #define AUART_LINECTRL_TOG 0x0000003c
70 #define AUART_LINECTRL2 0x00000040
71 #define AUART_LINECTRL2_SET 0x00000044
72 #define AUART_LINECTRL2_CLR 0x00000048
73 #define AUART_LINECTRL2_TOG 0x0000004c
74 #define AUART_INTR 0x00000050
75 #define AUART_INTR_SET 0x00000054
76 #define AUART_INTR_CLR 0x00000058
77 #define AUART_INTR_TOG 0x0000005c
78 #define AUART_DATA 0x00000060
79 #define AUART_STAT 0x00000070
80 #define AUART_DEBUG 0x00000080
81 #define AUART_VERSION 0x00000090
82 #define AUART_AUTOBAUD 0x000000a0
83
84 #define AUART_CTRL0_SFTRST (1 << 31)
85 #define AUART_CTRL0_CLKGATE (1 << 30)
86 #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
87 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
88 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
89
90 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
91
92 #define AUART_CTRL2_DMAONERR (1 << 26)
93 #define AUART_CTRL2_TXDMAE (1 << 25)
94 #define AUART_CTRL2_RXDMAE (1 << 24)
95
96 #define AUART_CTRL2_CTSEN (1 << 15)
97 #define AUART_CTRL2_RTSEN (1 << 14)
98 #define AUART_CTRL2_RTS (1 << 11)
99 #define AUART_CTRL2_RXE (1 << 9)
100 #define AUART_CTRL2_TXE (1 << 8)
101 #define AUART_CTRL2_UARTEN (1 << 0)
102
103 #define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
104 #define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
105 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
106 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
107 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
108 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
109 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
110 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
111 #define AUART_LINECTRL_WLEN_MASK 0x00000060
112 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
113 #define AUART_LINECTRL_FEN (1 << 4)
114 #define AUART_LINECTRL_STP2 (1 << 3)
115 #define AUART_LINECTRL_EPS (1 << 2)
116 #define AUART_LINECTRL_PEN (1 << 1)
117 #define AUART_LINECTRL_BRK (1 << 0)
118
119 #define AUART_INTR_RTIEN (1 << 22)
120 #define AUART_INTR_TXIEN (1 << 21)
121 #define AUART_INTR_RXIEN (1 << 20)
122 #define AUART_INTR_CTSMIEN (1 << 17)
123 #define AUART_INTR_RTIS (1 << 6)
124 #define AUART_INTR_TXIS (1 << 5)
125 #define AUART_INTR_RXIS (1 << 4)
126 #define AUART_INTR_CTSMIS (1 << 1)
127
128 #define AUART_STAT_BUSY (1 << 29)
129 #define AUART_STAT_CTS (1 << 28)
130 #define AUART_STAT_TXFE (1 << 27)
131 #define AUART_STAT_TXFF (1 << 25)
132 #define AUART_STAT_RXFE (1 << 24)
133 #define AUART_STAT_OERR (1 << 19)
134 #define AUART_STAT_BERR (1 << 18)
135 #define AUART_STAT_PERR (1 << 17)
136 #define AUART_STAT_FERR (1 << 16)
137 #define AUART_STAT_RXCOUNT_MASK 0xffff
138
139 static struct uart_driver auart_driver;
140
141 enum mxs_auart_type {
142 IMX23_AUART,
143 IMX28_AUART,
144 };
145
146 struct mxs_auart_port {
147 struct uart_port port;
148
149 #define MXS_AUART_DMA_ENABLED 0x2
150 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
151 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
152 #define MXS_AUART_RTSCTS 4 /* bit 4 */
153 unsigned long flags;
154 unsigned int mctrl_prev;
155 enum mxs_auart_type devtype;
156
157 struct clk *clk;
158 struct device *dev;
159
160 /* for DMA */
161 struct scatterlist tx_sgl;
162 struct dma_chan *tx_dma_chan;
163 void *tx_dma_buf;
164
165 struct scatterlist rx_sgl;
166 struct dma_chan *rx_dma_chan;
167 void *rx_dma_buf;
168
169 struct mctrl_gpios *gpios;
170 int gpio_irq[UART_GPIO_MAX];
171 bool ms_irq_enabled;
172 };
173
174 static const struct platform_device_id mxs_auart_devtype[] = {
175 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
176 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
177 { /* sentinel */ }
178 };
179 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
180
181 static const struct of_device_id mxs_auart_dt_ids[] = {
182 {
183 .compatible = "fsl,imx28-auart",
184 .data = &mxs_auart_devtype[IMX28_AUART]
185 }, {
186 .compatible = "fsl,imx23-auart",
187 .data = &mxs_auart_devtype[IMX23_AUART]
188 }, { /* sentinel */ }
189 };
190 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
191
192 static inline int is_imx28_auart(struct mxs_auart_port *s)
193 {
194 return s->devtype == IMX28_AUART;
195 }
196
197 static inline bool auart_dma_enabled(struct mxs_auart_port *s)
198 {
199 return s->flags & MXS_AUART_DMA_ENABLED;
200 }
201
202 static void mxs_auart_stop_tx(struct uart_port *u);
203
204 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
205
206 static void mxs_auart_tx_chars(struct mxs_auart_port *s);
207
208 static void dma_tx_callback(void *param)
209 {
210 struct mxs_auart_port *s = param;
211 struct circ_buf *xmit = &s->port.state->xmit;
212
213 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
214
215 /* clear the bit used to serialize the DMA tx. */
216 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
217 smp_mb__after_atomic();
218
219 /* wake up the possible processes. */
220 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
221 uart_write_wakeup(&s->port);
222
223 mxs_auart_tx_chars(s);
224 }
225
226 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
227 {
228 struct dma_async_tx_descriptor *desc;
229 struct scatterlist *sgl = &s->tx_sgl;
230 struct dma_chan *channel = s->tx_dma_chan;
231 u32 pio;
232
233 /* [1] : send PIO. Note, the first pio word is CTRL1. */
234 pio = AUART_CTRL1_XFER_COUNT(size);
235 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
236 1, DMA_TRANS_NONE, 0);
237 if (!desc) {
238 dev_err(s->dev, "step 1 error\n");
239 return -EINVAL;
240 }
241
242 /* [2] : set DMA buffer. */
243 sg_init_one(sgl, s->tx_dma_buf, size);
244 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
245 desc = dmaengine_prep_slave_sg(channel, sgl,
246 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
247 if (!desc) {
248 dev_err(s->dev, "step 2 error\n");
249 return -EINVAL;
250 }
251
252 /* [3] : submit the DMA */
253 desc->callback = dma_tx_callback;
254 desc->callback_param = s;
255 dmaengine_submit(desc);
256 dma_async_issue_pending(channel);
257 return 0;
258 }
259
260 static void mxs_auart_tx_chars(struct mxs_auart_port *s)
261 {
262 struct circ_buf *xmit = &s->port.state->xmit;
263
264 if (auart_dma_enabled(s)) {
265 u32 i = 0;
266 int size;
267 void *buffer = s->tx_dma_buf;
268
269 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
270 return;
271
272 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
273 size = min_t(u32, UART_XMIT_SIZE - i,
274 CIRC_CNT_TO_END(xmit->head,
275 xmit->tail,
276 UART_XMIT_SIZE));
277 memcpy(buffer + i, xmit->buf + xmit->tail, size);
278 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
279
280 i += size;
281 if (i >= UART_XMIT_SIZE)
282 break;
283 }
284
285 if (uart_tx_stopped(&s->port))
286 mxs_auart_stop_tx(&s->port);
287
288 if (i) {
289 mxs_auart_dma_tx(s, i);
290 } else {
291 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
292 smp_mb__after_atomic();
293 }
294 return;
295 }
296
297
298 while (!(readl(s->port.membase + AUART_STAT) &
299 AUART_STAT_TXFF)) {
300 if (s->port.x_char) {
301 s->port.icount.tx++;
302 writel(s->port.x_char,
303 s->port.membase + AUART_DATA);
304 s->port.x_char = 0;
305 continue;
306 }
307 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
308 s->port.icount.tx++;
309 writel(xmit->buf[xmit->tail],
310 s->port.membase + AUART_DATA);
311 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
312 } else
313 break;
314 }
315 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
316 uart_write_wakeup(&s->port);
317
318 if (uart_circ_empty(&(s->port.state->xmit)))
319 writel(AUART_INTR_TXIEN,
320 s->port.membase + AUART_INTR_CLR);
321 else
322 writel(AUART_INTR_TXIEN,
323 s->port.membase + AUART_INTR_SET);
324
325 if (uart_tx_stopped(&s->port))
326 mxs_auart_stop_tx(&s->port);
327 }
328
329 static void mxs_auart_rx_char(struct mxs_auart_port *s)
330 {
331 int flag;
332 u32 stat;
333 u8 c;
334
335 c = readl(s->port.membase + AUART_DATA);
336 stat = readl(s->port.membase + AUART_STAT);
337
338 flag = TTY_NORMAL;
339 s->port.icount.rx++;
340
341 if (stat & AUART_STAT_BERR) {
342 s->port.icount.brk++;
343 if (uart_handle_break(&s->port))
344 goto out;
345 } else if (stat & AUART_STAT_PERR) {
346 s->port.icount.parity++;
347 } else if (stat & AUART_STAT_FERR) {
348 s->port.icount.frame++;
349 }
350
351 /*
352 * Mask off conditions which should be ingored.
353 */
354 stat &= s->port.read_status_mask;
355
356 if (stat & AUART_STAT_BERR) {
357 flag = TTY_BREAK;
358 } else if (stat & AUART_STAT_PERR)
359 flag = TTY_PARITY;
360 else if (stat & AUART_STAT_FERR)
361 flag = TTY_FRAME;
362
363 if (stat & AUART_STAT_OERR)
364 s->port.icount.overrun++;
365
366 if (uart_handle_sysrq_char(&s->port, c))
367 goto out;
368
369 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
370 out:
371 writel(stat, s->port.membase + AUART_STAT);
372 }
373
374 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
375 {
376 u32 stat = 0;
377
378 for (;;) {
379 stat = readl(s->port.membase + AUART_STAT);
380 if (stat & AUART_STAT_RXFE)
381 break;
382 mxs_auart_rx_char(s);
383 }
384
385 writel(stat, s->port.membase + AUART_STAT);
386 tty_flip_buffer_push(&s->port.state->port);
387 }
388
389 static int mxs_auart_request_port(struct uart_port *u)
390 {
391 return 0;
392 }
393
394 static int mxs_auart_verify_port(struct uart_port *u,
395 struct serial_struct *ser)
396 {
397 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
398 return -EINVAL;
399 return 0;
400 }
401
402 static void mxs_auart_config_port(struct uart_port *u, int flags)
403 {
404 }
405
406 static const char *mxs_auart_type(struct uart_port *u)
407 {
408 struct mxs_auart_port *s = to_auart_port(u);
409
410 return dev_name(s->dev);
411 }
412
413 static void mxs_auart_release_port(struct uart_port *u)
414 {
415 }
416
417 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
418 {
419 struct mxs_auart_port *s = to_auart_port(u);
420
421 u32 ctrl = readl(u->membase + AUART_CTRL2);
422
423 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
424 if (mctrl & TIOCM_RTS) {
425 if (uart_cts_enabled(u))
426 ctrl |= AUART_CTRL2_RTSEN;
427 else
428 ctrl |= AUART_CTRL2_RTS;
429 }
430
431 writel(ctrl, u->membase + AUART_CTRL2);
432
433 mctrl_gpio_set(s->gpios, mctrl);
434 }
435
436 #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
437 static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
438 {
439 u32 mctrl_diff;
440
441 mctrl_diff = mctrl ^ s->mctrl_prev;
442 s->mctrl_prev = mctrl;
443 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
444 s->port.state != NULL) {
445 if (mctrl_diff & TIOCM_RI)
446 s->port.icount.rng++;
447 if (mctrl_diff & TIOCM_DSR)
448 s->port.icount.dsr++;
449 if (mctrl_diff & TIOCM_CD)
450 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
451 if (mctrl_diff & TIOCM_CTS)
452 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
453
454 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
455 }
456 return mctrl;
457 }
458
459 static u32 mxs_auart_get_mctrl(struct uart_port *u)
460 {
461 struct mxs_auart_port *s = to_auart_port(u);
462 u32 stat = readl(u->membase + AUART_STAT);
463 u32 mctrl = 0;
464
465 if (stat & AUART_STAT_CTS)
466 mctrl |= TIOCM_CTS;
467
468 return mctrl_gpio_get(s->gpios, &mctrl);
469 }
470
471 /*
472 * Enable modem status interrupts
473 */
474 static void mxs_auart_enable_ms(struct uart_port *port)
475 {
476 struct mxs_auart_port *s = to_auart_port(port);
477
478 /*
479 * Interrupt should not be enabled twice
480 */
481 if (s->ms_irq_enabled)
482 return;
483
484 s->ms_irq_enabled = true;
485
486 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
487 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
488 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
489
490 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
491 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
492
493 if (s->gpio_irq[UART_GPIO_RI] >= 0)
494 enable_irq(s->gpio_irq[UART_GPIO_RI]);
495
496 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
497 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
498 }
499
500 /*
501 * Disable modem status interrupts
502 */
503 static void mxs_auart_disable_ms(struct uart_port *port)
504 {
505 struct mxs_auart_port *s = to_auart_port(port);
506
507 /*
508 * Interrupt should not be disabled twice
509 */
510 if (!s->ms_irq_enabled)
511 return;
512
513 s->ms_irq_enabled = false;
514
515 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
516 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
517 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
518
519 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
520 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
521
522 if (s->gpio_irq[UART_GPIO_RI] >= 0)
523 disable_irq(s->gpio_irq[UART_GPIO_RI]);
524
525 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
526 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
527 }
528
529 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
530 static void dma_rx_callback(void *arg)
531 {
532 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
533 struct tty_port *port = &s->port.state->port;
534 int count;
535 u32 stat;
536
537 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
538
539 stat = readl(s->port.membase + AUART_STAT);
540 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
541 AUART_STAT_PERR | AUART_STAT_FERR);
542
543 count = stat & AUART_STAT_RXCOUNT_MASK;
544 tty_insert_flip_string(port, s->rx_dma_buf, count);
545
546 writel(stat, s->port.membase + AUART_STAT);
547 tty_flip_buffer_push(port);
548
549 /* start the next DMA for RX. */
550 mxs_auart_dma_prep_rx(s);
551 }
552
553 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
554 {
555 struct dma_async_tx_descriptor *desc;
556 struct scatterlist *sgl = &s->rx_sgl;
557 struct dma_chan *channel = s->rx_dma_chan;
558 u32 pio[1];
559
560 /* [1] : send PIO */
561 pio[0] = AUART_CTRL0_RXTO_ENABLE
562 | AUART_CTRL0_RXTIMEOUT(0x80)
563 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
564 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
565 1, DMA_TRANS_NONE, 0);
566 if (!desc) {
567 dev_err(s->dev, "step 1 error\n");
568 return -EINVAL;
569 }
570
571 /* [2] : send DMA request */
572 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
573 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
574 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
575 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
576 if (!desc) {
577 dev_err(s->dev, "step 2 error\n");
578 return -1;
579 }
580
581 /* [3] : submit the DMA, but do not issue it. */
582 desc->callback = dma_rx_callback;
583 desc->callback_param = s;
584 dmaengine_submit(desc);
585 dma_async_issue_pending(channel);
586 return 0;
587 }
588
589 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
590 {
591 if (s->tx_dma_chan) {
592 dma_release_channel(s->tx_dma_chan);
593 s->tx_dma_chan = NULL;
594 }
595 if (s->rx_dma_chan) {
596 dma_release_channel(s->rx_dma_chan);
597 s->rx_dma_chan = NULL;
598 }
599
600 kfree(s->tx_dma_buf);
601 kfree(s->rx_dma_buf);
602 s->tx_dma_buf = NULL;
603 s->rx_dma_buf = NULL;
604 }
605
606 static void mxs_auart_dma_exit(struct mxs_auart_port *s)
607 {
608
609 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
610 s->port.membase + AUART_CTRL2_CLR);
611
612 mxs_auart_dma_exit_channel(s);
613 s->flags &= ~MXS_AUART_DMA_ENABLED;
614 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
615 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
616 }
617
618 static int mxs_auart_dma_init(struct mxs_auart_port *s)
619 {
620 if (auart_dma_enabled(s))
621 return 0;
622
623 /* init for RX */
624 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
625 if (!s->rx_dma_chan)
626 goto err_out;
627 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
628 if (!s->rx_dma_buf)
629 goto err_out;
630
631 /* init for TX */
632 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
633 if (!s->tx_dma_chan)
634 goto err_out;
635 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
636 if (!s->tx_dma_buf)
637 goto err_out;
638
639 /* set the flags */
640 s->flags |= MXS_AUART_DMA_ENABLED;
641 dev_dbg(s->dev, "enabled the DMA support.");
642
643 /* The DMA buffer is now the FIFO the TTY subsystem can use */
644 s->port.fifosize = UART_XMIT_SIZE;
645
646 return 0;
647
648 err_out:
649 mxs_auart_dma_exit_channel(s);
650 return -EINVAL;
651
652 }
653
654 #define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
655 UART_GPIO_RTS))
656 #define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
657 UART_GPIO_CTS))
658 static void mxs_auart_settermios(struct uart_port *u,
659 struct ktermios *termios,
660 struct ktermios *old)
661 {
662 struct mxs_auart_port *s = to_auart_port(u);
663 u32 bm, ctrl, ctrl2, div;
664 unsigned int cflag, baud, baud_min, baud_max;
665
666 cflag = termios->c_cflag;
667
668 ctrl = AUART_LINECTRL_FEN;
669 ctrl2 = readl(u->membase + AUART_CTRL2);
670
671 /* byte size */
672 switch (cflag & CSIZE) {
673 case CS5:
674 bm = 0;
675 break;
676 case CS6:
677 bm = 1;
678 break;
679 case CS7:
680 bm = 2;
681 break;
682 case CS8:
683 bm = 3;
684 break;
685 default:
686 return;
687 }
688
689 ctrl |= AUART_LINECTRL_WLEN(bm);
690
691 /* parity */
692 if (cflag & PARENB) {
693 ctrl |= AUART_LINECTRL_PEN;
694 if ((cflag & PARODD) == 0)
695 ctrl |= AUART_LINECTRL_EPS;
696 }
697
698 u->read_status_mask = 0;
699
700 if (termios->c_iflag & INPCK)
701 u->read_status_mask |= AUART_STAT_PERR;
702 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
703 u->read_status_mask |= AUART_STAT_BERR;
704
705 /*
706 * Characters to ignore
707 */
708 u->ignore_status_mask = 0;
709 if (termios->c_iflag & IGNPAR)
710 u->ignore_status_mask |= AUART_STAT_PERR;
711 if (termios->c_iflag & IGNBRK) {
712 u->ignore_status_mask |= AUART_STAT_BERR;
713 /*
714 * If we're ignoring parity and break indicators,
715 * ignore overruns too (for real raw support).
716 */
717 if (termios->c_iflag & IGNPAR)
718 u->ignore_status_mask |= AUART_STAT_OERR;
719 }
720
721 /*
722 * ignore all characters if CREAD is not set
723 */
724 if (cflag & CREAD)
725 ctrl2 |= AUART_CTRL2_RXE;
726 else
727 ctrl2 &= ~AUART_CTRL2_RXE;
728
729 /* figure out the stop bits requested */
730 if (cflag & CSTOPB)
731 ctrl |= AUART_LINECTRL_STP2;
732
733 /* figure out the hardware flow control settings */
734 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
735 if (cflag & CRTSCTS) {
736 /*
737 * The DMA has a bug(see errata:2836) in mx23.
738 * So we can not implement the DMA for auart in mx23,
739 * we can only implement the DMA support for auart
740 * in mx28.
741 */
742 if (is_imx28_auart(s)
743 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
744 if (!mxs_auart_dma_init(s))
745 /* enable DMA tranfer */
746 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
747 | AUART_CTRL2_DMAONERR;
748 }
749 /* Even if RTS is GPIO line RTSEN can be enabled because
750 * the pinctrl configuration decides about RTS pin function */
751 ctrl2 |= AUART_CTRL2_RTSEN;
752 if (CTS_AT_AUART())
753 ctrl2 |= AUART_CTRL2_CTSEN;
754 }
755
756 /* set baud rate */
757 baud_min = DIV_ROUND_UP(u->uartclk * 32, AUART_LINECTRL_BAUD_DIV_MAX);
758 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
759 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
760 div = u->uartclk * 32 / baud;
761 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
762 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
763
764 writel(ctrl, u->membase + AUART_LINECTRL);
765 writel(ctrl2, u->membase + AUART_CTRL2);
766
767 uart_update_timeout(u, termios->c_cflag, baud);
768
769 /* prepare for the DMA RX. */
770 if (auart_dma_enabled(s) &&
771 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
772 if (!mxs_auart_dma_prep_rx(s)) {
773 /* Disable the normal RX interrupt. */
774 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
775 u->membase + AUART_INTR_CLR);
776 } else {
777 mxs_auart_dma_exit(s);
778 dev_err(s->dev, "We can not start up the DMA.\n");
779 }
780 }
781
782 /* CTS flow-control and modem-status interrupts */
783 if (UART_ENABLE_MS(u, termios->c_cflag))
784 mxs_auart_enable_ms(u);
785 else
786 mxs_auart_disable_ms(u);
787 }
788
789 static void mxs_auart_set_ldisc(struct uart_port *port,
790 struct ktermios *termios)
791 {
792 if (termios->c_line == N_PPS) {
793 port->flags |= UPF_HARDPPS_CD;
794 mxs_auart_enable_ms(port);
795 } else {
796 port->flags &= ~UPF_HARDPPS_CD;
797 }
798 }
799
800 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
801 {
802 u32 istat;
803 struct mxs_auart_port *s = context;
804 u32 mctrl_temp = s->mctrl_prev;
805 u32 stat = readl(s->port.membase + AUART_STAT);
806
807 istat = readl(s->port.membase + AUART_INTR);
808
809 /* ack irq */
810 writel(istat & (AUART_INTR_RTIS
811 | AUART_INTR_TXIS
812 | AUART_INTR_RXIS
813 | AUART_INTR_CTSMIS),
814 s->port.membase + AUART_INTR_CLR);
815
816 /*
817 * Dealing with GPIO interrupt
818 */
819 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
820 irq == s->gpio_irq[UART_GPIO_DCD] ||
821 irq == s->gpio_irq[UART_GPIO_DSR] ||
822 irq == s->gpio_irq[UART_GPIO_RI])
823 mxs_auart_modem_status(s,
824 mctrl_gpio_get(s->gpios, &mctrl_temp));
825
826 if (istat & AUART_INTR_CTSMIS) {
827 if (CTS_AT_AUART() && s->ms_irq_enabled)
828 uart_handle_cts_change(&s->port,
829 stat & AUART_STAT_CTS);
830 writel(AUART_INTR_CTSMIS,
831 s->port.membase + AUART_INTR_CLR);
832 istat &= ~AUART_INTR_CTSMIS;
833 }
834
835 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
836 if (!auart_dma_enabled(s))
837 mxs_auart_rx_chars(s);
838 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
839 }
840
841 if (istat & AUART_INTR_TXIS) {
842 mxs_auart_tx_chars(s);
843 istat &= ~AUART_INTR_TXIS;
844 }
845
846 return IRQ_HANDLED;
847 }
848
849 static void mxs_auart_reset_deassert(struct uart_port *u)
850 {
851 int i;
852 unsigned int reg;
853
854 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
855
856 for (i = 0; i < 10000; i++) {
857 reg = readl(u->membase + AUART_CTRL0);
858 if (!(reg & AUART_CTRL0_SFTRST))
859 break;
860 udelay(3);
861 }
862 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
863 }
864
865 static void mxs_auart_reset_assert(struct uart_port *u)
866 {
867 int i;
868 u32 reg;
869
870 reg = readl(u->membase + AUART_CTRL0);
871 /* if already in reset state, keep it untouched */
872 if (reg & AUART_CTRL0_SFTRST)
873 return;
874
875 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
876 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_SET);
877
878 for (i = 0; i < 1000; i++) {
879 reg = readl(u->membase + AUART_CTRL0);
880 /* reset is finished when the clock is gated */
881 if (reg & AUART_CTRL0_CLKGATE)
882 return;
883 udelay(10);
884 }
885
886 dev_err(u->dev, "Failed to reset the unit.");
887 }
888
889 static int mxs_auart_startup(struct uart_port *u)
890 {
891 int ret;
892 struct mxs_auart_port *s = to_auart_port(u);
893
894 ret = clk_prepare_enable(s->clk);
895 if (ret)
896 return ret;
897
898 if (uart_console(u)) {
899 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
900 } else {
901 /* reset the unit to a well known state */
902 mxs_auart_reset_assert(u);
903 mxs_auart_reset_deassert(u);
904 }
905
906 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
907
908 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
909 u->membase + AUART_INTR);
910
911 /* Reset FIFO size (it could have changed if DMA was enabled) */
912 u->fifosize = MXS_AUART_FIFO_SIZE;
913
914 /*
915 * Enable fifo so all four bytes of a DMA word are written to
916 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
917 */
918 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
919
920 /* get initial status of modem lines */
921 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
922
923 s->ms_irq_enabled = false;
924 return 0;
925 }
926
927 static void mxs_auart_shutdown(struct uart_port *u)
928 {
929 struct mxs_auart_port *s = to_auart_port(u);
930
931 mxs_auart_disable_ms(u);
932
933 if (auart_dma_enabled(s))
934 mxs_auart_dma_exit(s);
935
936 if (uart_console(u)) {
937 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
938 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
939 u->membase + AUART_INTR_CLR);
940 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
941 } else {
942 mxs_auart_reset_assert(u);
943 }
944
945 clk_disable_unprepare(s->clk);
946 }
947
948 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
949 {
950 if ((readl(u->membase + AUART_STAT) &
951 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
952 return TIOCSER_TEMT;
953
954 return 0;
955 }
956
957 static void mxs_auart_start_tx(struct uart_port *u)
958 {
959 struct mxs_auart_port *s = to_auart_port(u);
960
961 /* enable transmitter */
962 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
963
964 mxs_auart_tx_chars(s);
965 }
966
967 static void mxs_auart_stop_tx(struct uart_port *u)
968 {
969 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
970 }
971
972 static void mxs_auart_stop_rx(struct uart_port *u)
973 {
974 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
975 }
976
977 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
978 {
979 if (ctl)
980 writel(AUART_LINECTRL_BRK,
981 u->membase + AUART_LINECTRL_SET);
982 else
983 writel(AUART_LINECTRL_BRK,
984 u->membase + AUART_LINECTRL_CLR);
985 }
986
987 static struct uart_ops mxs_auart_ops = {
988 .tx_empty = mxs_auart_tx_empty,
989 .start_tx = mxs_auart_start_tx,
990 .stop_tx = mxs_auart_stop_tx,
991 .stop_rx = mxs_auart_stop_rx,
992 .enable_ms = mxs_auart_enable_ms,
993 .break_ctl = mxs_auart_break_ctl,
994 .set_mctrl = mxs_auart_set_mctrl,
995 .get_mctrl = mxs_auart_get_mctrl,
996 .startup = mxs_auart_startup,
997 .shutdown = mxs_auart_shutdown,
998 .set_termios = mxs_auart_settermios,
999 .set_ldisc = mxs_auart_set_ldisc,
1000 .type = mxs_auart_type,
1001 .release_port = mxs_auart_release_port,
1002 .request_port = mxs_auart_request_port,
1003 .config_port = mxs_auart_config_port,
1004 .verify_port = mxs_auart_verify_port,
1005 };
1006
1007 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1008
1009 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1010 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
1011 {
1012 unsigned int to = 1000;
1013
1014 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
1015 if (!to--)
1016 break;
1017 udelay(1);
1018 }
1019
1020 writel(ch, port->membase + AUART_DATA);
1021 }
1022
1023 static void
1024 auart_console_write(struct console *co, const char *str, unsigned int count)
1025 {
1026 struct mxs_auart_port *s;
1027 struct uart_port *port;
1028 unsigned int old_ctrl0, old_ctrl2;
1029 unsigned int to = 20000;
1030
1031 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1032 return;
1033
1034 s = auart_port[co->index];
1035 port = &s->port;
1036
1037 clk_enable(s->clk);
1038
1039 /* First save the CR then disable the interrupts */
1040 old_ctrl2 = readl(port->membase + AUART_CTRL2);
1041 old_ctrl0 = readl(port->membase + AUART_CTRL0);
1042
1043 writel(AUART_CTRL0_CLKGATE,
1044 port->membase + AUART_CTRL0_CLR);
1045 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
1046 port->membase + AUART_CTRL2_SET);
1047
1048 uart_console_write(port, str, count, mxs_auart_console_putchar);
1049
1050 /* Finally, wait for transmitter to become empty ... */
1051 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
1052 udelay(1);
1053 if (!to--)
1054 break;
1055 }
1056
1057 /*
1058 * ... and restore the TCR if we waited long enough for the transmitter
1059 * to be idle. This might keep the transmitter enabled although it is
1060 * unused, but that is better than to disable it while it is still
1061 * transmitting.
1062 */
1063 if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) {
1064 writel(old_ctrl0, port->membase + AUART_CTRL0);
1065 writel(old_ctrl2, port->membase + AUART_CTRL2);
1066 }
1067
1068 clk_disable(s->clk);
1069 }
1070
1071 static void __init
1072 auart_console_get_options(struct uart_port *port, int *baud,
1073 int *parity, int *bits)
1074 {
1075 unsigned int lcr_h, quot;
1076
1077 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
1078 return;
1079
1080 lcr_h = readl(port->membase + AUART_LINECTRL);
1081
1082 *parity = 'n';
1083 if (lcr_h & AUART_LINECTRL_PEN) {
1084 if (lcr_h & AUART_LINECTRL_EPS)
1085 *parity = 'e';
1086 else
1087 *parity = 'o';
1088 }
1089
1090 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1091 *bits = 7;
1092 else
1093 *bits = 8;
1094
1095 quot = ((readl(port->membase + AUART_LINECTRL)
1096 & AUART_LINECTRL_BAUD_DIVINT_MASK))
1097 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1098 quot |= ((readl(port->membase + AUART_LINECTRL)
1099 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1100 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1101 if (quot == 0)
1102 quot = 1;
1103
1104 *baud = (port->uartclk << 2) / quot;
1105 }
1106
1107 static int __init
1108 auart_console_setup(struct console *co, char *options)
1109 {
1110 struct mxs_auart_port *s;
1111 int baud = 9600;
1112 int bits = 8;
1113 int parity = 'n';
1114 int flow = 'n';
1115 int ret;
1116
1117 /*
1118 * Check whether an invalid uart number has been specified, and
1119 * if so, search for the first available port that does have
1120 * console support.
1121 */
1122 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1123 co->index = 0;
1124 s = auart_port[co->index];
1125 if (!s)
1126 return -ENODEV;
1127
1128 ret = clk_prepare_enable(s->clk);
1129 if (ret)
1130 return ret;
1131
1132 if (options)
1133 uart_parse_options(options, &baud, &parity, &bits, &flow);
1134 else
1135 auart_console_get_options(&s->port, &baud, &parity, &bits);
1136
1137 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1138
1139 clk_disable_unprepare(s->clk);
1140
1141 return ret;
1142 }
1143
1144 static struct console auart_console = {
1145 .name = "ttyAPP",
1146 .write = auart_console_write,
1147 .device = uart_console_device,
1148 .setup = auart_console_setup,
1149 .flags = CON_PRINTBUFFER,
1150 .index = -1,
1151 .data = &auart_driver,
1152 };
1153 #endif
1154
1155 static struct uart_driver auart_driver = {
1156 .owner = THIS_MODULE,
1157 .driver_name = "ttyAPP",
1158 .dev_name = "ttyAPP",
1159 .major = 0,
1160 .minor = 0,
1161 .nr = MXS_AUART_PORTS,
1162 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1163 .cons = &auart_console,
1164 #endif
1165 };
1166
1167 /*
1168 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1169 * could successfully get all information from dt or a negative errno.
1170 */
1171 static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1172 struct platform_device *pdev)
1173 {
1174 struct device_node *np = pdev->dev.of_node;
1175 int ret;
1176
1177 if (!np)
1178 /* no device tree device */
1179 return 1;
1180
1181 ret = of_alias_get_id(np, "serial");
1182 if (ret < 0) {
1183 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1184 return ret;
1185 }
1186 s->port.line = ret;
1187
1188 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1189 set_bit(MXS_AUART_RTSCTS, &s->flags);
1190
1191 return 0;
1192 }
1193
1194 static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1195 {
1196 enum mctrl_gpio_idx i;
1197 struct gpio_desc *gpiod;
1198
1199 s->gpios = mctrl_gpio_init_noauto(dev, 0);
1200 if (IS_ERR(s->gpios))
1201 return PTR_ERR(s->gpios);
1202
1203 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1204 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1205 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1206 dev_warn(dev,
1207 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1208 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1209 }
1210
1211 for (i = 0; i < UART_GPIO_MAX; i++) {
1212 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1213 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
1214 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1215 else
1216 s->gpio_irq[i] = -EINVAL;
1217 }
1218
1219 return 0;
1220 }
1221
1222 static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1223 {
1224 enum mctrl_gpio_idx i;
1225
1226 for (i = 0; i < UART_GPIO_MAX; i++)
1227 if (s->gpio_irq[i] >= 0)
1228 free_irq(s->gpio_irq[i], s);
1229 }
1230
1231 static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1232 {
1233 int *irq = s->gpio_irq;
1234 enum mctrl_gpio_idx i;
1235 int err = 0;
1236
1237 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1238 if (irq[i] < 0)
1239 continue;
1240
1241 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1242 err = request_irq(irq[i], mxs_auart_irq_handle,
1243 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1244 if (err)
1245 dev_err(s->dev, "%s - Can't get %d irq\n",
1246 __func__, irq[i]);
1247 }
1248
1249 /*
1250 * If something went wrong, rollback.
1251 */
1252 while (err && (--i >= 0))
1253 if (irq[i] >= 0)
1254 free_irq(irq[i], s);
1255
1256 return err;
1257 }
1258
1259 static int mxs_auart_probe(struct platform_device *pdev)
1260 {
1261 const struct of_device_id *of_id =
1262 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1263 struct mxs_auart_port *s;
1264 u32 version;
1265 int ret, irq;
1266 struct resource *r;
1267
1268 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1269 if (!s)
1270 return -ENOMEM;
1271
1272 ret = serial_mxs_probe_dt(s, pdev);
1273 if (ret > 0)
1274 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1275 else if (ret < 0)
1276 return ret;
1277
1278 if (of_id) {
1279 pdev->id_entry = of_id->data;
1280 s->devtype = pdev->id_entry->driver_data;
1281 }
1282
1283 s->clk = devm_clk_get(&pdev->dev, NULL);
1284 if (IS_ERR(s->clk))
1285 return PTR_ERR(s->clk);
1286
1287 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1288 if (!r)
1289 return -ENXIO;
1290
1291
1292 s->port.mapbase = r->start;
1293 s->port.membase = ioremap(r->start, resource_size(r));
1294 s->port.ops = &mxs_auart_ops;
1295 s->port.iotype = UPIO_MEM;
1296 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1297 s->port.uartclk = clk_get_rate(s->clk);
1298 s->port.type = PORT_IMX;
1299 s->port.dev = s->dev = &pdev->dev;
1300
1301 s->mctrl_prev = 0;
1302
1303 irq = platform_get_irq(pdev, 0);
1304 if (irq < 0)
1305 return irq;
1306
1307 s->port.irq = irq;
1308 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1309 dev_name(&pdev->dev), s);
1310 if (ret)
1311 return ret;
1312
1313 platform_set_drvdata(pdev, s);
1314
1315 ret = mxs_auart_init_gpios(s, &pdev->dev);
1316 if (ret) {
1317 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1318 return ret;
1319 }
1320
1321 /*
1322 * Get the GPIO lines IRQ
1323 */
1324 ret = mxs_auart_request_gpio_irq(s);
1325 if (ret)
1326 return ret;
1327
1328 auart_port[s->port.line] = s;
1329
1330 mxs_auart_reset_deassert(&s->port);
1331
1332 ret = uart_add_one_port(&auart_driver, &s->port);
1333 if (ret)
1334 goto out_free_gpio_irq;
1335
1336 version = readl(s->port.membase + AUART_VERSION);
1337 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1338 (version >> 24) & 0xff,
1339 (version >> 16) & 0xff, version & 0xffff);
1340
1341 return 0;
1342
1343 out_free_gpio_irq:
1344 mxs_auart_free_gpio_irq(s);
1345 auart_port[pdev->id] = NULL;
1346 return ret;
1347 }
1348
1349 static int mxs_auart_remove(struct platform_device *pdev)
1350 {
1351 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1352
1353 uart_remove_one_port(&auart_driver, &s->port);
1354 auart_port[pdev->id] = NULL;
1355 mxs_auart_free_gpio_irq(s);
1356
1357 return 0;
1358 }
1359
1360 static struct platform_driver mxs_auart_driver = {
1361 .probe = mxs_auart_probe,
1362 .remove = mxs_auart_remove,
1363 .driver = {
1364 .name = "mxs-auart",
1365 .of_match_table = mxs_auart_dt_ids,
1366 },
1367 };
1368
1369 static int __init mxs_auart_init(void)
1370 {
1371 int r;
1372
1373 r = uart_register_driver(&auart_driver);
1374 if (r)
1375 goto out;
1376
1377 r = platform_driver_register(&mxs_auart_driver);
1378 if (r)
1379 goto out_err;
1380
1381 return 0;
1382 out_err:
1383 uart_unregister_driver(&auart_driver);
1384 out:
1385 return r;
1386 }
1387
1388 static void __exit mxs_auart_exit(void)
1389 {
1390 platform_driver_unregister(&mxs_auart_driver);
1391 uart_unregister_driver(&auart_driver);
1392 }
1393
1394 module_init(mxs_auart_init);
1395 module_exit(mxs_auart_exit);
1396 MODULE_LICENSE("GPL");
1397 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1398 MODULE_ALIAS("platform:mxs-auart");
Linux with added FPC-III support